With Simultaneous Mechanical Treatment, E.g., Chemical-mechanical Polishing (epo) Patents (Class 257/E21.23)
  • Patent number: 10312163
    Abstract: The present disclosure relates to the field of semiconductor technologies, and discloses a method for manufacturing a semiconductor apparatus. An implementation of the method may include: providing a substrate structure; depositing a dummy gate material layer on the substrate structure; performing planarization processing on the dummy gate material layer; after the planarization processing, performing, according to surface roughness of the dummy gate material layer, first etching on the dummy gate material layer by using a fluorine-containing gas; after the first etching, forming a fluorine-containing polymer layer on the dummy gate material layer; and performing second etching on the substrate structure on which the fluorine-containing polymer layer is formed, to remove the fluorine-containing polymer layer, where the second etching includes etching a surface of the dummy gate material layer.
    Type: Grant
    Filed: June 1, 2018
    Date of Patent: June 4, 2019
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventors: Hai Yang Zhang, Yan Wang
  • Patent number: 10176979
    Abstract: An amine-free composition and process for cleaning post-chemical mechanical polishing (CMP) residue and contaminants from a microelectronic device having said residue and contaminants thereon. The amine-free composition preferably includes at least one oxidizing agent, at least one complexing agent, at least one basic compound, and water and has a pH in the range from about 2.5 to about 11.5. The composition achieves highly efficacious cleaning of the post-CMP residue and contaminant material from the surface of the microelectronic device without compromising the low-k dielectric material or the copper interconnect material.
    Type: Grant
    Filed: February 15, 2013
    Date of Patent: January 8, 2019
    Assignee: Entegris, Inc.
    Inventors: Jun Liu, Jeffrey A. Barnes, Emanuel I. Cooper, Laisheng Sun, Elizabeth Thomas, Jason Chang
  • Patent number: 10128146
    Abstract: Polishing slurries for polishing semiconductor substrates are disclosed. The polishing slurry may include first and second sets of colloidal silica particles with the second set having a silica content greater than the first set.
    Type: Grant
    Filed: July 28, 2016
    Date of Patent: November 13, 2018
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Hui Wang, Vandan Tanna, Tracy Michelle Ragan, James Raymond Capstick
  • Patent number: 10118272
    Abstract: The present invention provides a method for evaluating a polishing pad by which a life of a polishing pad to polish a wafer is evaluated, the method being characterized in that a quantity of polishing residues deposited on the polishing pad is measured, and the life of the polishing pad is evaluated based on a measurement value provided by the measurement. Consequently, it is possible to provide the method for evaluating a polishing pad and the method for polishing a wafer that enable immediately evaluating the life of the polishing pad and also enable suppressing a reduction in productivity and a yield ratio at the time of polishing the wafer.
    Type: Grant
    Filed: August 22, 2014
    Date of Patent: November 6, 2018
    Assignee: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Yuki Tanaka, Kazuya Sato, Syuichi Kobayashi
  • Patent number: 10008398
    Abstract: A substrate thinning apparatus includes a chuck table capable of supporting a substrate, a rotatable grinding device which includes a wheel tip capable of grinding the substrate supported by the chuck table, and a cleaning device configured to perform synchronized cleaning of the wheel tip while the grinding device is rotated. When the substrate thinning apparatus is used, even an extremely thin semiconductor device can be fabricated with substantial reliability.
    Type: Grant
    Filed: December 5, 2016
    Date of Patent: June 26, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-il Choi, Byung-ho Kim, Hong-seok Choi
  • Patent number: 9969046
    Abstract: A polishing apparatus polishes a surface of a substrate by pressing the substrate against a polishing pad on a polishing table. The polishing apparatus is configured to control a temperature of the polishing surface of the polishing pad by blowing a gas on the polishing pad during polishing. The polishing apparatus includes a pad temperature control mechanism having at least one gas ejection nozzle for ejecting a gas toward the polishing pad and configured to blow the gas onto the polishing pad to control a temperature of the polishing pad, and an atomizer having at least one nozzle for ejecting a liquid or a mixed fluid of a gas and a liquid and configured to blow the liquid or the mixed fluid onto the polishing pad to remove foreign matters on the polishing pad. The pad temperature control mechanism and the atomizer are formed into an integral unit.
    Type: Grant
    Filed: April 27, 2015
    Date of Patent: May 15, 2018
    Assignee: EBARA CORPORATION
    Inventors: Yasuyuki Motoshima, Toru Maruyama, Hisanori Matsuo
  • Patent number: 9865477
    Abstract: The present disclosure provides a semiconductor fabrication apparatus in accordance with one embodiment. The apparatus includes a wafer stage that is operable to secure and rotate a wafer; a polish head configured to polish a backside surface of the wafer; an air bearing module configured to apply an air pressure to a front surface of the wafer; and an edge sealing unit configured to seal edges of the wafer.
    Type: Grant
    Filed: February 24, 2016
    Date of Patent: January 9, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Hung Chen, Chia-Jung Hsu, Yi-An Lin
  • Patent number: 9806025
    Abstract: An SOI semiconductor device includes a first wafer having an active semiconductor layer and a first oxide layer and a second wafer having a semiconductor substrate and a second oxide layer, the first oxide layer being bonded to the second oxide layer, and one of the first wafer and the second wafer includes a nitride layer. The nitride layer can be formed between the semiconductor substrate and the second oxide layer. A third oxide layer can be formed on the semiconductor substrate and the nitride layer is formed between the second oxide layer and the third oxide layer. The nitride layer can be formed between the active semiconductor layer and the first oxide layer. The first wafer can include a third oxide layer formed on the active semiconductor layer and the nitride layer is formed between the third oxide layer and the first oxide layer.
    Type: Grant
    Filed: December 29, 2015
    Date of Patent: October 31, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Anthony K. Stamper, Mukta G. Farooq, John A. Fitzsimmons
  • Patent number: 9765239
    Abstract: Described is a use of a chemical-mechanical polishing (CMP) composition for polishing a substrate or layer containing one or more lll-V materials, wherein the chemical-mechanical polishing (CMP) composition comprises the following components: (A) surface modified silica particles having a negative zeta potential of ?15 mV or below at a pH in the range of from 2 to 6 (B) one or more constituents selected from the group consisting of (i) substituted and unsubstituted triazoles not having an aromatic ring annealed to the triazol ring, (ii) benzimidazole, (iii) chelating agents selected from the group consisting of amino acids with two or more carboxyl groups, aliphatic carboxylic acids, and the respective salts thereof, and (iv) homopolymers and copolymers of acrylic acid, and the respective salts thereof, (C) water (D) optionally one or more further constituents, wherein the pH of the composition is in the range of from 2 to 6.
    Type: Grant
    Filed: May 6, 2014
    Date of Patent: September 19, 2017
    Assignee: BASF SE
    Inventors: Yongqing Lan, Peter Przybylski, Zhenyu Bao, Julian Proelss
  • Patent number: 9649742
    Abstract: Polishing pads having a polishing surface with continuous protrusions are described. Methods of fabricating polishing pads having a polishing surface with continuous protrusions are also described.
    Type: Grant
    Filed: January 22, 2013
    Date of Patent: May 16, 2017
    Assignee: NexPlanar Corporation
    Inventors: Paul Andre Lefevre, William C. Allison, Alexander William Simpson, Diane Scott, Ping Huang, Leslie M. Charns, James Richard Rinehart, Robert Kerprich
  • Patent number: 9633836
    Abstract: Methods of forming a dielectric layer are provided. The methods may include introducing oxygen radicals and organic silicon precursors into a chamber to form a preliminary dielectric layer on a substrate. Each of the organic silicon precursors may include a carbon bridge and a porogen such that the preliminary dielectric layer may include carbon bridges and porogens. The methods may also include removing at least some of the porogens from the preliminary dielectric layer to form a porous dielectric layer including the carbon bridges.
    Type: Grant
    Filed: May 30, 2014
    Date of Patent: April 25, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Hoon Ahn, Seung-Hyuk Choi, Kyu-Hee Han
  • Patent number: 9592585
    Abstract: System and method for CMP station cleanliness. An embodiment comprises a chemical mechanical polishing (CMP) station comprising a housing unit covering the various components of the CMP station. The CMP station further comprising various surfaces of a slurry arm shield, a slurry spray nozzle, a pad conditioning arm shield, a platen shield, a carrier head; and the interior, vertical surfaces of the housing unit. A cleaning liquid delivery system configured to dose a cleaning liquid on the various surfaces of the CMP station at set intervals.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: March 14, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Yin Lin, Teng-Chun Tsai, Wan-Chun Pan, Hsiang-Pi Chang, Chi-Yuan Chang
  • Patent number: 9490116
    Abstract: Embodiments of the disclosure provide methods and system for manufacturing film layers with minimum lithographic overlay errors on a semiconductor substrate. In one embodiment, a method for forming a film layer on a substrate includes supplying a deposition gas mixture including a silicon containing gas and a reacting gas onto a substrate disposed on a substrate support in a processing chamber, forming a plasma in the presence of the depositing gas mixture in the processing chamber, applying current to a plasma profile modulator disposed in the processing chamber while supplying the depositing gas mixture into the processing chamber, and rotating the substrate while depositing a film layer on the substrate.
    Type: Grant
    Filed: October 8, 2015
    Date of Patent: November 8, 2016
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Michael Tsiang, Praket P. Jha, Xinhai Han, Nagarajan Rajagopalan, Bok Hoen Kim, Tsutomu Kiyohara, Subbalakshmi Sreekala
  • Patent number: 9434045
    Abstract: A planarization device and a planarization method using the same are provided. The planarization device comprises a platen, a grinding pad, an operation arm, a chuck and a shielding pad. The grinding pad is disposed on the platen. The operation arm has a lower surface. The chuck rotatably is disposed on the operation arm. The shielding pad is detachably disposed on the lower surface of the operation arm.
    Type: Grant
    Filed: May 5, 2014
    Date of Patent: September 6, 2016
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Yu-Hua Yeh, Liang-Yu Hu, Tang-Tsai Chang, Ming-Tsan Lai
  • Patent number: 9281210
    Abstract: Disclosed are a chemical-mechanical polishing composition and a method of polishing a substrate. The polishing composition comprises low average particle size (e.g., 30 nm or less) wet-process ceria abrasive particles, at least one alcohol amine, and water, wherein said polishing composition has a pH of about 6. The polishing composition can be used, e.g., to polish any suitable substrate, such as a polysilicon wafer used in the semiconductor industry.
    Type: Grant
    Filed: October 10, 2013
    Date of Patent: March 8, 2016
    Assignee: Cabot Microelectronics Corporation
    Inventors: Brian Reiss, Jeffrey Dysard, Sairam Shekhar
  • Patent number: 8975179
    Abstract: The present disclosure provides a method of semiconductor fabrication including forming a dielectric layer is formed on and interposing a first feature and a second feature. A first CMP process is performed on the dielectric layer to removing the dielectric layer from a top surface of the first feature to expose an underlying layer and decreasing a thickness of the dielectric layer disposed on a top surface of the second feature such that a portion of the dielectric layer remains disposed on the top surface of the second feature. Thereafter, a second CMP process is performed which removes the dielectric layer remaining on the top surface of the second feature.
    Type: Grant
    Filed: October 18, 2011
    Date of Patent: March 10, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Che-Hao Tu, Weilun Hong, Ying-Tsung Chen, Liang-Guang Chen
  • Patent number: 8974692
    Abstract: Provided are novel chemical mechanical polishing (CMP) slurry compositions for polishing copper substrates and method of using the CMP compositions. The CMP slurry compositions deliver superior planarization with high and tunable removal rates and low defects when polishing bulk copper layers of the nanostructures of IC chips. The CMP slurry compositions also offer the high selectivity for polishing copper relative to the other materials (such as Ti, TiN, Ta, TaN, and Si), suitable for through-silicon via (TSV) CMP process which demands high copper film removal rates.
    Type: Grant
    Filed: June 27, 2013
    Date of Patent: March 10, 2015
    Assignee: Air Products and Chemicals, Inc.
    Inventors: Xiaobo Shi, Krishna Murella, James Allen Schlueter, Jae Ouk Choo
  • Patent number: 8961807
    Abstract: Disclosed are a polishing composition and method of polishing a substrate. The composition has low-load (e.g., up to about 0.1 wt. %) of abrasive particles. The polishing composition also contains water and at least one anionic surfactant. In some embodiments, the abrasive particles are alpha alumina particles (e.g., coated with organic polymer). The polishing composition can be used, e.g., to polish a substrate of weak strength such as an organic polymer. An agent for oxidizing at least one of silicon and organic polymer is included in the composition in some embodiments.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: February 24, 2015
    Assignee: Cabot Microelectronics Corporation
    Inventors: Lin Fu, Steven Grumbine
  • Patent number: 8936729
    Abstract: According to one embodiment, a planarizing method is proposed. In the planarizing method, a surface to be processed of an object to be processed including a silicon oxide film is planarized in a processing solution by bringing the surface to be processed into contact with or close proximity with the surface of a solid-state plate on which fluorine is adsorbed. The bonding energy between fluorine and the solid-state plate is lower than that between fluorine and silicon.
    Type: Grant
    Filed: September 5, 2012
    Date of Patent: January 20, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akifumi Gawase, Yukiteru Matsui
  • Patent number: 8932952
    Abstract: Disclosed is a method for polishing a silicon wafer, wherein a surface to be polished of a silicon wafer is rough polished, while supplying a polishing liquid, which is obtained by adding a water-soluble polymer to an aqueous alkaline solution that contains no free abrasive grains, to a polishing cloth. Consequently, the surface to be polished can be polished at high polishing rate and the flatness of the edge portion including roll-off and roll-up can be controlled.
    Type: Grant
    Filed: March 23, 2011
    Date of Patent: January 13, 2015
    Assignee: Sumco Corporation
    Inventors: Shinichi Ogata, Ryuichi Tanimoto, Ichiro Yamasaki, Shunsuke Mikuriya
  • Patent number: 8916473
    Abstract: An effective chemical mechanical planarization (CMP) method is provided for forming vias in silicon wafers for the fabrication of stacked devices using TSV (through-silicon via) technology. The method affords high removal rates of both metal (e.g., copper) and silicon such that a need for a grinding step prior to CMP processing may not be necessary. The method affords an approximately 1:1 Cu:Si selectivity for removal of silicon and copper under appropriate conditions and the Cu:Si selectivity is tunable by adjustment of levels of some key components.
    Type: Grant
    Filed: December 3, 2010
    Date of Patent: December 23, 2014
    Assignee: Air Products and Chemicals, Inc.
    Inventors: James Matthew Henry, Daniel Hernandez Castillo, II
  • Patent number: 8906123
    Abstract: A method and associated composition for CMP processing of noble metal-containing substrates (such as ruthenium-containing substrates) afford both high removal rates of the noble metal and are tunable with respect to rate of noble metal removal in relation to removal of other films. Low levels of an oxidizing agent containing one or more peroxy-functional group(s) can be used along with a novel ligand to effectively polish noble metal substrates.
    Type: Grant
    Filed: December 14, 2011
    Date of Patent: December 9, 2014
    Assignee: Air Products and Chemicals Inc.
    Inventor: Xiaobo Shi
  • Patent number: 8883020
    Abstract: Greater planarity is achieved between surfaces of a conductive structure and a layer within which the conductive structure resides. A portion of the conductive structure protruding above the surface of the layer is selectively oxidized, at least in part, to form an oxidized portion. The oxidized portion is then removed, at least partially, to facilitate achieving greater planarity. The protruding portions may optionally be formed by selectively disposing conductive material over the conductive structure, when that the conductive structure is initially recessed below the surface of the layer. A further embodiment includes selectively oxidizing a portion of the conductive structure below the surface of the layer, removing at least some of the oxidized portion so that an upper surface of the conductive structure is below the upper surface of the layer, and planarizing the upper surface of the layer to the upper surface of the conductive structure.
    Type: Grant
    Filed: January 30, 2013
    Date of Patent: November 11, 2014
    Assignee: Globalfoundries, Inc.
    Inventors: Xunyuan Zhang, Xiuyu Cai
  • Patent number: 8871647
    Abstract: A group III nitride substrate in one embodiment has a surface layer. The surface layer contains 3 at. % to 25 at. % of carbon and 5×1010 atoms/cm2 to 200×1010 atoms/cm2 of a p-type metal element. The group III nitride substrate has a stable surface.
    Type: Grant
    Filed: August 18, 2011
    Date of Patent: October 28, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Keiji Ishibashi
  • Patent number: 8853088
    Abstract: Methods are provided for forming gates in gate-last processes. The methods may include performing chemical mechanical polishing (CMP) on an interlayer dielectric (ILD) that is on a plurality of dummy gates, each of the plurality of dummy gates including a gate mask in an upper portion thereof, and the CMP exposing the gate mask. The methods may also include removing the gate mask by etching the gate mask. The methods may further include performing CMP on the ILD.
    Type: Grant
    Filed: September 21, 2011
    Date of Patent: October 7, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jaeseok Kim, Ho Young Kim
  • Patent number: 8828745
    Abstract: A method for manufacturing TSVs, wherein the method comprises several steps as follows: A stack structure having a substrate and an ILD layer (inter layer dielectric layer) is provided, in which an opening penetrating through the ILD layer and further extending into the substrate is formed. After an insulator layer and a metal barrier layer are formed on the stack structure and the sidewalls of the opening, a top metal layer is then formed on the stack structure to fulfill the opening. A first planarization process stopping on the barrier layer is conducted to remove a portion of the top metal layer. A second planarization process stopping on the ILD layer is subsequently conducted to remove a portion of the metal barrier layer, a portion of the insulator layer and a portion of the top metal layer, wherein the second planarization process has a polishing endpoint determined by a light interferometry or a motor current.
    Type: Grant
    Filed: July 6, 2011
    Date of Patent: September 9, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Wei-Che Tsao, Chia-Lin Hsu, Jen-Chieh Lin, Teng-Chun Tsai, Hsin-Kuo Hsu, Ya-Hsueh Hsieh, Ren-Peng Huang, Chih-Hsien Chen, Wen-Chin Lin, Yung-Lun Hsieh
  • Patent number: 8790160
    Abstract: A method for chemical mechanical polishing of a substrate comprising a germanium-antimony-tellurium chalcogenide phase change alloy (GST) using a chemical mechanical polishing composition comprising, as initial components: water; an abrasive; at least one of a phthalic acid, a phthalic anhydride, a phthalate compound and a phthalic acid derivative; a chelating agent; a poly(acrylic acid-co-maleic acid); and an oxidizing agent; wherein the chemical mechanical polishing composition facilitates a high GST removal rate with low defectivity.
    Type: Grant
    Filed: April 28, 2011
    Date of Patent: July 29, 2014
    Assignee: Rohm and Haas Electronic Materials CMP Holdings, Inc.
    Inventors: Jaeseok Lee, Yi Guo, Kancharla-Arun Kumar Reddy, Guangyun Zhang
  • Patent number: 8779479
    Abstract: An object is to provide a semiconductor device with a novel structure. A semiconductor device includes a first transistor, which includes a channel formation region provided in a substrate including a semiconductor material, impurity regions, a first gate insulating layer, a first gate electrode, and a first source electrode and a first drain electrode, and a second transistor, which includes an oxide semiconductor layer over the substrate including the semiconductor material, a second source electrode and a second drain electrode, a second gate insulating layer, and a second gate electrode. The second source electrode and the second drain electrode include an oxide region formed by oxidizing a side surface thereof, and at least one of the first gate electrode, the first source electrode, and the first drain electrode is electrically connected to at least one of the second gate electrode, the second source electrode, and the second drain electrode.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: July 15, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama
  • Patent number: 8758090
    Abstract: A polishing method includes: mounting a wafer on a fixed abrasive polishing pad located on a polishing platen; delivering a polishing slurry to the fixed abrasive polishing pad to polish the wafer; and adsorbing abrasive particles generated during the polishing process with an electrode. The electrode has a polarity opposite to a polarity of charges of the abrasive particles. A polishing device includes a polishing platen, a fixed abrasive polishing pad, a slurry pipeline and a polarity changer having an electrode. Therefore, the abrasive particles generated during the polishing process are removed, which prevents the wafer from being scratched, thereby increasing wafer yield and improving efficiency.
    Type: Grant
    Filed: December 16, 2011
    Date of Patent: June 24, 2014
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Qun Shao, Li Jiang, Mingqi Li, Qingling Wang
  • Patent number: 8748302
    Abstract: In a replacement gate approach, the dielectric material for laterally encapsulating the gate electrode structures may be provided in the form of a first interlayer dielectric material having superior gap filling capabilities and a second interlayer dielectric material that provides high etch resistivity and robustness during a planarization process. In this manner, undue material erosion upon replacing the placeholder material may be avoided, which results in reduced yield loss and superior device uniformity.
    Type: Grant
    Filed: February 21, 2012
    Date of Patent: June 10, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Christopher M. Prindle, Johannes F. Groschopf, Andreas R. Ott
  • Patent number: 8748289
    Abstract: A method for manufacturing a semiconductor device makes it possible to efficiently polish with a polishing tape a peripheral portion of a silicon substrate under polishing conditions particularly suited for a deposited film and for silicon underlying the deposited film. The method includes pressing a first polishing tape against a peripheral portion of a device substrate having a deposited film on a silicon surface while rotating the device substrate at a first rotational speed, thereby removing the deposited film lying in the peripheral portion of the device substrate and exposing the underlying silicon. A second polishing tape is pressed against the exposed silicon lying in the peripheral portion of the device substrate while rotating the device substrate at a second rotational speed, thereby polishing the silicon to a predetermined depth.
    Type: Grant
    Filed: April 23, 2013
    Date of Patent: June 10, 2014
    Assignee: Ebara Corporation
    Inventors: Masayuki Nakanishi, Tetsuji Togawa, Kenya Ito, Masaya Seki, Kenji Iwade, Takeo Kubota
  • Patent number: 8734204
    Abstract: A polishing solution for metal films that comprises an oxidizing agent, a metal oxide solubilizer, a metal corrosion preventing agent, a water-soluble polymer and water, wherein the water-soluble polymer is a copolymer of acrylic acid and methacrylic acid, the copolymerization ratio of methacrylic acid in the copolymer being 1-20 mol % based on the total of acrylic acid and methacrylic acid.
    Type: Grant
    Filed: April 13, 2009
    Date of Patent: May 27, 2014
    Assignee: Hitachi Chemical Company, Ltd.
    Inventors: Kouji Haga, Masato Fukasawa, Hiroshi Nakagawa, Kouji Mishima
  • Patent number: 8734665
    Abstract: A composition and a method for chemical mechanical polishing. The composition includes a surfactant anion an alkyl alcohol, a controlled amount of chloride ion source and a diluent. The composition further includes abrasive particles and an oxidizer. The method includes providing the composition on a surface to be polished and polishing the surface by contacting the surface with a polishing pad.
    Type: Grant
    Filed: October 12, 2011
    Date of Patent: May 27, 2014
    Assignee: International Business Machines Corporation
    Inventors: Graham M. Bates, Michael T. Brigham, Joseph K. Comeau, Jason P. Ritter, Eva A. Shah, Matthew T. Tiersch, Eric J. White
  • Patent number: 8728942
    Abstract: Mirror-polishing a front surface of a silicon wafer using polishing liquid composed of an abrasive grain-free alkaline solution including water-soluble polymers simplifies a polishing process, thus leading to an increase in productivity and a reduction in cost, and reduces the density of LPDs attributable to processing and occurring in the front surface of a mirror-polished wafer, thus improving the surface roughness of the wafer front surface.
    Type: Grant
    Filed: August 20, 2010
    Date of Patent: May 20, 2014
    Assignee: Sumico Corporation
    Inventors: Shinichi Ogata, Kazushige Takaishi, Hironori Nishimura, Shigeru Okuuchi, Shunsuke Mikuriya, Yuichi Nakayoshi
  • Publication number: 20140124900
    Abstract: A through-substrate via (TSV) die includes a substrate having a top side semiconductor surface having active circuitry therein including a plurality of transistors functionally connected and a bottom side surface, wherein the layers on the top side semiconductor surface exert a net tensile stress to the top side semiconductor surface. A plurality of TSVs which extend from the top side semiconductor surface to TSV tips which protrude from the bottom side surface include an inner metal core surrounded by a dielectric liner that forms an outer edge for the TSVs. A dielectric stack is on the bottom side surface lateral to the TSV tips including a compressive dielectric layer and a tensile dielectric layer on the compressive dielectric layer.
    Type: Application
    Filed: November 2, 2012
    Publication date: May 8, 2014
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: JEFFREY ALAN WEST, MARGARET SIMMONS-MATTHEWS, RAJESH TIWARI
  • Publication number: 20140117419
    Abstract: A method and device are provided for etching and replacing silicon fins in connection with a FinFET integration process. Embodiments include providing a first plurality and a second plurality of silicon fins on a silicon wafer with an oxide between adjacent silicon fins; forming a first nitride liner on an upper surface of the first plurality of silicon fins and the oxide therebetween; etching the second plurality of silicon fins, forming trenches; removing the first nitride liner; depositing a second nitride liner on an upper surface of the first plurality of silicon fins and the oxide therebetween and in the trenches; removing the second nitride liner down to the upper surface of the first plurality of silicon fins; and recessing the oxide.
    Type: Application
    Filed: October 30, 2012
    Publication date: May 1, 2014
    Applicant: GLOBALFOUNDRIES Inc.
    Inventor: Werner JUENGLING
  • Patent number: 8709915
    Abstract: A method of manufacturing a semiconductor device comprises: forming a protective film so as to cover at least a side edge of a substrate; forming a trench, which is annular in shape when viewed oppositely to a first principal surface of the substrate, on the first principal surface by etching using a photoresist pattern; and forming an insulating film so as to fill the trench, to form an insulating ring.
    Type: Grant
    Filed: July 23, 2012
    Date of Patent: April 29, 2014
    Inventor: Takeo Tsukamoto
  • Patent number: 8703004
    Abstract: According to one embodiment, a method is disclosed for chemical planarization. The method can include forming a surface layer on a to-be-processed film having irregularity. The surface layer binds to or adsorbs onto the to-be-processed film along the irregularity to suppress dissolution of the to-be-processed film. The method can include planarizing the to-be-processed film in a processing solution dissolving the to-be-processed film, by rotating the to-be-processed film and a processing body while the to-be-processed film contacting the processing body via the surface layer, removing the surface layer on convex portions of the irregularity while leaving the surface layer on concave portions of the irregularity and making dissolution degree of the convex portions larger than dissolution degree of the concave portions.
    Type: Grant
    Filed: March 16, 2012
    Date of Patent: April 22, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yukiteru Matsui, Masako Kodera, Hiroshi Tomita, Gaku Minamihaba, Akifumi Gawase
  • Patent number: 8702472
    Abstract: A polishing composition contains at least abrasive grains and water and is used in polishing an object to be polished. The abrasive grains are selected so as to satisfy the relationship X1×Y1?0 and the relationship X2×Y2>0, where X1 [mV] represents the zeta potential of the abrasive grains measured during polishing of the object by using the polishing composition, Y1 [mV] represents the zeta potential of the object measured during polishing of the object by using the polishing composition, X2 [mV] represents the zeta potential of the abrasive grains measured during washing of the object after polishing, and Y2 [mV] represents the zeta potential of the object measured during washing of the object after polishing. The abrasive grains are preferably of silicon oxide, aluminum oxide, cerium oxide, zirconium oxide, silicon carbide, or diamond. The object is preferably of a nickel-containing alloy, silicon oxide, or aluminum oxide.
    Type: Grant
    Filed: March 8, 2011
    Date of Patent: April 22, 2014
    Assignee: Fujimi Incorporated
    Inventors: Hitoshi Morinaga, Kazusei Tamai, Hiroshi Asano
  • Publication number: 20140091477
    Abstract: A method for forming a field-effect transistor with a raised drain structure is disclosed. The method includes depositing a low-k inter-metal layer over a semiconductor substrate, depositing a porogen-containing low-k layer over the low-k inter-metal layer, and etching a space for the via through the low-k inter-metal layer and the porogen-containing low-k layer. The method further includes depositing a metal layer, a portion of the metal layer filling the space for the via, another portion of the metal layer being over the porogen-containing low-layer, removing the portion of the metal layer over the porogen-containing layer by a CMP process, and curing the porogen-containing low-k layer to form a cured low-k layer.
    Type: Application
    Filed: September 28, 2012
    Publication date: April 3, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yung-Hsu Wu, Shih-Kang Fu, Hsin-Chieh Yao, Chia-Min Lin, Hsiang-Huan Lee, Chung-Ju Lee, Hai-Ching Chen, Shau-Lin Shue
  • Publication number: 20140080304
    Abstract: An integrated tool to reduce defects in manufacturing a semiconductor device by reducing queue times during a manufacturing process. The integrated tool may include at least one a polishing tool comprising at least one polishing module and at least one deposition tool comprising at least one deposition chamber. At least one pump-down chamber may connect the polishing tool to the deposition tool. The at least one pump-down chamber includes a passage through which the semiconductor device is passed. Defects in the semiconductor device are reduced by reducing the queue time at various stages of the fabrication process.
    Type: Application
    Filed: September 14, 2012
    Publication date: March 20, 2014
    Applicant: STMICROELECTRONICS, INC.
    Inventor: John H. Zhang
  • Patent number: 8674382
    Abstract: A semiconductor light emitting device (10) comprises a semiconductor structure (12) comprising a first body (14) of a first semiconductor material (in this case Ge) comprising a first region of a first doping kind (in this case n) and a second body (18) of a second semiconductor material (in this case Si) comprising a first region of a second doping kind (in this case p). The structure comprises a junction region (15) comprising a first heterojunction (16) formed between the first body (14) and the second body (18) and a pn junction (17) formed between regions of the structure of the first and second doping kinds respectively. A biasing arrangement (20) is connected to the structure for, in use, reverse biasing the pn junction, thereby to cause emission of light.
    Type: Grant
    Filed: January 30, 2009
    Date of Patent: March 18, 2014
    Assignee: Insiava (Pty) Limited
    Inventors: Lukas Willem Snyman, Monuko Du Plessis
  • Publication number: 20140057439
    Abstract: A method of forming interlayer dielectric comprising the steps of forming a first undoped layer, forming in-situ and sequentially a doped layer and a second undoped layer on the first undoped layer, and planarizing the second undoped layer.
    Type: Application
    Filed: August 21, 2012
    Publication date: February 27, 2014
    Inventors: JIANDONG ZHANG, Han Chuan Fang, jianjun Zhang, Xiaowei Shu, MIAO ZHANG
  • Publication number: 20140042491
    Abstract: This description relates to a gate electrode of a field effect transistor. An exemplary structure for a field effect transistor includes a substrate; a gate electrode over the substrate including a first top surface and a sidewall; a source/drain (S/D) region at least partially disposed in the substrate on one side of the gate electrode; a spacer on the sidewall distributed between the gate electrode and the S/D region; and a contact etch stop layer (CESL) adjacent to the spacer and further comprising a portion extending over the S/D region, wherein the portion has a second top surface substantially coplanar with the first top surface.
    Type: Application
    Filed: August 10, 2012
    Publication date: February 13, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Neng-Kuo CHEN, Clement Hsingjen WANN, Yi-An LIN, Chun-Wei CHANG, Sey-Ping SUN
  • Patent number: 8647986
    Abstract: A semiconductor process includes the following steps. A first gate structure and a second gate structure are formed on a substrate, wherein the top of the first gate structure includes a cap layer, so that the vertical height of the first gate structure is higher than the vertical height of the second gate structure. An interdielectric layer is formed on the substrate. A first chemical mechanical polishing process is performed to expose the top surface of the cap layer. A second chemical mechanical polishing process is performed to expose the top surface of the second gate structure or an etching process is performed to remove the interdielectric layer located on the second gate structure. A second chemical mechanical polishing process is then performed to remove the cap layer.
    Type: Grant
    Filed: August 30, 2011
    Date of Patent: February 11, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Po-Cheng Huang, Teng-Chun Tsai, Chia-Lin Hsu, Chun-Wei Hsu, Yen-Ming Chen, Chih-Hsun Lin, Chang-Hung Kung
  • Patent number: 8647965
    Abstract: A method of producing a radiographic image detector includes: preparing a thin-film transistor substrate comprising an insulating substrate and a thin-film transistor that is disposed on a surface of the insulating substrate at a first side; attaching, to the thin-film transistor substrate, a protective member comprising a protective member support and an adhesive layer that includes conductive particles and that is disposed on the protective member support, such that the adhesive layer and a surface of the thin-film transistor substrate at the first side contact each other; polishing a surface of the thin-film transistor substrate at a second side opposite to the first side, after the attaching of the protective member; separating and removing the protective member from the thin-film transistor substrate after the polishing; and providing a scintillator layer on a surface of the thin-film transistor substrate at the first side, after the removing of the protective member.
    Type: Grant
    Filed: December 14, 2010
    Date of Patent: February 11, 2014
    Assignee: FUJIFILM Corporation
    Inventor: Keiichiro Sato
  • Publication number: 20140038413
    Abstract: A dielectric layer is deposited on a working surface of a substrate, wherein the dielectric layer contains or consists of a dielectric polymer. The dielectric layer is partially cured. A portion of the partially cured dielectric layer is removed using a chemical mechanical polishing process. Then the curing of remnant portions of the partially cured dielectric layer is continued to form a dielectric structure. The partially cured dielectric layer shows high removal rates during chemical mechanical polishing. With remnant portions of the dielectric layer provided in cavities, high volume insulating structures can be provided in an efficient manner.
    Type: Application
    Filed: August 3, 2012
    Publication date: February 6, 2014
    Applicant: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventors: Gerhard Schmidt, Daniel Schloegl, Marcella Johanna Hartl, Philipp Sebastian Koch, Roland Strasser
  • Patent number: 8637403
    Abstract: A method of manufacturing a semiconductor structure includes varying local chemical mechanical polishing (CMP) abrading rates of an insulator film by selectively varying a carbon content of the insulator film.
    Type: Grant
    Filed: December 12, 2011
    Date of Patent: January 28, 2014
    Assignee: International Business Machines Corporation
    Inventors: Yoba Amoah, Graham M. Bates, Joseph P. Hasselbach, Thomas L. McDevitt, Eva A. Shah
  • Publication number: 20140024216
    Abstract: The present invention provides chemical-mechanical polishing (CMP) compositions suitable for polishing a substrate comprising a germanium-antimony-tellurium (GST) alloy. The CMP compositions of the present invention are aqueous slurries comprising a particulate abrasive, a water-soluble surface active agent, a complexing agent, and a corrosion inhibitor. The ionic character of the surface active material (e.g., cationic, anionic, or nonionic) is selected based on the zeta potential of the particulate abrasive. A CMP method for polishing a GST alloy-containing substrate utilizing the composition is also disclosed.
    Type: Application
    Filed: July 17, 2012
    Publication date: January 23, 2014
    Inventors: Matthias STENDER, Glenn WHITENER, Chul Woo NAM
  • Publication number: 20140015107
    Abstract: Closed loop control may be used to improve uniformity of within wafer uniformity using chemical mechanical planarization. For example, closed loop control may be used to determine a control profile for a chemical mechanical planarization process to more uniformly and consistently achieve the desired extent of variation of within wafer uniformity of a semiconductor wafer.
    Type: Application
    Filed: July 12, 2012
    Publication date: January 16, 2014
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Ching-Kun Chen, Chun-Fu Chen, Chin-Ta Su