Abstract: A method of processing a substrate includes subjecting a substrate to processing that modifies a thickness of an outer layer of the substrate, measuring a spectrum of light reflected from the substrate during processing, reducing the dimensionality of the measured spectrum to generate a plurality of component values, generating a characterizing value using an artificial neural network, and determining at least one of whether to halt processing of the substrate or an adjustment for a processing parameter based on the characterizing value. The artificial neural network has a plurality of input nodes to receive the plurality of component values, an output node to output the characterizing value, and a plurality of hidden nodes connecting the input nodes to the output node.

Abstract: A method of cleaning wafer-cleaning brushes includes passing a wafer having a first polished main side and an opposing unpolished backside between a pair of substantially cylindrical shaped wafer-cleaning brushes are rotated about an axial direction of the brushes while passing the wafer between the pair of wafer-cleaning brushes. A cleaning solution is applied to the brushes while passing the wafer between the pair of wafer-cleaning brushes. While passing between the pair of brushes, the first polished main side of the wafer faces a first direction, the first direction is an opposite direction to which a polished side of a production wafer faces during a subsequent polished wafer cleaning operation. The substantially cylindrical shaped wafer-cleaning brushes include a plurality of protrusions on an external surface of the brushes, and the brushes contact the wafer at least a portion of time the wafer is passing between the pair of brushes.

Abstract: A substrate processing apparatus includes a polishing section and a transport section. The polishing section has a first polishing unit, a second polishing unit, and a transport mechanism. The first polishing unit has a first polishing apparatus and a second polishing apparatus. The second polishing unit has a third polishing apparatus and a fourth polishing apparatus. Each of the first to fourth polishing apparatuses has a polishing table to which a polishing pad is mounted, a top ring, and auxiliary units that perform a process on the polishing pad during polishing. Around the polishing table, a pair of auxiliary unit mounting units for mounting the respective auxiliary units in a left-right switchable manner with respect to a straight line connecting a swing center of the top ring and a center of rotation of the polishing table is provided at respective positions symmetrical with respect to the straight line.

Abstract: A slurry containing abrasive grains and a liquid medium, in which the abrasive grains include first particles and second particles in contact with the first particles, the first particles contain cerium oxide, the second particles contain a cerium compound, and an Rsp value calculated by Formula (1) below is 1.60 or more: Rsp=(Tb/Tav)?1??(1) [in the formula, Tav represents a relaxation time (unit: ms) obtained by pulsed NMR measurement of the slurry in a case where a content of the abrasive grains is 2.0% by mass, and Tb represents a relaxation time (unit: ms) obtained by pulsed NMR measurement of a supernatant solution obtained when the slurry is subjected to centrifugal separation for 50 minutes at a centrifugal acceleration of 2.36×105 G in a case where the content of the abrasive grains is 2.0% by mass.

Abstract: A slurry containing abrasive grains and a liquid medium, in which the abrasive grains include first particles and second particles in contact with the first particles, the first particles contain cerium oxide, the second particles contain a cerium compound, and an Rsp value calculated by Formula (1) below is 1.60 or more: Rsp=(Tb/Tav)?1??(1) [in the formula, Tav represents a relaxation time (unit: ms) obtained by pulsed NMR measurement of the slurry in a case where a content of the abrasive grains is 2.0% by mass, and Tb represents a relaxation time (unit: ms) obtained by pulsed NMR measurement of a supernatant solution obtained when the slurry is subjected to centrifugal separation for 50 minutes at a centrifugal acceleration of 2.36×105 G in a case where the content of the abrasive grains is 2.0% by mass.

Abstract: A non-transitory computer-readable storage medium storing a program of stretching operation of an elastic membrane which can enhance elasticity of an elastic membrane in a short time without using a dummy wafer is disclosed. The non-transitory computer-readable storage medium storing a program of stretching operation of an elastic membrane in a substrate holding apparatus, the program causes a computer to perform stretching operation of supplying a pressurized fluid to a pressure chamber formed by the elastic membrane and allowing the pressure chamber to be open to the atmosphere a predetermined number of times by a pressure regulating device in a state where the substrate holding apparatus is positioned above a polishing table during standby operation of a polishing apparatus.

Abstract: Provided are self-aligned double patterning methods including feature trimming. The SADP process is performed in a single batch processing chamber in which the substrate is laterally moved between sections of the processing chamber separated by gas curtains so that each section independently has a process condition.

Abstract: A load port including: a tabular portion which constitutes a part of a wall surface of a wafer carrying chamber and has an opening through which the wafer carrying chamber is opened; a mounting table on which a wafer storage container is mounted; a door section which can open and close the opening; a sucking tool which can suck and hold a lid; a latch which can fix and unfix a container main body and lid; and a latch driving mechanism storage section which stores a latch driving mechanism therein, load port being configured to enable setting an air pressure in latch driving mechanism storage section to be equal to the air pressure in a clean room or lower than the air pressure in clean room. Consequently, it is possible to provide the load port and a method for carrying wafers which can prevent dust from adhering to the wafers.

Abstract: According to one example, a method includes epitaxially growing first portions of a plurality of elongated semiconductor structures on a semiconductor substrate, the elongated semiconductor structures running perpendicular to the substrate. The method further includes forming a gate layer on the substrate, the gate layer contacting the elongated semiconductor structures. The method further includes performing a planarization process on the gate layer and the elongated semiconductor structures, and epitaxially growing second portions of the plurality of elongated semiconductor structures, the second portions comprising a different material than the first portions.

Abstract: Provided is a management system associated with a manufacturing line including one or more facilities. Each of the facilities is configured to process each workpiece according to order information. The management system includes: a collecting means for collecting event information about a process that takes place in each of the facilities; a classifying means for classifying, on the basis of a generation source and content of each piece of event information, the event information collected by the collecting means, into sets of event information generated due to the same workpiece; a generation means for generating data which represents process circumstances for each workpiece on the basis of the event information belonging to each of the sets classified by the classifying means; and a visualizing means for visualizing process progression circumstances for each workpiece processed according to the order information, on the basis of the data generated by the generating means.

Abstract: Provided are a chemical mechanical polishing apparatus and a control method thereof. The chemical mechanical polishing apparatus includes a plurality of polishing platens provided with a polishing pad on an upper surface thereof, and a polishing platen transferring unit for transferring the plurality of polishing platens to different process positions according to a predetermined process sequence. Here, different processes are performed at different process positions.

Abstract: Before a first surface of a substrate is polished using a chemical mechanical process, the substrate is transferred to a modification station. The substrate comprises a side wall connected with the first surface at an edge and a second surface opposite to the first surface and also connected to the side wall. The first surface is substantially flat. The side wall is substantially perpendicular to the first surface. The edge of the substrate is modified at the modification station by removing material from a region of the first surface. The side wall of the substrate is a boundary of the region. The modified edge comprises a modified first surface that tapers within the region towards the second surface. The side wall remains substantially perpendicular to the first surface.

Abstract: The present disclosure relates to the field of semiconductor technologies, and discloses a method for manufacturing a semiconductor apparatus. An implementation of the method may include: providing a substrate structure; depositing a dummy gate material layer on the substrate structure; performing planarization processing on the dummy gate material layer; after the planarization processing, performing, according to surface roughness of the dummy gate material layer, first etching on the dummy gate material layer by using a fluorine-containing gas; after the first etching, forming a fluorine-containing polymer layer on the dummy gate material layer; and performing second etching on the substrate structure on which the fluorine-containing polymer layer is formed, to remove the fluorine-containing polymer layer, where the second etching includes etching a surface of the dummy gate material layer.

Abstract: An amine-free composition and process for cleaning post-chemical mechanical polishing (CMP) residue and contaminants from a microelectronic device having said residue and contaminants thereon. The amine-free composition preferably includes at least one oxidizing agent, at least one complexing agent, at least one basic compound, and water and has a pH in the range from about 2.5 to about 11.5. The composition achieves highly efficacious cleaning of the post-CMP residue and contaminant material from the surface of the microelectronic device without compromising the low-k dielectric material or the copper interconnect material.

Abstract: Polishing slurries for polishing semiconductor substrates are disclosed. The polishing slurry may include first and second sets of colloidal silica particles with the second set having a silica content greater than the first set.

Abstract: The present invention provides a method for evaluating a polishing pad by which a life of a polishing pad to polish a wafer is evaluated, the method being characterized in that a quantity of polishing residues deposited on the polishing pad is measured, and the life of the polishing pad is evaluated based on a measurement value provided by the measurement. Consequently, it is possible to provide the method for evaluating a polishing pad and the method for polishing a wafer that enable immediately evaluating the life of the polishing pad and also enable suppressing a reduction in productivity and a yield ratio at the time of polishing the wafer.

Abstract: A substrate thinning apparatus includes a chuck table capable of supporting a substrate, a rotatable grinding device which includes a wheel tip capable of grinding the substrate supported by the chuck table, and a cleaning device configured to perform synchronized cleaning of the wheel tip while the grinding device is rotated. When the substrate thinning apparatus is used, even an extremely thin semiconductor device can be fabricated with substantial reliability.

Abstract: A polishing apparatus polishes a surface of a substrate by pressing the substrate against a polishing pad on a polishing table. The polishing apparatus is configured to control a temperature of the polishing surface of the polishing pad by blowing a gas on the polishing pad during polishing. The polishing apparatus includes a pad temperature control mechanism having at least one gas ejection nozzle for ejecting a gas toward the polishing pad and configured to blow the gas onto the polishing pad to control a temperature of the polishing pad, and an atomizer having at least one nozzle for ejecting a liquid or a mixed fluid of a gas and a liquid and configured to blow the liquid or the mixed fluid onto the polishing pad to remove foreign matters on the polishing pad. The pad temperature control mechanism and the atomizer are formed into an integral unit.

Abstract: The present disclosure provides a semiconductor fabrication apparatus in accordance with one embodiment. The apparatus includes a wafer stage that is operable to secure and rotate a wafer; a polish head configured to polish a backside surface of the wafer; an air bearing module configured to apply an air pressure to a front surface of the wafer; and an edge sealing unit configured to seal edges of the wafer.

Abstract: An SOI semiconductor device includes a first wafer having an active semiconductor layer and a first oxide layer and a second wafer having a semiconductor substrate and a second oxide layer, the first oxide layer being bonded to the second oxide layer, and one of the first wafer and the second wafer includes a nitride layer. The nitride layer can be formed between the semiconductor substrate and the second oxide layer. A third oxide layer can be formed on the semiconductor substrate and the nitride layer is formed between the second oxide layer and the third oxide layer. The nitride layer can be formed between the active semiconductor layer and the first oxide layer. The first wafer can include a third oxide layer formed on the active semiconductor layer and the nitride layer is formed between the third oxide layer and the first oxide layer.

Abstract: Described is a use of a chemical-mechanical polishing (CMP) composition for polishing a substrate or layer containing one or more lll-V materials, wherein the chemical-mechanical polishing (CMP) composition comprises the following components: (A) surface modified silica particles having a negative zeta potential of ?15 mV or below at a pH in the range of from 2 to 6 (B) one or more constituents selected from the group consisting of (i) substituted and unsubstituted triazoles not having an aromatic ring annealed to the triazol ring, (ii) benzimidazole, (iii) chelating agents selected from the group consisting of amino acids with two or more carboxyl groups, aliphatic carboxylic acids, and the respective salts thereof, and (iv) homopolymers and copolymers of acrylic acid, and the respective salts thereof, (C) water (D) optionally one or more further constituents, wherein the pH of the composition is in the range of from 2 to 6.

Abstract: Polishing pads having a polishing surface with continuous protrusions are described. Methods of fabricating polishing pads having a polishing surface with continuous protrusions are also described.

Abstract: Methods of forming a dielectric layer are provided. The methods may include introducing oxygen radicals and organic silicon precursors into a chamber to form a preliminary dielectric layer on a substrate. Each of the organic silicon precursors may include a carbon bridge and a porogen such that the preliminary dielectric layer may include carbon bridges and porogens. The methods may also include removing at least some of the porogens from the preliminary dielectric layer to form a porous dielectric layer including the carbon bridges.

Abstract: System and method for CMP station cleanliness. An embodiment comprises a chemical mechanical polishing (CMP) station comprising a housing unit covering the various components of the CMP station. The CMP station further comprising various surfaces of a slurry arm shield, a slurry spray nozzle, a pad conditioning arm shield, a platen shield, a carrier head; and the interior, vertical surfaces of the housing unit. A cleaning liquid delivery system configured to dose a cleaning liquid on the various surfaces of the CMP station at set intervals.

Abstract: Embodiments of the disclosure provide methods and system for manufacturing film layers with minimum lithographic overlay errors on a semiconductor substrate. In one embodiment, a method for forming a film layer on a substrate includes supplying a deposition gas mixture including a silicon containing gas and a reacting gas onto a substrate disposed on a substrate support in a processing chamber, forming a plasma in the presence of the depositing gas mixture in the processing chamber, applying current to a plasma profile modulator disposed in the processing chamber while supplying the depositing gas mixture into the processing chamber, and rotating the substrate while depositing a film layer on the substrate.

Abstract: A planarization device and a planarization method using the same are provided. The planarization device comprises a platen, a grinding pad, an operation arm, a chuck and a shielding pad. The grinding pad is disposed on the platen. The operation arm has a lower surface. The chuck rotatably is disposed on the operation arm. The shielding pad is detachably disposed on the lower surface of the operation arm.

Abstract: Disclosed are a chemical-mechanical polishing composition and a method of polishing a substrate. The polishing composition comprises low average particle size (e.g., 30 nm or less) wet-process ceria abrasive particles, at least one alcohol amine, and water, wherein said polishing composition has a pH of about 6. The polishing composition can be used, e.g., to polish any suitable substrate, such as a polysilicon wafer used in the semiconductor industry.

Abstract: The present disclosure provides a method of semiconductor fabrication including forming a dielectric layer is formed on and interposing a first feature and a second feature. A first CMP process is performed on the dielectric layer to removing the dielectric layer from a top surface of the first feature to expose an underlying layer and decreasing a thickness of the dielectric layer disposed on a top surface of the second feature such that a portion of the dielectric layer remains disposed on the top surface of the second feature. Thereafter, a second CMP process is performed which removes the dielectric layer remaining on the top surface of the second feature.

Abstract: Provided are novel chemical mechanical polishing (CMP) slurry compositions for polishing copper substrates and method of using the CMP compositions. The CMP slurry compositions deliver superior planarization with high and tunable removal rates and low defects when polishing bulk copper layers of the nanostructures of IC chips. The CMP slurry compositions also offer the high selectivity for polishing copper relative to the other materials (such as Ti, TiN, Ta, TaN, and Si), suitable for through-silicon via (TSV) CMP process which demands high copper film removal rates.

Abstract: Disclosed are a polishing composition and method of polishing a substrate. The composition has low-load (e.g., up to about 0.1 wt. %) of abrasive particles. The polishing composition also contains water and at least one anionic surfactant. In some embodiments, the abrasive particles are alpha alumina particles (e.g., coated with organic polymer). The polishing composition can be used, e.g., to polish a substrate of weak strength such as an organic polymer. An agent for oxidizing at least one of silicon and organic polymer is included in the composition in some embodiments.

Abstract: According to one embodiment, a planarizing method is proposed. In the planarizing method, a surface to be processed of an object to be processed including a silicon oxide film is planarized in a processing solution by bringing the surface to be processed into contact with or close proximity with the surface of a solid-state plate on which fluorine is adsorbed. The bonding energy between fluorine and the solid-state plate is lower than that between fluorine and silicon.

Abstract: Disclosed is a method for polishing a silicon wafer, wherein a surface to be polished of a silicon wafer is rough polished, while supplying a polishing liquid, which is obtained by adding a water-soluble polymer to an aqueous alkaline solution that contains no free abrasive grains, to a polishing cloth. Consequently, the surface to be polished can be polished at high polishing rate and the flatness of the edge portion including roll-off and roll-up can be controlled.

Abstract: An effective chemical mechanical planarization (CMP) method is provided for forming vias in silicon wafers for the fabrication of stacked devices using TSV (through-silicon via) technology. The method affords high removal rates of both metal (e.g., copper) and silicon such that a need for a grinding step prior to CMP processing may not be necessary. The method affords an approximately 1:1 Cu:Si selectivity for removal of silicon and copper under appropriate conditions and the Cu:Si selectivity is tunable by adjustment of levels of some key components.

Abstract: A method and associated composition for CMP processing of noble metal-containing substrates (such as ruthenium-containing substrates) afford both high removal rates of the noble metal and are tunable with respect to rate of noble metal removal in relation to removal of other films. Low levels of an oxidizing agent containing one or more peroxy-functional group(s) can be used along with a novel ligand to effectively polish noble metal substrates.

Abstract: Greater planarity is achieved between surfaces of a conductive structure and a layer within which the conductive structure resides. A portion of the conductive structure protruding above the surface of the layer is selectively oxidized, at least in part, to form an oxidized portion. The oxidized portion is then removed, at least partially, to facilitate achieving greater planarity. The protruding portions may optionally be formed by selectively disposing conductive material over the conductive structure, when that the conductive structure is initially recessed below the surface of the layer. A further embodiment includes selectively oxidizing a portion of the conductive structure below the surface of the layer, removing at least some of the oxidized portion so that an upper surface of the conductive structure is below the upper surface of the layer, and planarizing the upper surface of the layer to the upper surface of the conductive structure.

Abstract: A group III nitride substrate in one embodiment has a surface layer. The surface layer contains 3 at. % to 25 at. % of carbon and 5×1010 atoms/cm2 to 200×1010 atoms/cm2 of a p-type metal element. The group III nitride substrate has a stable surface.

Abstract: Methods are provided for forming gates in gate-last processes. The methods may include performing chemical mechanical polishing (CMP) on an interlayer dielectric (ILD) that is on a plurality of dummy gates, each of the plurality of dummy gates including a gate mask in an upper portion thereof, and the CMP exposing the gate mask. The methods may also include removing the gate mask by etching the gate mask. The methods may further include performing CMP on the ILD.

Abstract: A method for manufacturing TSVs, wherein the method comprises several steps as follows: A stack structure having a substrate and an ILD layer (inter layer dielectric layer) is provided, in which an opening penetrating through the ILD layer and further extending into the substrate is formed. After an insulator layer and a metal barrier layer are formed on the stack structure and the sidewalls of the opening, a top metal layer is then formed on the stack structure to fulfill the opening. A first planarization process stopping on the barrier layer is conducted to remove a portion of the top metal layer. A second planarization process stopping on the ILD layer is subsequently conducted to remove a portion of the metal barrier layer, a portion of the insulator layer and a portion of the top metal layer, wherein the second planarization process has a polishing endpoint determined by a light interferometry or a motor current.

Abstract: A method for chemical mechanical polishing of a substrate comprising a germanium-antimony-tellurium chalcogenide phase change alloy (GST) using a chemical mechanical polishing composition comprising, as initial components: water; an abrasive; at least one of a phthalic acid, a phthalic anhydride, a phthalate compound and a phthalic acid derivative; a chelating agent; a poly(acrylic acid-co-maleic acid); and an oxidizing agent; wherein the chemical mechanical polishing composition facilitates a high GST removal rate with low defectivity.

Abstract: An object is to provide a semiconductor device with a novel structure. A semiconductor device includes a first transistor, which includes a channel formation region provided in a substrate including a semiconductor material, impurity regions, a first gate insulating layer, a first gate electrode, and a first source electrode and a first drain electrode, and a second transistor, which includes an oxide semiconductor layer over the substrate including the semiconductor material, a second source electrode and a second drain electrode, a second gate insulating layer, and a second gate electrode. The second source electrode and the second drain electrode include an oxide region formed by oxidizing a side surface thereof, and at least one of the first gate electrode, the first source electrode, and the first drain electrode is electrically connected to at least one of the second gate electrode, the second source electrode, and the second drain electrode.

Abstract: A polishing method includes: mounting a wafer on a fixed abrasive polishing pad located on a polishing platen; delivering a polishing slurry to the fixed abrasive polishing pad to polish the wafer; and adsorbing abrasive particles generated during the polishing process with an electrode. The electrode has a polarity opposite to a polarity of charges of the abrasive particles. A polishing device includes a polishing platen, a fixed abrasive polishing pad, a slurry pipeline and a polarity changer having an electrode. Therefore, the abrasive particles generated during the polishing process are removed, which prevents the wafer from being scratched, thereby increasing wafer yield and improving efficiency.

Abstract: In a replacement gate approach, the dielectric material for laterally encapsulating the gate electrode structures may be provided in the form of a first interlayer dielectric material having superior gap filling capabilities and a second interlayer dielectric material that provides high etch resistivity and robustness during a planarization process. In this manner, undue material erosion upon replacing the placeholder material may be avoided, which results in reduced yield loss and superior device uniformity.

Abstract: A method for manufacturing a semiconductor device makes it possible to efficiently polish with a polishing tape a peripheral portion of a silicon substrate under polishing conditions particularly suited for a deposited film and for silicon underlying the deposited film. The method includes pressing a first polishing tape against a peripheral portion of a device substrate having a deposited film on a silicon surface while rotating the device substrate at a first rotational speed, thereby removing the deposited film lying in the peripheral portion of the device substrate and exposing the underlying silicon. A second polishing tape is pressed against the exposed silicon lying in the peripheral portion of the device substrate while rotating the device substrate at a second rotational speed, thereby polishing the silicon to a predetermined depth.

Abstract: A polishing solution for metal films that comprises an oxidizing agent, a metal oxide solubilizer, a metal corrosion preventing agent, a water-soluble polymer and water, wherein the water-soluble polymer is a copolymer of acrylic acid and methacrylic acid, the copolymerization ratio of methacrylic acid in the copolymer being 1-20 mol % based on the total of acrylic acid and methacrylic acid.

Abstract: A composition and a method for chemical mechanical polishing. The composition includes a surfactant anion an alkyl alcohol, a controlled amount of chloride ion source and a diluent. The composition further includes abrasive particles and an oxidizer. The method includes providing the composition on a surface to be polished and polishing the surface by contacting the surface with a polishing pad.

Abstract: Mirror-polishing a front surface of a silicon wafer using polishing liquid composed of an abrasive grain-free alkaline solution including water-soluble polymers simplifies a polishing process, thus leading to an increase in productivity and a reduction in cost, and reduces the density of LPDs attributable to processing and occurring in the front surface of a mirror-polished wafer, thus improving the surface roughness of the wafer front surface.

Abstract: A through-substrate via (TSV) die includes a substrate having a top side semiconductor surface having active circuitry therein including a plurality of transistors functionally connected and a bottom side surface, wherein the layers on the top side semiconductor surface exert a net tensile stress to the top side semiconductor surface. A plurality of TSVs which extend from the top side semiconductor surface to TSV tips which protrude from the bottom side surface include an inner metal core surrounded by a dielectric liner that forms an outer edge for the TSVs. A dielectric stack is on the bottom side surface lateral to the TSV tips including a compressive dielectric layer and a tensile dielectric layer on the compressive dielectric layer.

Abstract: A method and device are provided for etching and replacing silicon fins in connection with a FinFET integration process. Embodiments include providing a first plurality and a second plurality of silicon fins on a silicon wafer with an oxide between adjacent silicon fins; forming a first nitride liner on an upper surface of the first plurality of silicon fins and the oxide therebetween; etching the second plurality of silicon fins, forming trenches; removing the first nitride liner; depositing a second nitride liner on an upper surface of the first plurality of silicon fins and the oxide therebetween and in the trenches; removing the second nitride liner down to the upper surface of the first plurality of silicon fins; and recessing the oxide.

Abstract: A method of manufacturing a semiconductor device comprises: forming a protective film so as to cover at least a side edge of a substrate; forming a trench, which is annular in shape when viewed oppositely to a first principal surface of the substrate, on the first principal surface by etching using a photoresist pattern; and forming an insulating film so as to fill the trench, to form an insulating ring.

Abstract: According to one embodiment, a method is disclosed for chemical planarization. The method can include forming a surface layer on a to-be-processed film having irregularity. The surface layer binds to or adsorbs onto the to-be-processed film along the irregularity to suppress dissolution of the to-be-processed film. The method can include planarizing the to-be-processed film in a processing solution dissolving the to-be-processed film, by rotating the to-be-processed film and a processing body while the to-be-processed film contacting the processing body via the surface layer, removing the surface layer on convex portions of the irregularity while leaving the surface layer on concave portions of the irregularity and making dissolution degree of the convex portions larger than dissolution degree of the concave portions.