Abstract: According to one embodiment, the method of manufacturing a semiconductor device includes contacting a film formed on a semiconductor substrate with a rotating polishing pad which is supported on a turntable, and feeding polishing foam to a region of the polishing pad with which the film is contacted, thereby polishing the film. The polishing foam is obtained by turning the aqueous dispersion into a foamy body. The aqueous dispersion includes 0.01-20% by mass of abrasive grain and 0.01-1% by mass of foam forming and retaining agent, all based on a total mass of the aqueous dispersion.

Abstract: A polishing liquid is provided with which a polishing rate relative to a conductive metal wiring typically represented by a copper wiring on a substrate having a barrier layer containing manganese and/or a manganese alloy and an insulating layer on the surface (particularly, copper oxide formed at the boundary) is decreased and with which less step height between the conductive metal wiring and the insulating layer is formed, and a polishing method using the polishing liquid is also provided. The polishing liquid includes: colloidal silica particles exhibiting a positive ? potential at the surface thereof; a corrosion inhibiting agent; and an oxidizing agent, in which the polishing liquid is used in a chemical mechanical polishing process for a semiconductor device having, on a surface thereof, a barrier layer containing manganese and/or a manganese alloy, a conductive metal wiring, and an insulating layer.

Abstract: A method of chemically-mechanically polishing a substrate having a Group III-nitride surface includes providing a chemical-mechanical polishing slurry composition. The slurry composition includes a slurry solution including a liquid carrier and an oxidizer including a transition metal or a per-based compound. The slurry solution includes at least one component that reacts with the Group III-nitride surface to form a softened Group III-nitride surface. The Group III-nitride comprising surface is contacted with the slurry composition by a pad to form the softened Group III-nitride surface. The pad is moved relative to the softened Group III-nitride surface, wherein at least a portion of the softened Group III-nitride surface is removed.

Abstract: A polishing method and a polishing apparatus particularly suitable for finishing a surface of a substrate of a compound semiconductor containing an element such as Ga or the like to a desired level of flatness, so that a surface of a substrate of a compound semiconductor containing an element of Ga can be flattened with high surface accuracy within a practical processing time. In the presence of water (232) such as weak acid water, water with air dissolved therein, or electrolytic ion water, a surface of a substrate (142) made of a compound semiconductor containing either one of Ga, Al, and In and the surface of a polishing pad (242) having an electrically conductive member (264) in an area of the surface which is held in contact with the substrate (142) are relatively moved while being held in contact with each other, thereby polishing the surface of the substrate (142).

Abstract: A chemical mechanical polishing method includes providing a device layer having a surface to be polished, polishing the surface using an alkaline grinding slurry, removing a residual layer that is been formed on the polished surface using an acid buffer, forming a passivation layer covering the polished surface of the device layer after the residual layer has been removed, and cleaning the passivation layer using deionized water. A semiconductor device thus fabricated has surfaces with excellent flatness, good manufacturing yield and long-term reliability.

Abstract: A post-W CMP cleaning solution consists of carboxylic acid and deionized water. The carboxylic acid may be selected from the group consisting of (1) monocarboxylic acids; (2) dicarboxylic acids; (3) tricarboxylic acids; (4) polycarboxylic acids; (5) hydroxycarboxylic acids; (6) salts of the above-described carboxylic acids; and (7) any combination thereof. The post-W CMP cleaning solution can work well without adding any other chemical additives such as surfactants, corrosion inhibitors, pH adjusting agents or chelating agents.

Abstract: A process for removing a bulk material layer from a substrate and planarizing the exposed surface by CMP by (1) providing an CMP agent exhibiting at the end of the chemical mechanical polishing, without the addition of supplementary materials, the same SER as at its start and a lower MRR than at its start,—an SER which is lower than the initial SER and an MRR which is the same or essentially the same as the initial MRR or a lower SER and a lower MRR than at its start; (2) contacting the surface of the bulk material layer with the CMP agent; (3) the CMP of the bulk material layer with the CMP agent; and (4) continuing the CMP until all material residuals are removed from the exposed surface; and a CMP agent and their use for manufacturing electrical and optical devices.

Abstract: The CMP polishing liquid of the invention comprises a metal salt containing at least one type of metal selected from the group consisting of metals of Groups 8, 11, 12 and 13, 1,2,4-triazole, a phosphorus acid, an oxidizing agent and abrasive grains. The polishing method of the invention comprises a step of polishing at least a palladium layer with an abrasive cloth while supplying a CMP polishing liquid between the palladium layer of a substrate having the palladium layer and the abrasive cloth, wherein the CMP polishing liquid comprises a metal salt containing at least one type of metal selected from the group consisting of metals of Groups 8, 11, 12 and 13, 1,2,4-triazole, a phosphorus acid, an oxidizing agent and abrasive grains.

Abstract: Methods of protecting a surface of a copper layer or a copper bonding pad on a semiconductor device against oxidation. A surface of the layer or bonding pad is cleaned by removing an oxidation layer with a plasma. A polymer layer is formed on the cleaned surface of the layer using a plasma-enhanced deposition process to protect the cleaned surface of the layer against exposure to an oxidizing gas.

Abstract: An aqueous chemical mechanical polishing (CMP) agent (A) comprising solid particles (a1) containing (a11) a corrosion inhibitor for metals, and (a12) a solid material, the said solid particles (a1) being finely dispersed in the aqueous phase; and its use in a process for removing a bulk material layer from the surface of a substrate and planarizing the exposed surface by chemical mechanical polishing until all material residuals are removed from the exposed surface, wherein the CMP agent exhibits at the end of the chemical mechanical polishing, without the addition of supplementary materials, —the same or essentially the same static etch rate (SER) as at its start and a lower material removal rate (MRR) than at its start, —a lower SER than at its start and the same or essentially the same MRR as at its start or—a lower SER and a lower MRR than at its start; such that the CMP agent exhibits a soft landing behavior.

Abstract: The present disclosure provides a semiconductor manufacturing method. The method includes defining a plurality of time regions of pad life for a polishing pad in a chemical mechanical polishing (CMP) system; assigning a ladder coefficient to the polishing pad according to the plurality of time regions of pad life; defining a plurality of endpoint windows to the plurality of time regions, respectively, according to pad life effect; applying a CMP process to a wafer positioned on the polishing pad; determining a time region of a polishing signal of the wafer based on the ladder coefficient; associating one of the endpoint windows to the polishing signal according to the time region; and ending the CMP process at an endpoint determined by the endpoint window.

Abstract: A chemical mechanical polishing composition useful for chemical mechanical polishing a semiconductor wafer containing an interconnect metal is provided, comprising, as initial components: water; an azole inhibitor; an alkali metal organic surfactant; a hydrotrope; a phosphorus containing agent; optionally, a non-saccharide water soluble polymer; optionally, a water soluble acid compound of formula I, wherein R is selected from a hydrogen and a C1-5 alkyl group, and wherein x is 1 or 2; optionally, a complexing agent; optionally, an oxidizer; optionally, an organic solvent; and, optionally, an abrasive.

Abstract: A chemical mechanical polishing composition useful for chemical mechanical polishing a semiconductor wafer containing an interconnect metal is provided, comprising, as initial components: water; an azole inhibitor; an alkali metal organic surfactant; a hydrotrope; a phosphorus containing agent; a water soluble cellulose; optionally, a non-saccharide water soluble polymer; optionally, a water soluble acid compound of formula I, wherein R is selected from a hydrogen and a C1-5 alkyl group, and wherein x is 1 or 2; optionally, a complexing agent; optionally, an oxidizer; optionally, an organic solvent; and, optionally, an abrasive.

Abstract: The invention provides a method for manufacturing a transistor which includes: providing a substrate having a plurality of transistors formed thereon, wherein each transistor includes a gate; forming a stressed layer and a first oxide layer on the transistors and on the substrate successively; forming a sacrificial layer on the first oxide layer; patterning the sacrificial layer to remove a part of the sacrificial layer which covers on the gates of the transistors; forming a second oxide layer on the residual sacrificial layer and on a part of the first oxide layer which is exposed after the part of the sacrificial layer is removed; performing a first planarization process to remove a part of the second oxide layer located on the gates of the transistors; performing a second planarization process to remove the residual second oxide layer; and performing a third planarization process to remove the stressed layer.

Abstract: A method for thinning a wafer is provided. In one embodiment, a wafer is provided having a plurality of semiconductor chips, the wafer having a first side and a second side opposite the first side, wherein each of the chips includes a set of through silicon vias (TSVs), each of the TSVs substantially sealed by a liner layer and a barrier layer. A wafer carrier is provided for attaching to the second side of the wafer. The first side of the wafer is thinned and thereafer recessed to partially expose portions of the liner layers, barrier layers and the TSVs protruding from the wafer. An isolation layer is deposited over the first side of the wafer and the top portions of the liner layers, barrier layers and the TSVs. Thereafter, an insulation layer is deposited over the isolation layer. The insulation layer is then planarized to expose top portions of the TSVs. A dielectric layer is deposited over the planarized first side of the wafer.

Abstract: The present invention provides a chemical-mechanical planarization method. The chemical-mechanical planarization method includes: providing a substrate including a gate and source/drain regions on the sides of the gate, the gate and the source/drain regions being overlay by an insulating layer, and the insulating layer including a protruding part above the gate and a recessed part above a surface of the substrate between gates; selectively doping the insulating layer such that only the protruding part is doped; and performing CMP on the substrate after doping, to remove the protruding part and planarize the surface of the substrate. By selectively doping the insulating layer, the method makes only the protruding part of the insulating layer doped, enhancing the corrosive attacks on the material of the protruding part by the slurry in the CMP, and increasing the removal rate of the material of the protruding part by the CMP.

Abstract: The first embodiment of the CMP polishing liquid of the invention comprises cerium oxide particles, an organic compound with an acetylene bond, and water, the content of the organic compound with an acetylene bond being at least 0.00001 mass % and not greater than 0.01 mass % based on the total mass of the CMP polishing liquid. The second embodiment of the CMP polishing liquid of the invention comprises cerium oxide particles, an organic compound with an acetylene bond, an anionic polymer compound or salt thereof, and water, the anionic polymer compound being obtained by polymerizing a composition comprising a vinyl compound with an anionic substituent as a monomer component, the content of the organic compound with an acetylene bond being at least 0.000001 mass % and less than 0.05 mass % based on the total mass of the CMP polishing liquid.

Abstract: Hardmask films having high hardness and low stress are provided. In some embodiments a film has a stress of between about ?600 MPa and 600 MPa and hardness of at least about 12 GPa. In some embodiments, a hardmask film is prepared by depositing multiple sub-layers of doped or undoped silicon carbide using multiple densifying plasma post-treatments in a PECVD process chamber. In some embodiments, a hardmask film includes a high-hardness boron-containing film selected from the group consisting of SixByCz, SixByNz, SixByCzNw, BxCy, and BxNy. In some embodiments, a hardmask film includes a germanium-rich GeNx material comprising at least about 60 atomic % of germanium. These hardmasks can be used in a number of back-end and front-end processing schemes in integrated circuit fabrication.

Abstract: A method for fabricating a semiconductor device according to an embodiment, includes forming a plurality of films above a substrate in a same chamber without transferring the substrate out of the chamber, forming a target film to be polished above the plurality of films, and polishing the target film by a chemical mechanical polishing (CMP) technique using a film on a front side among the plurality of films as a polishing stopper.

Abstract: A Chemical Mechanical Polishing (CMP) method includes providing a semiconductor substrate having an overlying dielectric layer, performing a first grinding on the dielectric layer, wherein the first grinding produces organic residues on a surface of the dielectric layer after the first grinding. The method further includes performing a second grinding on the dielectric layer by using an alkaline solution to remove the organic residues on the surface of the dielectric layer. The organic residues remaining on the surface of the dielectric layer are removed by using the alkaline solution after the first grinding process is performed. The method additionally includes cleaning a grinding pad and the substrate using deionized water.

Abstract: A method comprising: providing at least one first diamond film comprising polycrystalline diamond, e.g., nanocrystalline or ultrananocrystalline diamond, disposed on a substrate, wherein the first diamond film comprises a surface comprising diamond asperities and having a first diamond film thickness, removing asperities from the first diamond film to form a second diamond film having a second diamond film thickness, wherein the second thickness is either substantially the same as the first thickness, or the second thickness is about 100 nm or less thinner than the first diamond film thickness, optionally patterning the second diamond film to expose substrate regions and, optionally, depositing semiconductor material on the exposed substrate regions, and depositing a solid layer on the second diamond film to form a first layered structure.

Abstract: The invention relates to a chemical-mechanical polishing composition comprising silica, one or more tetraalkylammonium salts, one or more bicarbonate salts, one or more alkali metal hydroxides, one or more aminophosphonic acids, one or more rate accelerator compounds, one or more polysaccharides, and water. The polishing composition reduces surface roughness and PSD of polished substrates. The invention further relates to a method of chemically-mechanically polishing a substrate, especially a silicon substrate, using the polishing composition described herein.

Abstract: A semiconductor device manufacturing method includes: forming a first insulating film over the surface of a semiconductor substrate having at least two adjacent protrusions in such a manner that the film thickness between the two protrusions is not less than 1.2 times the height of at least one of the two protrusions; and forming a second insulating film over the first insulating film, the second insulating film being harder than the first insulating film.

Abstract: A chemical mechanical planarization method uses a chemical mechanical planarization composition that includes at least one nitrogen containing material and a pH modifying material, absent an abrasive material. The nitrogen containing material may be selected from a particular group of nitrogen containing polymers and corresponding nitrogen containing monomers. The chemical mechanical planarization method and the chemical mechanical planarization composition provide for planarizing a silicon material layer, such as but not limited to a poly-Si layer, in the presence of a silicon containing dielectric material layer, such as but not limited to a silicon oxide layer or a silicon nitride layer, with enhanced efficiency provided by an enhanced removal rate ratio.

Abstract: A pump having: a cavity formed inside an insulating substrate, the upper part of the substrate being situated near the cavity having an edge; a conductive layer covering the inside of the cavity up to the edge and optionally covering the edge itself; a flexible membrane made of a conductive material placed above the cavity and resting against the edge; a dielectric layer covering the conductive layer or the membrane whereby insulating the portions of the conductive layer and of the membrane that are near one another; at least one aeration line formed in the insulating substrate that opens into the cavity via an opening in the conductive layer, and; terminals for applying a voltage between the conductive layer and the membrane.

Abstract: Provided are a multi-selective polishing slurry composition and a semiconductor element production method using the same. A silicon film provided with element patterns is formed on the uppermost part of a substrate having a first region and a second region. The element pattern density on the first region is higher than the element pattern density on the second region. Formed in sequence on top of the element patterns are a first silicon oxide film, a silicon nitride film and a second silicon oxide film. The substrate is subjected to chemical-mechanical polishing until the silicon film is exposed, by using a polishing slurry composition containing a polishing agent, a silicon nitride film passivation agent and a silicon film passivation agent.

Abstract: Reliability and yield of MTJ devices is improved by reducing surface roughness in the MTJ layers of the MTJ devices. Surface roughness is reduced by reducing surface roughness of layers below the MTJ layers such as the bottom electrode layer. Planarizing the bottom electrode layer through chemical mechanical polishing or etch back of spin-on material before depositing the MTJ layers decreases surface roughness of the bottom electrode layer and the MTJ layers. Alternatively, a capping layer may be planarized before deposition of the bottom electrode layer and MTJ layers to reduce surface roughness in the capping layer, the bottom electrode layer, and the MTJ layers.

Abstract: A method comprising: providing at least one first diamond film comprising polycrystalline diamond, e.g., nanocrystalline or ultrananocrystalline diamond, disposed on a substrate, wherein the first diamond film comprises a surface comprising diamond asperities and having a first diamond film thickness, removing asperities from the first diamond film to form a second diamond film having a second diamond film thickness, wherein the second thickness is either substantially the same as the first thickness, or the second thickness is about 100 nm or less thinner than the first diamond film thickness, optionally patterning the second diamond film to expose substrate regions and, optionally, depositing semiconductor material on the exposed substrate regions, and depositing a solid layer on the second diamond film to form a first layered structure.

Abstract: An interlayer insulating film is formed on a semiconductor substrate having a semiconductor element formed thereon. At this time, there are protrusions higher than surroundings thereof and non-protruding portions lower than the protrusions on the surface of the interlayer insulating film. First, a first polishing process is carried out on the surface of the interlayer insulating film with use of a first abrasive having non-Prestonian properties produced by mixing abrasive materials including abrasive grains, a polymer additive and water at a predetermined first mixture ratio. Then, after the first abrasive process shifts to an automatically stopping state, a second polishing process is carried out on the surface of the interlayer insulating film with use of a second abrasive having the concentration of polymer additive lower than that of the first abrasive and produced by mixing the abrasive materials at a second mixture ratio different from the first mixture ratio.

Abstract: According to embodiments of the present invention, a method of processing a wafer is provided. The wafer includes a plurality of through-wafer interconnects extending from a frontside surface of the wafer to a backside surface of the wafer. The method includes removing a part of wafer material of the back-side such that a portion of the wafer material between the through-wafer interconnects is removed, thereby exposing a portion of the through-wafer interconnects, forming a layer of low-k dielectric material between the through-wafer interconnects, and planarizing the layer of low-k dielectric material such that a surface of the portion of the through-wafer interconnect is exposed.

Abstract: A method for fabricating a fine pattern of a semiconductor device is provided. The method includes forming a base layer, a first mask pattern having identical features of a first width with inclined sidewalls and a second mask pattern having identical features of a second width in sequence on a substrate, wherein a smallest distance between any two adjacent inclined sidewalls is equal to the second width. The base layer is etched by using the first mask pattern as an etch mask to form first openings of the second width and a fill layer is formed covering the substrate. The second mask pattern is removed to form second openings in the fill layer and then the first mask pattern and the base layer are etched through the second openings to form third openings. The fill layer and the first mask pattern are removed to form a pattern of the base layer having identical features of a third width, wherein the third width of the features of the base layer pattern is equal to the second width.

Abstract: Mirror-polishing a front surface of a silicon wafer using polishing liquid composed of an abrasive grain-free alkaline solution including water-soluble polymers simplifies a polishing process, thus leading to an increase in productivity and a reduction in cost, and reduces the density of LPDs attributable to processing and occurring in the front surface of a mirror-polished wafer, thus improving the surface roughness of the wafer front surface.

Abstract: A method for producing a semiconductor wafer includes a number of steps in order including a bilateral material-removing process followed by rounding off an edge of the wafer and grinding front and back sides of the wafer by holding one side and grinding the other. The front and back are then polished with a polishing cloth including bound abrasives and subsequently treated with an etching medium to carry out a material removal of no more than 1?m on each side. The front side is then polished using a polishing cloth including bound abrasives and the back side is simultaneously polished using a polishing cloth free of abrasives while a polish with abrasives is provided. The edge is then polished followed by polishing the back with a polishing cloth including bound abrasives and simultaneously polishing the front with a cloth free of abrasives while a polish including abrasives is provided.

Abstract: A manufacturing method of a device is provided. In the manufacturing method, a substrate is provided. The substrate has a plurality of patterns and a plurality of openings formed thereon, and the openings are located among the patterns. A first liquid supporting layer is formed on the patterns, and the openings are filled with the first liquid supporting layer. The first liquid supporting layer is transformed into a first solid supporting layer. The first solid supporting layer includes a plurality of supporting elements formed in the openings, and the supporting elements are formed among the patterns. A treatment process is performed on the patterns. The first solid supporting layer that includes the supporting elements is transformed into a second liquid supporting layer. The second liquid supporting layer is removed.

Abstract: A CMP composition and associated method are provided that afford good corrosion protection and low defectivity levels both during and subsequent to CMP processing. This composition and method are useful in CMP (chemical mechanical planarization) processing in semiconductor manufacture involving removal of metal(s) and/or barrier layer material(s) and especially for CMP processing in low technology node applications.

Abstract: A method for manufacturing TSVs comprises following steps: A stack structure having a substrate, an ILD layer and a dielectric stop layer is provided, in which an opening penetrating through the ILD layer and the dialectic stop layer and further extending into the substrate is formed. After an insulator layer and a metal barrier are formed on the stack structure, a top metal layer is formed on the stack structure to fulfill the opening. A first planarization process stopping on the metal barrier is conducted, wherein the first planarization process has a polishing rate for removing the metal barrier less than that for removing the top metal layer. A second planarization process stopping on the dielectric stop layer is conducted, wherein the second planarization process has a polishing rate for removing the insulator layer greater than that for removing the dielectric stop layer. The dielectric stop layer is than removed.

Abstract: The present invention provides a chemical-mechanical planarization method and a method for fabricating a metal gate in gate last process. The chemical-mechanical planarization method includes: providing a substrate including a gate and source/drain regions on the sides of the gate, the gate and the source/drain regions being overlay by an insulating layer, and the insulating layer including a protruding part above the gate and a recessed part above a surface of the substrate between gates; selectively doping the insulating layer such that only the protruding part is doped; and performing CMP on the substrate after doping, to remove the protruding part and planarize the surface of the substrate.

Abstract: A method of manufacturing a solar cell by providing a first substrate; depositing on the first substrate a sequence of layers of semiconductor material forming a solar cell including a top subcell and a bottom subcell; forming a metal back contact over the bottom subcell; forming a group of discrete, spaced-apart first bonding elements over the surface of the back metal contact; attaching a surrogate substrate on top of the back metal contact using the bonding elements; and removing the first substrate to expose the surface of the top subcell.

Abstract: A polishing agent of the invention comprises tetravalent metal hydroxide particles, a cationized polyvinyl alcohol, at least one type of saccharide selected from the group consisting of an amino sugar, a derivative of the amino sugar, a polysaccharide containing an amino sugar and a derivative of the polysaccharide, and water. The method for polishing a substrate of the invention comprises a step of polishing the silicon oxide film 1 (film to be polished), formed on the silicon substrate 2 having the silicon oxide film 1, by relatively moving the silicon substrate 2 and a polishing platen, in a state that the silicon oxide film 1 is pressed against a polishing pad on the polishing platen, while supplying the polishing agent of the invention between the silicon oxide film 1 and the polishing pad.

Abstract: The compositions and methods for the removal of residues and contaminants from metal or dielectric surfaces comprises at least one alkyl diphosphonic acid, at least one second acidic substance at amble ratio of about 1:1 to about 10:1 in water, arid pH is adjusted to from about 6 to about 10 with a metal ion free base, and a surfactant. Particularly, a composition and method of cleaning residues after chemical mechanical polishing of a copper or aluminum surface of the semiconductor substrates.

Abstract: A method is provided for integrating metal-containing cap layers into copper (Cu) metallization of semiconductor devices. In one embodiment, the method includes providing a planarized patterned substrate containing metal surfaces and dielectric layer surfaces with a residue formed thereon, removing the residue from the planarized patterned substrate, and depositing metal-containing cap layers selectively on the metal surfaces by exposing the dielectric layer surfaces and the metal surfaces to a deposition gas containing metal-containing precursor vapor. The removing includes treating the planarized patterned substrate containing the residue with a reactant gas containing a hydrophobic functional group, and exposing the treated planarized patterned substrate to a reducing gas.

Abstract: A dielectric deposition tool for forming a silicon dioxide layer on a wafer with a TEOS showerhead which delivers a flow rate per unit area from an edge band of the showerhead that is at least twice a flow rate per unit area from a central region of the showerhead. The edge band extends at least one half inch from an outer edge of the showerhead up to one fourth of the diameter of the wafer. A process of forming an integrated circuit by forming a silicon dioxide layer on a wafer containing the integrated circuit using the dielectric deposition tool. The silicon dioxide layer is thicker under the edge band than under the central region. A subsequent CMP operation reduces the thickness difference between the wafer outer annulus and the wafer core by at least half. The silicon dioxide layer has a compressive stress between 125 and 225 MPa.

Abstract: Solutions for forming an extremely thin semiconductor-on-insulator (ETSOI) layer. In one embodiment, a method includes providing a wafer including a plurality of semiconductor-on-insulator (SOI) layer regions separated by at least one shallow trench isolation (STI); amorphizing the plurality of SOI layer regions by implanting the plurality of SOI layer regions with an implant species; and removing a portion of the amorphized SOI layer region to form at least one recess in the amorphized SOI layer region.

Abstract: The present invention provides a chemical-mechanical polishing (CMP) composition suitable for polishing a silicon nitride-containing substrate while suppressing polysilicon removal from the substrate. The composition comprises abrasive particles suspended in an acidic aqueous carrier containing a surfactant comprising an alkyne-diol, an alkyne diol ethoxylate, or a combination thereof. Methods of polishing a semiconductor substrate therewith are also disclosed.

Abstract: A method of controlling polishing includes storing a library having a plurality of reference spectra, polishing a substrate, measuring a sequence of spectra of light from the substrate during polishing, for each measured spectrum of the sequence of spectra, finding a best matching reference spectrum using a matching technique other than sum of squared differences to generate a sequence of best matching reference spectra, and determining at least one of a polishing endpoint or an adjustment for a polishing rate based on the sequence of best matching reference spectra. Finding a best matching reference spectrum may include performing a cross-correlation of the measured spectrum with each of two or more of the plurality of reference spectra from the library and selecting a reference spectrum with the greatest correlation to the measured spectrum as a best matching reference spectrum.

Abstract: The present invention relates to a slurry for chemical mechanical polishing, comprising an abrasive; an oxidant; an organic acid; and a polymeric additive comprising polyolefin-polyalkyleneoxide copolymer, wherein the polyolefin-polyalkyleneoxide copolymer comprises a polyolefin repeat unit and two or more polyalkyleneoxide repeat units, and at least one polyalkyleneoxide repeat unit is branched.

Abstract: The invention relates to a CMP polishing liquid comprising a medium and silica particles as an abrasive grain dispersed into the medium, characterized in that: (A1) the silica particles have a silanol group density of 5.0/nm2 or less; (B1) a biaxial average primary particle diameter when arbitrary 20 silica particles are selected from an image obtained by scanning electron microscope observation is 25 to 55 nm; and (C1) an association degree of the silica particles is 1.1 or more. The invention provides a CMP polishing liquid which has the high barrier film polishing speed, the favorable abrasive grain dispersion stability, and the high interlayer dielectric polishing speed, and a polishing method producing semiconductor substrates or the like, that have excellent microfabrication, thin film formation, dimension accuracy, electric property and high reliability with low cost.

Abstract: The method of the present invention comprises providing a wafer including a first, second and third material; contacting the third material in the presence of a working liquid with abrasive composites fixed to an abrasive article; and moving the wafer until an exposed surface of the wafer is substantially planar and comprises at least one area of exposed third material and one area of exposed second material. The components of the working liquid include an aqueous solvent; a pH buffer exhibiting a pKa greater than 7 and comprising a basic pH adjusting agent and a multidentate acidic complexing agent; and a non-ionic surfactant. The nonionic surfactant exhibits a hydrophile-lipophile balance of at least about 4. The working liquid is substantially free of loose abrasive particles and exhibits a pH of about 7-12.

Abstract: A chemical mechanical polishing process includes placing a substrate on a first polishing pad of a first platen, wherein the substrate has a bulk metal layer and a barrier layer; polishing the bulk metal layer by using the first polishing pad having a hardness of above 50 (Shore D) until the barrier layer is exposed; polishing the barrier layer on a second polishing pad of a second platen after removing the bulk metal layer, wherein the second polishing pad has a hardness ranging between 40 and 50 (Shore D) and includes an upper layer and a lower backing layer and the upper layer has a hardness less than 50 (Shore D).

Abstract: A wafer carrier adapted to further reduce the edge effect and allow a wafer to be uniformly polished across its entire surface, with a retaining ring made from very hard materials such as PEEK, PET or polycarbonate with a hardness in the range of 80 to 85 Shore D, while the inner surface or insert is made of polyurethane or other material with a hardness in the range of 85 to 95 Shore A.