Abstract: A polishing method includes polishing, in a first polish, a wafer to remove overburden and planarize a top layer leaving a portion remaining on an underlying layer. A second polishing step includes two phases. In a first phase, the top layer is removed and the underlying layer is exposed, with a top layer to underlying layer selectivity of between about 1:1 to about 2:1 to provide a planar topography. In a second phase, residual portions of the top layer are removed from a top of the underlying layer to ensure complete exposure of an underlying layer surface.

Abstract: A planarization method includes planarizing a semiconductor wafer in a first chemical mechanical polish step to remove overburden and planarize a top layer leaving a thickness of top layer material over underlying layers. The top layer material is planarized in a second chemical mechanical polish step to further remove the top layer and expose underlying layers of a second material and a third material such that a selectivity of the top layer material to the second material to the third material is between about 1:1:1 to about 2:1:1 to provide a planar topography.

Abstract: Methods are provided for forming gates in gate-last processes. The methods may include performing chemical mechanical polishing (CMP) on an interlayer dielectric (ILD) that is on a plurality of dummy gates, each of the plurality of dummy gates including a gate mask in an upper portion thereof, and the CMP exposing the gate mask. The methods may also include removing the gate mask by etching the gate mask. The methods may further include performing CMP on the ILD.

Abstract: This invention is to provide a method of polishing a silicon wafer wherein a high flatness can be attained likewise the conventional polishing method and further the occurrence of defects due to the remaining of substances included in the polishing solution on the surface of the wafer can be suppressed as well as a polished silicon wafer. The method of polishing a silicon wafer by supplying a polishing solution containing abrasive grains onto a surface of a polishing pad and then relatively sliding the polishing pad to a silicon wafer to polish the surface of the silicon wafer, is characterized in that the number of abrasive grains included in the polishing solution is controlled to not more than 5×1013 grains/cm3.

Abstract: A chemical mechanical polishing composition, comprising, as initial components: water; an abrasive; a diquaternary substance according to formula (I), wherein each X is independently selected from N and P; wherein R1 is selected from a saturated or unsaturated C1-C15 alkyl group, a C6-C15 aryl group and a C6-C15 aralkyl group; wherein R2, R3, R4, R5, R6 and R7 are each independently selected from selected from a hydrogen, a saturated or unsaturated C1-C15 alkyl group, a C6-C15 aryl group, a C6-C15 aralkyl group and a C6-C15 alkaryl group; and, wherein the anion in formula (I) can be any anion or combination of anions that balance the 2+ charge on the cation in formula (I); a derivative of guanidine according to formula (II), wherein R8 is selected from a hydrogen, a saturated or unsaturated C1-C15 alkyl group, a C6-C15 aryl group, a C6-C15 aralkyl group and a C6-C15 alkaryl group; wherein R9, R10, R11 and R12 are each independently selected from a hydrogen, a saturated or unsaturated C1-C15 alkyl group, a C6-

Abstract: A chemical mechanical polishing slurry composition, comprising, as initial components: water; an abrasive; a halogenated quaternary ammonium compound according to formula (I), wherein R8 is selected from a C1-10 alkyl group and a C1-10 hydroxyalkyl group; wherein X1 is a halide selected from chloride, bromide, iodide and fluoride; wherein R9, R10 and R11 are each independently selected from a saturated or unsaturated C1-10 alkyl group, a C1-10 haloalkyl group, a C6-15 aryl group, a C6-15 haloaryl group, a C6-15 arylalkyl group and a C6-15 haloarylalkyl; and, wherein the anion in formula (I) can be any anion that balances the + charge on the cation in formula (I); and, optionally, a diquaternary substance according to formula (II), wherein each A is independently selected from N and P; wherein R1 is selected from a saturated or unsaturated C1-C15 alkyl group, a C6-C15 aryl group and a C6-C15 aralkyl group; wherein R2, R3, R4, R5, R6 and R7 are each independently selected from selected from a hydrogen, a satura

Abstract: Slurry compositions and chemically activated CMP methods for polishing a substrate having a silicon carbide surface using such slurries. In such methods, the silicon carbide surface is contacted with a CMP slurry composition that comprises i) a liquid carrier and ii) a plurality of particles having at least a soft surface portion, wherein the soft surface portion includes a transition metal compound that provides a Mohs hardness ?6, and optionally iii) an oxidizing agent. The oxidizing agent can include a transition metal. The slurry is moved relative to the silicon carbide comprising surface, wherein at least a portion of the silicon carbide surface is removed.

Abstract: Provided is a method of planarizing a semiconductor device. The method includes providing a substrate. The method includes forming a first material layer on the substrate. The method includes forming a second material layer over the first material layer. The second material layer is softer than the first material layer and has an exposed surface that is not in contact with the first material layer. The method includes flattening the second material layer without removing a portion of the second material layer. The flattening is carried out in a manner such that the exposed surface is substantially flat after the flattening. The method includes performing an etch back process to remove the second material layer and a portion of the first material layer. Wherein an etching selectivity of the etch back process with respect to the first and second material layers is approximately 1:1.

Abstract: (A) solid polymer particles being finely dispersed in the aqueous phase and containing pendant functional groups (a1) capable of strongly interacting and forming strong complexes with the metal of the surfaces to be polished, and pendant functional groups (a2) capable of interacting less strongly with the metal of the surfaces to be polished than the functional groups (a1); and (B) an organic non-polymeric compound dissolved in the aqueous phase and capable of interacting and forming strong, water-soluble complexes with the metal of the surfaces to be polished and causing an increase of the material removal rate MRR and the static etch rate SER of the metal surfaces to be polished with increasing concentration of the compound (B); a CMP process comprising selecting (A) and (B) and the use of the CMP agent and process for polishing wafers with ICs.

Abstract: A copper/barrier CMP process includes (a) providing a substrate having a bulk metal layer and a barrier layer; (b) polishing the substrate with a first hard polishing pad on a first platen to substantially remove an upper portion of the bulk metal layer, wherein the first hard polishing pad has a hardness of above 50 (Shore D); (c) polishing the substrate with a second hard polishing pad on a second platen to remove residual copper, thereby exposing the barrier layer, wherein the second hard polishing pad has a hardness of above 50 (Shore D); and (d) polishing the substrate with a third hard polishing pad on a third platen to remove the barrier layer, wherein the third hard polishing pad has a hardness ranging between 40-50 (Shore D).

Abstract: A chemical mechanical polishing method comprises polishing an organic film using a slurry including polymer particles having a surface functional group and a water-soluble polymer.

Abstract: A method for chemical-mechanical polishing two adjacent structures of a semiconductor device is provided. The method for mechanical polishing comprising: (a) providing a semiconductor device comprising a recess formed in a surface thereof, a first layer formed over the surface, and a second layer filled with the recess and formed on the first layer; and (b) substantially polishing the first and second layer with a pad and a substantially inhibitor-free slurry, wherein the pad comprising a corrosion inhibitor of the second layer.

Abstract: A method for forming a semiconductor device. A substrate having thereon at least one small pattern and at least one large pattern is provided. A sacrificial layer is deposited to cover the small pattern and the large pattern. A chemical mechanical polishing is performed to planarize the sacrificial layer. The sacrificial layer is then dry etched to a thickness that is smaller than a height of the small pattern and the large pattern, thereby revealing an oxide hard mask of the small pattern and the large pattern. The oxide hard mask is then selectively removed.

Abstract: Provided is a polishing fluid that has a fast polishing rate, and can selectively suppress polishing of layers including polysilicon or modified polysilicon during the chemical mechanical polishing in the manufacture of semiconductor integrated circuits, and a polishing method using the same. A polishing fluid used for the chemical mechanical polishing in which each of the components represented by the following (1) and (2) is included, the pH is 1.5 to 5.0, and a polishing workpiece can be polished in a range of a ratio represented by RR (other)/RR (p-Si) when the polishing rate of the first layer is RR (p-Si), and the polishing rate of the second layer is RR (other) of 1.5 to 200. (1) Colloidal silica particles (2) At least one inorganic phosphate compound selected from phosphoric acid, pyrophosphoric acid, and polyphosphoric acid.

Abstract: The titled method affords low dishing levels in the polished substrate while simultaneously affording high metal removal rates. The method utilizes an associated polishing composition. Components in the composition include a poly(alkyleneimine) such as polyethyleneimine, an abrasive, an acid, and an oxidizing agent, such as a per-compound.

Abstract: A method includes bonding a wafer on a carrier through an adhesive, and performing a thinning process on the wafer. After the step of performing the thinning process, a portion of the adhesive not covered by the wafer is removed, while the portion of the adhesive covered by the wafer is not removed.

Abstract: A system for preparing a microcellular polyurethane material, includes a froth, prepared, for instance, by inert gas frothing a urethane prepolymer, preferably an aliphatic isocyanate polyether prepolymer, in the presence of a surfactant; a filler soluble in a CMP slurry; and a curative, preferably including an aromatic diamine and a triol. To produce the microcellular material, the froth can be combined with the filler, e.g., PVP, followed by curing the resulting mixture. The microcellular material has a low rebound and can dissipate irregular energy and stabilize polishing to yield improved uniformity and less dishing. CMP pads using the microcellular material have pores created by inert gas frothing throughout the pad polymer body and additional surface pores created by dissolution of fillers during polishing, providing flexibility in surface softness and pad stiffness.

Abstract: The invention provides a method for chemical mechanical polishing of a substrate. The invention comprises providing a substrate, wherein the substrate comprises a chalcogenide phase change alloy and providing a chemical mechanical polishing composition, wherein the chemical mechanical polishing composition comprises, by weight percent, water, 0.1 to 30 abrasive, at least one polishing agent selected from 0.05 to 5 halogen compound, 0.05 to 5 phthalic acid, 0.05 to 5 phthalic anhydride and salts, derivatives and mixtures thereof and wherein the chemical mechanical polishing composition has a pH of 2 to less than 7. A chemical mechanical polishing pad polishes the substrate with the chemical mechanical polishing pad and the chemical mechanical polishing composition to selectively or non-selectively remove the chalcogenide phase change alloy from the substrate.

Abstract: The present disclosure provides a method of fabricating a semiconductor device, a semiconductor device fabricated by such a method, and a chemical mechanical polishing (CMP) tool for performing such a method. In one embodiment, a method of fabricating a semiconductor device includes providing an integrated circuit (IC) wafer including a metal conductor in a trench of a dielectric layer over a substrate, and performing a chemical mechanical polishing (CMP) process to planarize the metal conductor and the dielectric layer. The method further includes cleaning the planarized metal conductor and dielectric layer to remove residue from the CMP process, rinsing the cleaned metal conductor and dielectric layer with an alcohol, and drying the rinsed metal conductor and dielectric layer in an inert gas environment.

Abstract: The CMP polishing solution of the invention comprises (A) a metal corrosion inhibitor containing a compound with a 1,2,3-triazolo[4,5-b]pyridine skeleton, (B) an abrasive grain having a positive zeta potential in the CMP polishing solution, (C) a metal oxide solubilizer and (D) an oxidizing agent. The polishing method of the invention comprises a first polishing step in which the conductive substance layer of a substrate comprising an interlayer insulating filth having an elevated section and a trench at the surface, a barrier layer formed following the surface of the interlayer insulating film and the conductive substance layer formed covering the barrier layer, is polished to expose the barrier layer located on the elevated section of the interlayer insulating film, and a second polishing step in which the barrier layer exposed in the first polishing step is polished using the CMP polishing solution to expose the elevated section of the interlayer insulating film.

Abstract: The present invention relates to lithographic apparatuses and processes, and more particularly to multiple patterning lithography for printing target patterns beyond the limits of resolution of the lithographic apparatus. Self-aligned assist pattern (SAP) is derived from original design layout in an automated manner using geometric Boolean operations based on some predefined design rules, and are included in the mask layout for efficient self-alignment of various sub-layouts of the target pattern during a multiple patterning lithography process. SAP can be of any shape and size, and can have continuous features (e.g., a ring), or discontinuous (e.g., bars not connected to each other) features. An end-to-end multiple patterning lithography using spacer and SAP may use positive tone lithography, and/or negative tone lithography for line and/or space printing.

Abstract: A method includes depositing a layer of a sacrificial material in a first region above a substrate. The first region of the substrate is separate from a second region of the substrate, where a corrosion resistant film is to be provided above the second region. The corrosion resistant film is deposited, so that a first portion of the corrosion resistant film is above the sacrificial material in the first region, and a second portion of the corrosion resistant film is above the second region. The first portion of the corrosion resistant film is removed by chemical mechanical polishing. The sacrificial material is removed from the first region using an etching process that selectively etches the sacrificial material, but not the corrosion resistant film.

Abstract: A method using an associated composition for chemical mechanical planarization of a copper-containing substrate affords high copper removal rates and low dishing values during CMP processing of the copper-containing substrate, including an abrasive, at least three surfactants, preferably non-ionic and preferably three distinct surfactants, preferably in the range of 100 ppm to 2000 ppm per surfactant and an oxidizing agent.

Abstract: A method and apparatus for performing chemical-mechanical planarization (CMP) is disclosed, which in one embodiment includes a CMP tool for polishing a semiconductor wafer. The CMP tool includes a slurry mixture that has slurry beads. The slurry beads are formed of a polymer material. The slurry beads are used to remove summits and non-uniformities on the semiconductor wafer. In some embodiments the CMP tool includes a counter-face that replaces the polishing pad of a conventional CMP tool. In some embodiments the counter-face is made of polycarbonate. In another embodiment a slurry mixture for use with a CMP tool is disclosed. The slurry mixture includes slurry beads, where each of the slurry beads has a diameter of between 0.1 and 1000 microns, or in some embodiments a diameter of between 10 and 50 microns.

Abstract: A group III nitride substrate in one embodiment has a surface layer. The surface layer contains 3 at. % to 25 at. % of carbon and 5×1010 atoms/cm2 to 200×1010 atoms/cm2 of a p-type metal element. The group III nitride substrate has a stable surface.

Abstract: A process/method for cleaning wafers that eliminates and/or reduces pitting caused by standard clean 1 by performing a pre-etch and then passivating the wafer surface prior to the application of the standard clean 1. The process/method may be especially useful for advanced front end of line post-CPM cleaning. In one embodiment, the invention is a method of processing a substrate comprising: a) providing at least one substrate; b) etching a surface of the substrate by applying an etching solution; c) passivating the etched surface of the substrate by applying ozone; and d) cleaning the passivated surface of the substrate by applying an aqueous solution comprising ammonium hydroxide and hydrogen peroxide.

Abstract: A chemical mechanical polishing composition, comprising, as initial components: water; 0.1 to 40 wt % abrasive having an average particle size of 5 to 150 nm; 0.001 to 1 wt % of an adamarityl substance according to formula (II); 0 to 1 wt % diquaternary substance according to formula (I); and, 0 to 1 wt % of a quaternary ammonium compound. Also, provided is a method for chemical mechanical polishing using the chemical mechanical polishing composition.

Abstract: An effective chemical mechanical planarization (CMP) method is provided for forming vias in silicon wafers for the fabrication of stacked devices using TSV (through-silicon via) technology. The method affords high removal rates of both metal (e.g., copper) and silicon such that a need for a grinding step prior to CMP processing may not be necessary. The method affords an approximately 1:1 Cu:Si selectivity for removal of silicon and copper under appropriate conditions and the Cu:Si selectivity is tunable by adjustment of levels of some key components.

Abstract: Methods and apparatuses for removing polysilicon material from a semiconductor workpiece are disclosed. A particular method includes contacting a polishing pad with a semiconductor workpiece having a surface polysilicon material. The method also includes disposing a polishing liquid between the polysilicon material and the polishing pad. The polishing liquid contains an oxidizer that does not include metal elements. The method further includes moving at least one of the semiconductor workpiece and the polishing pad relative to the other while the semiconductor workpiece contacts the polishing pad and the polishing liquid. At least some of the polysilicon material is removed while the polysilicon material contacts the oxidizer in the polishing liquid, as at least one of the semiconductor workpiece and the polishing pad moves relative to the other.

Abstract: Embodiments described herein relate to removing material from a substrate. More particularly, the embodiments described herein relate to polishing or planarzing a substrate by a chemical mechanical polishing process. In one embodiment, a method of chemical mechanical polishing (CMP) of a substrate is provided. The method comprises exposing a substrate having a conductive material layer formed thereon to a polishing solution comprising phosphoric acid, one or more chelating agents, one or more corrosion inhibitors, and one or more oxidizers, forming a passivation layer on the conductive material layer, providing relative motion between the substrate and a polishing pad and removing at least a portion of the passivation layer to expose a portion of the underlying conductive material layer, and removing a portion of the exposed conductive material layer.

Abstract: Various pattern transfer and etching steps can be used to create features. Conventional photolithography steps can be used in combination with pitch-reduction techniques to form superimposed, pitch-reduced patterns of crossing elongate features that can be consolidated into a single layer. Planarizing techniques using a filler layer and a protective layer are disclosed. Portions of an integrated circuit having different heights can be etched to a common plane.

Abstract: A smoothing method for semiconductor material and semiconductor wafers produced by the method are disclosed. Semiconductor wafers with reduced atomic steps, as well with reduced scratches and subsurface defects can be produced. Such wafers feature an improved growth surface that can provide for the growth of an epilayer with reduced macroscopic defects and defect densities. A method of smoothing the surface of a wafer according to example embodiments of the invention includes planarizing the surface of a semiconductor wafer, and then oxidizing the wafer to achieve a specified thickness of oxide on the surface of the wafer. The oxide can then be stripped from the surface of the semiconductor wafer.

Abstract: The polishing solution for CMP of the invention comprises abrasive grains, a first additive and water, wherein the first additive is at least 1,2-benzoisothiazole-3(2H)-one or 2-aminothiazole. The polishing method of the invention is a polishing method for a substrate having a silicon oxide film on the surface, and the polishing method comprises a step of polishing the silicon oxide film with a polishing pad while supplying the polishing solution for CMP between the silicon oxide film and the polishing pad.

Abstract: A one-step CMP process for polishing three or more layer film stacks on a wafer having a multilayer film stack thereon including a silicon nitride (SiNx) layer on its semiconductor surface, and a silicon oxide layer on the SiNx layer, wherein trench access vias extend through the silicon oxide layer and SiNx layer to trenches formed into the semiconductor surface, and wherein a polysilicon layer fills the trench access vias, fills the trenches, and is on the silicon oxide layer. CMP polishes the multilayer film stack with a slurry including slurry particles including at least one of silica and ceria. The CMP provides a removal rate (RR) for the polysilicon layer>a RR for the silicon oxide layer>a RR for the SiNx layer. The CMP process is continued to remove the polysilicon layer, silicon oxide layer and a portion of the SiNx layer to stop on the SiNx layer. Optical endpointing during CMP can provide a predetermined remaining thickness range for the SiNx layer.

Abstract: This invention relates to a chemical composition for chemical mechanical polishing (CMP) of substrates that are widely used in the semiconductor industry. The inventive chemical composition contains additives that are capable of improving consistency of the polishing performance and extending the lifetime of a polishing pad.

Abstract: A multilevel interconnect structure for a semiconductor device includes an intermetal dielectric layer with funnel-shaped connecting vias. The funnel-shaped connecting vias are provided in connection with systems exhibiting submicron spacings. The architecture of the multilevel interconnect structure provides a low resistance connecting via.

Abstract: A method of the present invention includes polishing a wafer having an exposed copper or copper alloy surface and an exposed silicon surface by using a polishing composition containing 0.02 to 0.6% by mass of hydrogen peroxide, preferably 0.05 to 0.2% by mass thereof. The polishing composition preferably further contains at least one of a complexing agent, an inorganic electrolyte, and abrasive grains such as colloidal silica. The polishing composition has a pH of preferably 9 or more, more preferably 10 or more.

Abstract: A polishing composition contains a polishing accelerator, a water-soluble polymer including a constitutional unit originating from a polymerizable compound having a guanidine structure such as dicyandiamide, and an oxidant. The water-soluble polymer may be a water-soluble polymer including a constitutional unit originating from dicyandiamide and a constitutional unit originating from formaldehyde, a diamine or a polyamine.

Abstract: A chemical mechanical polishing aqueous dispersion comprises (A) abrasive grains, (B) at least one of quinolinecarboxylic acid and pyridinecarboxylic acid, (C) an organic acid other than quinolinecarboxylic acid and pyridinecarboxylic acid, (D) an oxidizing agent, and (E) a nonionic surfactant having a triple bond, the mass ratio (WB/WC) of the amount (WB) of the component (B) to the amount (WC) of the component (C) being 0.01 or more and less than 2, and the component (E) being shown by the following general formula (1), wherein m and n individually represent integers equal to or larger than one, provided that m+n?50 is satisfied.

Abstract: Provided is a polishing liquid which is used for chemical mechanical polishing of a body to be polished having a layer containing polysilicon or a modified polysilicon, and using which the polishing rate of a layer containing a silicon-based material other than polysilicon is high and polishing of the layer containing polysilicon can be selectively suppressed. The polishing liquid includes components (A), (B), and (C), has a pH of from 1.5 to 7.0, and is capable of selectively polishing a second layer with respect to a first layer: (A) colloidal silica particles having a negative ? potential; (B) phosphoric acid or an organic phosphonic acid compound represented by the following Formula (1) or (2); and (C) an anionic surfactant having at least one group represented by the following Formulae (I) to (IV): R2—C(R3)3-a—(PO3H2)a??Formula (1): R4—N(R5)m—(CH2—PO3H2)n??Formula (2): —PO3X2??Formula (I): —OPO3X2??Formula (II): —COOX??Formula (III): —SO3X??Formula (IV).

Abstract: A method for chemical mechanical polishing of a substrate is provided, comprising: providing a substrate, wherein the substrate comprises silicon oxide; providing a chemical mechanical polishing composition, comprising, as initial components: water; an abrasive; and a substance according to formula I wherein R1, R2 and R3 are each independently selected from a C1-4 alky group; providing a chemical mechanical polishing pad with a polishing surface; moving the polishing surface relative to the substrate; dispensing the chemical mechanical polishing composition onto the polishing surface; and, abrading at least a portion of the substrate to polish the substrate; wherein the substance according to formula I included in the chemical mechanical polishing composition provides an enhanced silicon oxide removal rate and an improved polishing defectivity performance; and, wherein at least some of the silicon oxide is removed from the substrate.

Abstract: An effective method for forming through-base wafer vias for the fabrication of stacked devices, such as electronic devices, is described. The base wafer can be a silicon wafer, in which case the method relates to TSV (through-silicon via) technology. The method affords high removal rates of silicon under appropriate conditions.

Abstract: A method for chemical mechanical polishing of a substrate is provided, comprising: providing a substrate, wherein the substrate comprises polysilicon and at least one of silicon oxide and silicon nitride; providing a chemical mechanical polishing composition, comprising, as initial components: water; an abrasive; and an alkyl aryl polyether sulfonate compound, wherein the alkyl aryl polyether sulfonate compound has a hydrophobic portion having an alkyl group bound to an aryl ring and a nonionic acyclic hydrophilic portion having 4 to 100 carbon atoms; providing a chemical mechanical polishing pad with a polishing surface; moving the polishing surface relative to the substrate; dispensing the chemical mechanical polishing composition onto the polishing surface; and, abrading at least a portion of the substrate to polish the substrate; wherein at least some of the polysilicon is removed from the substrate; and, wherein at least some of the at least one of silicon oxide and silicon nitride is removed from the su

Abstract: A method for chemical mechanical polishing of a substrate is provided, comprising: providing a substrate, wherein the substrate comprises polysilicon and at least one of silicon oxide and silicon nitride; providing a chemical mechanical polishing composition, comprising, as initial components: water; an abrasive; and an acyclic organosulfonic acid compound, wherein the acyclic organosulfonic acid compound has an acyclic hydrophobic portion having 6 to 30 carbon atoms and a nonionic acyclic hydrophilic portion having 10 to 300 carbon atoms; providing a chemical mechanical polishing pad with a polishing surface; moving the polishing surface relative to the substrate; dispensing the chemical mechanical polishing composition onto the polishing surface; and, abrading at least a portion of the substrate to polish the substrate; wherein at least some of the polysilicon is removed from the substrate; and, wherein at least some of the at least one of silicon oxide and silicon nitride is removed from the substrate.

Abstract: A method for chemical mechanical polishing of a substrate is provided, comprising: providing a substrate, wherein the substrate comprises polysilicon, silicon oxide and silicon nitride; providing a chemical mechanical polishing composition, comprising, as initial components: water; an abrasive; an alkyl aryl polyether sulfonate compound, wherein the alkyl aryl polyether sulfonate compound has a hydrophobic portion having an alkyl group bound to an aryl ring and a nonionic acyclic hydrophilic portion having 4 to 100 carbon atoms; and a substance according to formula I wherein each of R1, R2, R3, R4, R5, R6 and R7 is a bridging group having a formula —(CH2)n—, wherein n is an integer selected from 1 to 10; providing a chemical mechanical polishing pad with a polishing surface; moving the polishing surface relative to the substrate; dispensing the chemical mechanical polishing composition onto the polishing surface; and, abrading at least a portion of the substrate to polish the substrate; wherein at least s

Abstract: The present invention provides an aqueous CMP slurry composition that includes abrasive particles and from about 0.01% to the limit of solubility in water of a compound according to Formula (I): wherein only one of R1, R2, R3, R4 and R5 is a hydroxyl group (—OH), only one of R1, R2, R3, R4 and R5 is a methoxy group (—OCH3), and the three of R1, R2, R3, R4 and R5 that are not either a hydroxyl group (—OH) or a methoxy group (—OCH3) are hydrogen atoms (—H).

Abstract: A polishing composition is disclosed containing a nonionic active agent with a molecular weight of 1,000 or more and less than 100,000 and an HLB value of not less than 17, a basic compound, and water. The nonionic active agent is preferably an oxyalkylene homopolymer or a copolymer of different oxyalkylenes. The polishing composition may further contain at least one of silicon dioxide and a water-soluble polymer. The polishing composition is used, for example, in polishing the surface of semiconductor substrates such as silicon wafers.

Abstract: Processes for forming high density gap-filling silicon oxide on a patterned substrate are described. The processes increase the density of gap-filling silicon oxide particularly in narrow trenches. The density may also be increased in wide trenches and recessed open areas. The densities of the gap-filling silicon oxide in the narrow and wide trenches/open areas become more similar following the treatment which allows the etch rates to match more closely. This effect may also be described as a reduction in the pattern loading effect. The process involves forming then planarizing silicon oxide. Planarization exposes a new dielectric interface disposed closer to the narrow trenches. The newly exposed interface facilitates a densification treatment by annealing and/or exposing the planarized surface to a plasma.

Abstract: The present invention relates to a polishing composition used in a step of polishing until a barrier layer adjacent to a copper layer is exposed, in a pattern formation of polishing the copper layer provided on an insulating layer through the barrier layer thereby alternately forming a copper embedded wiring and the insulating layer, the polishing composition including: an alicyclic resin acid; a colloidal silica in which a content thereof in the polishing composition is from 0.1 to 1.5% by mass, an average primary particle size thereof is from 10 to 40 nm, an average secondary particle size thereof is from 30 to 80 nm, and (the average secondary particle size×the content) is in a range of from 10 to 40; and tetramethylammonium ion.

Abstract: Provided are a semiconductor memory device whereby generation of dishing during planarization of a peripheral circuit region is suppressed, and a method of fabricating the semiconductor memory device. The semiconductor memory device includes a semiconductor substrate comprising a first active area in a memory cell region and a second active area in a peripheral circuit region; a plurality of first isolation films and a plurality of second isolation films protruding from a surface of the semiconductor substrate and defining the first active area and the second active area, respectively; and at least one polish stopper film formed within the second active area and protruding from the surface of the semiconductor substrate.