Abstract: A wafer carrier with a wafer mounting plate disposed under a plenum which can be pressurized and depressurized to alter the shape of the wafer mounting plate and a plenum, formed with the wafer mounting plate and the wafer itself, to which vacuum can be applied to hold the wafer to the wafer mounting plate during polishing

Abstract: The invention provides a chemical-mechanical polishing composition comprising coated ?-alumina particles, an organic carboxylic acid, and water. The invention also provides a chemical-mechanical polishing composition comprising an abrasive having a negative zeta potential in the polishing composition, an organic carboxylic acid, at least one alkyldiphenyloxide disulfonate surfactant, and water, wherein the polishing composition does not further comprise a heterocyclic compound. The abrasive is colloidally stable in the polishing composition. The invention further provides methods of polishing a substrate with the aforesaid polishing compositions.

Abstract: System and method for implementing multi-resolution advanced process control (“APC”) are described. One embodiment is a method including obtaining low resolution metrology data and high resolution metrology data related to a process module for performing a process on the wafer. A process variable of the process is modeled as a function of the low resolution metrology data to generate a low-resolution process model and the process variable is modeled as a function of the high resolution metrology data to generate a high-resolution process model.

Abstract: The CMP polishing liquid of the invention is used by mixing a first solution and a second solution, the first solution comprises cerium-based abrasive grains, a dispersant and water, the second solution comprises a polyacrylic acid compound, a surfactant, a pH regulator, a phosphoric acid compound and water, the pH of the second solution is 6.5 or higher, and the first solution and second solution are mixed so that the phosphoric acid compound content is within a prescribed range. The CMP polishing liquid of the invention comprises cerium-based abrasive grains, a dispersant, a polyacrylic acid compound, a surfactant, a pH regulator, a phosphoric acid compound and water, with the phosphoric acid compound content being within a prescribed range.

Abstract: An object is to provide a semiconductor device with a novel structure. A semiconductor device includes a first transistor, which includes a channel formation region provided in a substrate including a semiconductor material, impurity regions, a first gate insulating layer, a first gate electrode, and a first source electrode and a first drain electrode, and a second transistor, which includes an oxide semiconductor layer over the substrate including the semiconductor material, a second source electrode and a second drain electrode, a second gate insulating layer, and a second gate electrode. The second source electrode and the second drain electrode include an oxide region formed by oxidizing a side surface thereof, and at least one of the first gate electrode, the first source electrode, and the first drain electrode is electrically connected to at least one of the second gate electrode, the second source electrode, and the second drain electrode.

Abstract: A method of manufacturing a semiconductor device, includes a wafer grinding step of, by means of a revolving grinding stone, forming a thinned portion in a wafer while at the same time forming a slope surrounding said thinned portion, wherein during said formation of said slope, said grinding stone is positioned so that there is always a space between said slope and the facing side of said grinding stone, wherein said thinned portion is thinner than a peripheral portion of said wafer, and wherein said slope extends along and defines an inner circumferential side of said peripheral portion and forms an angle of 75° or more but less than 90° with respect to a main surface of said wafer. The method of manufacturing a semiconductor device further includes a step of forming a semiconductor device in said thinned portion.

Abstract: A semiconductor process includes the following steps. A first gate structure and a second gate structure are formed on a substrate, wherein the top of the first gate structure includes a cap layer, so that the vertical height of the first gate structure is higher than the vertical height of the second gate structure. An interdielectric layer is formed on the substrate. A first chemical mechanical polishing process is performed to expose the top surface of the cap layer. A second chemical mechanical polishing process is performed to expose the top surface of the second gate structure or an etching process is performed to remove the interdielectric layer located on the second gate structure. A second chemical mechanical polishing process is then performed to remove the cap layer.

Abstract: A method for chemical mechanical polishing of a copper substrate, is provided, comprising: providing a copper substrate; providing slurry composition comprising, as initial components: water; 0.1 to 20 wt % abrasive; 0.01 to 15 wt % complexing agent; 0.02 to 5 wt % inhibitor; 0.01 to 5 wt % phosphorus containing compound; 0.001 to 3 wt % polyvinyl pyrrolidone; >0.1 to 1 wt % histidine; >0.1 to 1 wt % guanidine; optional oxidizing agent; optional leveling agent; optional biocide; and, optional pH adjusting agent; wherein the slurry composition provided has pH of 9 to 11; providing a chemical mechanical polishing pad with a polishing surface; dispensing the slimy composition onto the polishing surface at or near the interface between the polishing surface and the substrate; and, creating dynamic contact at an interface between the polishing surface and the substrate with a down force of 0.69 to 34.5 kPa; wherein the substrate is polished.

Abstract: According to one embodiment, a semiconductor device manufacturing method is provided. In the semiconductor device manufacturing method, a process target film is formed on a semiconductor substrate, and the surface of the process target film is polished by a CMP method. The CMP method comprises heating a rotating polishing pad from a first temperature to a second temperature higher than the first temperature, and bringing the surface of the process target film into contact with the polishing pad heated to the second temperature.

Abstract: [Problems] An object of the present invention is to provide a cleaning liquid composition which removes residual liquid and contaminants after chemical-mechanical polishing (CMP) of the surface of a semiconductor substrate in the production process of a semiconductor circuit device; and a cleaning method using the cleaning liquid composition. [Means for Solution] The cleaning liquid composition according to the present invention comprises a quaternary ammonium hydroxide, 1-ethinyl-1-cyclohexanol, a complexing agent, diethylenetriamine pentamethylene phosphonate and water and has a pH of 9 to 13. By cleaning a wiring material with the cleaning liquid composition according to the present invention, the wiring material can be protected against contamination, corrosion, oxidation and generation of foreign substance that are originated from the production process of a semiconductor circuit device or the environment, so that a clean wiring surface can be obtained.

Abstract: A polishing composition contains at least one water soluble polymer selected from the group consisting of polyvinylpyrrolidone and poly(N-vinylformamide), and an alkali, and preferably further contains at least one of a chelating agent and an abrasive grain. The water soluble polymer preferably has a weight average molecular weight of 6,000 to 4,000,000. The polishing composition is mainly used in polishing of the surfaces of semiconductor wafers such as silicon wafers, especially used in preliminary polishing of the surfaces of such wafers.

Abstract: The present invention relates to a method for fabrication of in-laid metal interconnects. The method comprises the steps of providing a substrate with a dielectric material on top thereof, depositing a protection layer on top of the dielectric material, depositing a sacrificial layer on top of the protection layer, the sacrificial layer having a mechanical strength that is lower than the mechanical strength of the protection layer, making an opening) through the sacrificial layer, through the protection layer and into the dielectric material, depositing a barrier layer in the opening and on the sacrificial layer, depositing metal material on the barrier layer, the metal material filling the opening, removing portions of the metal material existing beyond the opening by means of polishing, and removing the barrier layer and the sacrificial layer in one polishing step.

Abstract: A method for manufacturing TSVs comprises following steps: A stack structure having a substrate, an ILD layer and a dielectric stop layer is provided, in which an opening penetrating through the ILD layer and the dialectic stop layer and further extending into the substrate is formed. After an insulator layer and a metal barrier are formed on the stack structure, a top metal layer is formed on the stack structure to fulfill the opening. A first planarization process stopping on the metal barrier is conducted, wherein the first planarization process has a polishing rate for removing the metal barrier less than that for removing the top metal layer. A second planarization process stopping on the dielectric stop layer is conducted, wherein the second planarization process has a polishing rate for removing the insulator layer greater than that for removing the dielectric stop layer. The dielectric stop layer is than removed.

Abstract: The present invention relates to a polishing slurry for performing chemical mechanical polishing on a surface to be polished including a surface made of silicon oxide and a surface made of metal, characterized in that it includes cerium oxide particles, a complexing agent, and water.

Abstract: According to example embodiments, a methods includes forming a peripheral structure including peripheral circuits on a peripheral circuits region of a substrate, recessing a cell array region of the substrate to form a concave region having a bottom surface lower than a top surface of the peripheral structure, forming a stacked layer structure conformally covering the concave region, the stacked layer structure including a plurality of layers sequentially stacked and having a lowest top surface in the cell array region and a highest top surface in the peripheral circuits region, forming a planarization stop layer that conformally covers the stacked layer structure, and planarizing the stacked layer structure using the planarization stop layer in the cell array region as a planarization end point to expose top surfaces of the thin layers between the cell array region and the peripheral circuits region simultaneously with a top surface of the peripheral structure.

Abstract: A method for manufacturing TSVs, wherein the method comprises several steps as follows: A stack structure having a substrate and an ILD layer (inter layer dielectric layer) is provided, in which an opening penetrating through the ILD layer and further extending into the substrate is formed. After an insulator layer and a metal barrier layer are formed on the stack structure and the sidewalls of the opening, a top metal layer is then formed on the stack structure to fulfill the opening. A first planarization process stopping on the barrier layer is conducted to remove a portion of the top metal layer. A second planarization process stopping on the ILD layer is subsequently conducted to remove a portion of the metal barrier layer, a portion of the insulator layer and a portion of the top metal layer, wherein the second planarization process has a polishing endpoint determined by a light interferometry or a motor current.

Abstract: A chemical-mechanical polishing composition comprising: (a) at least one type of abrasive particles; (b) at least two oxidizing agents; (c) at least one pH adjusting agent; and (d) deionized water; (e) optionally comprising at least one antioxidant, and a method for the chemical-mechanical planarization of a substrate containing at least one copper layer, at least one ruthenium layer, and at least one tantalum layer comprising the steps of (1) providing the said chemical-mechanical polishing composition; (2) contacting the substrate surface to be polished with the chemical-mechanical polishing composition and a polishing pad; and (3) chemically and mechanically polishing the substrate surface by way of moving the polishing pad relative to the substrate.

Abstract: A method including forming an organic polymer layer (OPL) on a substrate; forming a patterned photoresist layer having a first opening and a second opening over the OPL, the second opening wider than the first opening; performing a first reactive ion etch (RIE) to form a first trench and a second trench in the organic layer, the second trench wider than the first trench, the first trench extending into but not through the organic polymer layer, the second trench extending through the OPL to the substrate, the first RIE forming a first polymer layer on sidewalls of the first trench and a second polymer layer on sidewalls of the second trench, the second polymer layer thicker than the first polymer layer; and performing a second RIE to extend the first trench through the OPL to the substrate, the second RIE removing the second polymer layer from sidewalls of the second trench.

Abstract: According to one embodiment, a method of manufacturing a semiconductor device, the method includes forming a pillar on a base layer, forming a insulating layer on the base layer to cover the pillar by using GCIB method, where a lowermost portion of an upper surface of the insulating layer is lower than an upper surface of the pillar, and polishing the insulating layer and the pillar to expose a head of the pillar by using CMP method, where an end point of the polishing is the lowermost portion of the upper surface of the insulating layer.

Abstract: A method and associated composition for CMP processing of noble metal-containing substrates (such as ruthenium-containing substrates) afford both high removal rates of the noble metal and are tunable with respect to rate of noble metal removal in relation to removal of other films. Low levels of an oxidizing agent containing one or more peroxy-functional group(s) can be used along with a novel ligand to effectively polish noble metal substrates.

Abstract: A dispenser for a chemical-mechanical polishing (CMP) apparatus, includes a delivery arm disposed over a polishing pad of a CMP apparatus, at least a slurry delivery groove formed in the delivery arm and extending along a length of the delivery arm, and a plurality of first openings connected to the slurry delivery groove.

Abstract: An aqueous polishing agent, comprising, as the abrasive, at least one kind of polymer particles (A) finely dispersed in the aqueous phase and having at their surface a plurality of at least one kind of functional groups (al) capable of interacting with the metals and/or the metal oxides on top of the surfaces to be polished and forming complexes with the said metals and metal cations, the said polymer particles (A) being preparable by the emulsion or suspension polymerization of at least one monomer containing at least one radically polymerizable double bond in the presence of at least one oligomer or polymer containing a plurality of functional groups (a1); graft copolymers preparable by the emulsion or suspension polymerization of at least one monomer containing at least one radically polymerizable double bond in the presence of at least one oligomeric or polymeric aminotriazine-polyamine condensate; and a process for the chemical and mechanical polishing of patterned and unstructured metal surfaces making

Abstract: A one-step CMP process for polishing three or more layer film stacks on a wafer having a multilayer film stack thereon including a silicon nitride (SiNx) layer on its semiconductor surface, and a silicon oxide layer on the SiNx layer, wherein trench access vias extend through the silicon oxide layer and SiNx layer to trenches formed into the semiconductor surface, and wherein a polysilicon layer fills the trench access vias, fills the trenches, and is on the silicon oxide layer. CMP polishes the multilayer film stack with a slurry including slurry particles including at least one of silica and ceria. The CMP provides a removal rate (RR) for the polysilicon layer > a RR for the silicon oxide layer > a RR for the SiNx layer. The CMP process is continued to remove the polysilicon layer, silicon oxide layer and a portion of the SiNx layer to stop on the SiNx layer. Optical endpointing during CMP can provide a predetermined remaining thickness range for the SiNx layer.

Abstract: An object of the present invention is to provide a polishing liquid for CMP with which polishing scratches can be reduced and a sufficiently high polishing rate can be obtained in a CMP step for an ILD film, aggregation of an abrasive grain is difficult to occur, and high flatness is obtained, and provide a polishing method using the same. The polishing liquid for CMP according to the present invention is a polishing liquid for CMP containing an abrasive grain, an additive, and water, wherein the abrasive grain comprises a cerium-based particle, and the additive comprises a 4-pyrone-based compound and at least one of a nonionic surfactant or a cationic surfactant: [wherein X11, X12, and X13 each independently represent a hydrogen atom or a monovalent substituent.

Abstract: A method of polishing copper wiring surfaces of in ultra large scale integrated circuit, the method including: a) preparing a polishing solution including between 35 and 80 w. % of a nano SiO2 abrasive, between 12 and 60 w. % of deionized water, between 1 and 3 w. % of an oxidant, between 1 and 4 w. % of an active agent, and between 0.5 and 1.5 w. % of a chelating agent; and b) polishing using the polishing solution under following conditions: between 2 and 5 kPa pressure; between 20 and 50° C.; between 120 and 250 mL/min slurry flow rate; and at between 30 and 60 rpm/min rotational speed.

Abstract: Embodiments of the invention include methods and structures for fabricating a semiconductor structure, and, particularly for improving the planarity of a bonded semiconductor structure comprising a processed semiconductor structure and a semiconductor structure.

Abstract: The present invention discloses a method for fabricating semiconductor devices. After removing excessive aluminium to form aluminium gates through a chemical mechanical planarization (CMP) process, the exposed surfaces of the aluminium gates are oxidized with H2O2 solution to form a film of alumina, and the semiconductor device is cleaned.

Abstract: A method of fabricating a semiconductor device includes dressing a surface of a polishing pad with a conditioning disk held by an arm while rotating a platen that holds the polishing pad in a chemical mechanical polishing apparatus, wherein the dressing is performed by pressing the conditioning disk to the polishing pad, and rotating the arm around a rotational axis of the arm thereby to move the conditioning disk substantially along a radius direction of the platen between a center part and a circumferential part of the platen, and wherein torque N applied to the arm is measured at plural positions of the conditioning disk along the substantial radius direction during the dressing, and it is determined whether maintenance to the arm is necessary in accordance with an average value <N> of the measured torques N and a fluctuation range Y of the measured torques N.

Abstract: A non-polished glass wafer, a thinning system, and a method for using the non-polished glass wafer to thin a semiconductor wafer are described herein. In one embodiment, the glass wafer has a body (e.g., circular body) including a non-polished first surface and a non-polished second surface substantially parallel to each other. In addition, the circular body has a wafer quality index which is equal to a total thickness variation in micrometers plus one-tenth of a warp in micrometers that is less than 6.0.

Abstract: The CMP polishing liquid of the invention is used by mixing a first solution and a second solution, the first solution comprises cerium-based abrasive grains, a dispersant and water, the second solution comprises a polyacrylic acid compound, a surfactant, a pH regulator, a phosphoric acid compound and water, the pH of the second solution is 6.5 or higher, and the first solution and second solution are mixed so that the phosphoric acid compound content is within a prescribed range. The CMP polishing liquid of the invention comprises cerium-based abrasive grains, a dispersant, a polyacrylic acid compound, a surfactant, a pH regulator, a phosphoric acid compound and water, with the phosphoric acid compound content being within a prescribed range.

Abstract: Provided is a polishing composition used for polishing a semiconductor wafer surface having a step in order to planarize the wafer surface and thereby reclaiming the semiconductor wafer. The polishing composition contains at least a step eliminating agent, which is adsorbed to the surface of the semiconductor wafer and acts to prevent etching of bottom portion of the step on the wafer surface during polishing. The step eliminating agent is, for example, a water-soluble polymer or a surfactant, and more specifically, a polyvinyl alcohol, a polyvinyl pyrrolidone, a polyethylene glycol, a cellulose, a carboxylic acid surfactant, a sulfonic acid surfactant, a phosphate ester surfactant, or an oxyalkylene polymer.

Abstract: A chemical mechanical polishing pad having a polishing layer with an integral window and a polishing surface adapted for polishing a substrate selected from a magnetic substrate, an optical substrate and a semiconductor substrate, wherein the formulation of the integral window provides improved defectivity performance during polishing. Also provided is a method of polishing a substrate using the chemical mechanical polishing pad.

Abstract: A planarization process for a pre-damascene structure is described, wherein the pre-damascene structure includes a metal hard mask that is disposed on a first material layer with a damascene opening therein and a second material layer that fills the damascene opening and covers the metal hard mask. A first CMP step is conducted using a first slurry to remove the second material layer outside the damascene opening. A second CMP step is conducted using a second slurry to remove the metal hard mask.

Abstract: A method for chemical mechanical polishing of a substrate comprising a germanium-antimony-tellurium chalcogenide phase change alloy (GST) using a chemical mechanical polishing composition consisting essentially of, as initial components: water; an abrasive; a material selected from ethylene diamine tetra acetic acid and salts thereof; and an oxidizing agent; wherein the chemical mechanical polishing composition facilitates a high GST removal rate with low defectivity.

Abstract: Disclosed herein is a CMP slurry composition. The CMP slurry composition includes cerium oxide particles, an adsorbent for adsorbing the cerium oxide particles to a polishing pad, an adsorption adjusting agent for adjusting adsorption performance of the adsorbent, and a pH adjusting agent. The CMP slurry composition may improve polishing efficiency of a patterned oxide layer and lifespan of a diamond disc conditioner.

Abstract: A chemical mechanical polishing (CMP) stop layer is implemented in a semiconductor fabrication process. The CMP stop layer, among other things, mitigates erosion of sidewall spacers during semiconductor fabrication and adverse effects associated therewith.

Abstract: The present invention relates to a polishing composition used in a step of polishing until a barrier layer adjacent to a copper layer is exposed, in a pattern formation of polishing the copper layer provided on an insulating layer through the barrier layer thereby alternately forming a copper embedded wiring and the insulating layer, the polishing composition including: an alicyclic resin acid; a colloidal silica in which a content thereof in the polishing composition is from 0.1 to 1.5% by mass, an average primary particle size thereof is from 10 to 40 nm, an average secondary particle size thereof is from 30 to 80 nm, and (the average secondary particle size×the content) is in a range of from 10 to 40; and tetramethylammonium ion.

Abstract: A method for chemical mechanical polishing of a substrate comprising a germanium-antimony-tellurium chalcogenide phase change alloy (GST) using a chemical mechanical polishing composition consisting essentially of, as initial components: water; an abrasive; a material selected from ethylene diamine tetra acetic acid and salts thereof; and an oxidizing agent; wherein the chemical mechanical polishing composition facilitates a high GST removal rate with low defectivity.

Abstract: A method for planarizing a semiconductor device includes providing a substrate having at least one opening therein, each opening defining a lower portion and an upper portion; coating a light sensitive material layer over the substrate, the light sensitive material layer covering the lower and upper portions of the at least one opening; etching back the light sensitive material layer to expose the upper portion of the at least one opening; repeating the steps of coating and etching to remove a predetermined amount below the upper portion of the at least one opening; depositing an insulating layer over the substrate; and planarizing the insulating layer until the upper portion of the at least one opening is exposed.

Abstract: The present invention provides a slurry for chemical mechanical polishing comprising water-soluble clathrate compound (a), polymer compound (b) having an acidic group optionally in a salt form as a side chain, polishing abrasive grain (c) and water (d), wherein the content of the water-soluble clathrate compound (a) is 0.001 mass %-3 mass % of the total amount of the slurry, the polymer compound (b) has a weight average molecular weight of not less than 1,000 and less than 1,000,000, and the content of the polymer compound (b) is 0.12 mass %-3 mass % of the total amount of the slurry, and a polishing method for substrate using the slurry.

Abstract: The present invention relates to a CMP slurry composition comprising an abrasive particle; a dispersant; an ionic polymer additive; and a non-ionic polymer additive including a polyolefin-polyethylene glycol copolymer including at least two polyethylene glycol repeat unit as a backbone and at least a polyethylene glycol repeating unit as a side chain, and a polishing method with using the slurry composition. The CMP slurry composition shows a low polishing rate to a single-crystalline silicon layer or a polysilicon layer and a high polishing rate to a silicon oxide layer, resulting in having an excellent polishing selectivity.

Abstract: A chemical mechanical polishing slurry for polishing a copper layer without excessively or destructively polishing a barrier layer beneath the copper layer is disclosed and includes an acid, a surfactant, and a silica sol having silica polishing particles that are surface modified with a surface charge modifier and that have potassium ions attached thereto. A method for preparing the chemical mechanical polishing slurry and a chemical mechanical polishing method using the chemical mechanical polishing slurry are also disclosed.

Abstract: A chemical mechanical polishing (CMP) method is provided The method is capable of polishing a substrate in a CMP apparatus by using a hydrophobic polishing pad and includes following steps. A first CMP process is performed to the substrate. A first cleaning process is performed to the hydrophobic polishing pad. A second CMP process is performed to the substrate, wherein the first CMP process, the first cleaning process and the second CMP process are performed in sequence.

Abstract: A chemical mechanical polishing (CMP) process includes steps of providing a substrate, performing a first polishing step to the substrate with an acidic slurry, and performing a second polishing step to the substrate with a basic slurry after the first polishing step.

Abstract: A method of shaping a substrate in one embodiment includes providing a first support layer, providing a first shaping pattern on the first support layer, providing a substrate on the first shaping pattern, performing a first chemical mechanical polishing (CMP) process on the substrate positioned on the first shaping pattern, and removing the once polished substrate from the first shaping pattern.

Abstract: A method of fabricating the semiconductor component including following steps is provided. A substrate is provided, wherein an opening is already formed in the substrate. A material layer is formed on the substrate, wherein the material layer fills up the opening, and the material layer outside and above the opening has a recess therein. A sacrifice layer is formed on a surface of the recess. A chemical mechanical polishing (CMP) process is performed to remove the sacrifice layer and the material layer outside the opening, wherein a polishing rate of the CMP process on the material layer is greater than that of the CMP process on the sacrifice layer.

Abstract: The present invention provides an acidic aqueous polishing composition suitable for polishing a silicon nitride-containing substrate in a chemical-mechanical polishing (CMP) process. The composition, at point of use, comprises about 0.01 to about 2 percent by weight of a particulate calcined ceria abrasive, about 10 to about 1000 ppm of at least one cationic polymer, optionally, about 10 to about 2000 ppm of a polyoxyalkylene polymer; and an aqueous carrier therefor. The at least one cationic polymer is selected from a poly(vinylpyridine) polymer and a combination of a poly(vinylpyridine) polymer and a quaternary ammonium-substituted polymer. Methods of polishing substrates and of selectively removing silicon nitride from a substrate in preference to removal of polysilicon using the compositions are also provided.

Abstract: A metal polishing slurry includes a chemical solution and abrasives characterized by a bimodal or other multimodal distribution of particle sizes or a prevalence of two or more particle sizes or ranges of particle sizes. A method and system for using the slurry in a CMP polishing operation, are also provided.

Abstract: A blanket stop layer is conformally formed on a layer with a large step height. A first chemical mechanical polishing process is performed to remove the blanket stop layer atop the layer in the raised region. A second chemical mechanical polishing process is performed to planarize the wafer using the blanket stop layer as a stop layer when the layer is lower than or at a same level as the blanket stop layer or using the layer as a stop layer when the blanket stop layer is lower than or at a same level as the layer, or a selective dry etch is performed to remove the layer in the raised region. Thus, the layer in the raised region can be easily removed without occurrence of dishing in the non-raised region which is protected by the blanket stop layer.

Abstract: Solutions for forming an integrated circuit structure having a substantially planar N-P step height are disclosed. In one embodiment, a method includes: providing a structure having an n-type field effect transistor (NFET) region and a p-type field effect transistor (PFET) region; forming a mask over the PFET region to leave the NFET region exposed; performing dilute hydrogen-flouride (DHF) cleaning on the exposed NFET region to substantially lower an STI profile of the NFET region; and forming a silicon germanium (SiGE) channel in the PFET region after the performing of the DHF.