Abstract: A polishing composition contains at least abrasive grains and water and is used in polishing an object to be polished. The abrasive grains are selected so as to satisfy the relationship X1×Y1?0 and the relationship X2×Y2>0, where X1 [mV] represents the zeta potential of the abrasive grains measured during polishing of the object by using the polishing composition, Y1 [mV] represents the zeta potential of the object measured during polishing of the object by using the polishing composition, X2 [mV] represents the zeta potential of the abrasive grains measured during washing of the object after polishing, and Y2 [mV] represents the zeta potential of the object measured during washing of the object after polishing. The abrasive grains are preferably of silicon oxide, aluminum oxide, cerium oxide, zirconium oxide, silicon carbide, or diamond. The object is preferably of a nickel-containing alloy, silicon oxide, or aluminum oxide.

Abstract: A method for forming a field-effect transistor with a raised drain structure is disclosed. The method includes depositing a low-k inter-metal layer over a semiconductor substrate, depositing a porogen-containing low-k layer over the low-k inter-metal layer, and etching a space for the via through the low-k inter-metal layer and the porogen-containing low-k layer. The method further includes depositing a metal layer, a portion of the metal layer filling the space for the via, another portion of the metal layer being over the porogen-containing low-layer, removing the portion of the metal layer over the porogen-containing layer by a CMP process, and curing the porogen-containing low-k layer to form a cured low-k layer.

Abstract: An integrated tool to reduce defects in manufacturing a semiconductor device by reducing queue times during a manufacturing process. The integrated tool may include at least one a polishing tool comprising at least one polishing module and at least one deposition tool comprising at least one deposition chamber. At least one pump-down chamber may connect the polishing tool to the deposition tool. The at least one pump-down chamber includes a passage through which the semiconductor device is passed. Defects in the semiconductor device are reduced by reducing the queue time at various stages of the fabrication process.

Abstract: A semiconductor light emitting device (10) comprises a semiconductor structure (12) comprising a first body (14) of a first semiconductor material (in this case Ge) comprising a first region of a first doping kind (in this case n) and a second body (18) of a second semiconductor material (in this case Si) comprising a first region of a second doping kind (in this case p). The structure comprises a junction region (15) comprising a first heterojunction (16) formed between the first body (14) and the second body (18) and a pn junction (17) formed between regions of the structure of the first and second doping kinds respectively. A biasing arrangement (20) is connected to the structure for, in use, reverse biasing the pn junction, thereby to cause emission of light.

Abstract: A method of forming interlayer dielectric comprising the steps of forming a first undoped layer, forming in-situ and sequentially a doped layer and a second undoped layer on the first undoped layer, and planarizing the second undoped layer.

Abstract: This description relates to a gate electrode of a field effect transistor. An exemplary structure for a field effect transistor includes a substrate; a gate electrode over the substrate including a first top surface and a sidewall; a source/drain (S/D) region at least partially disposed in the substrate on one side of the gate electrode; a spacer on the sidewall distributed between the gate electrode and the S/D region; and a contact etch stop layer (CESL) adjacent to the spacer and further comprising a portion extending over the S/D region, wherein the portion has a second top surface substantially coplanar with the first top surface.

Abstract: A method of producing a radiographic image detector includes: preparing a thin-film transistor substrate comprising an insulating substrate and a thin-film transistor that is disposed on a surface of the insulating substrate at a first side; attaching, to the thin-film transistor substrate, a protective member comprising a protective member support and an adhesive layer that includes conductive particles and that is disposed on the protective member support, such that the adhesive layer and a surface of the thin-film transistor substrate at the first side contact each other; polishing a surface of the thin-film transistor substrate at a second side opposite to the first side, after the attaching of the protective member; separating and removing the protective member from the thin-film transistor substrate after the polishing; and providing a scintillator layer on a surface of the thin-film transistor substrate at the first side, after the removing of the protective member.

Abstract: A semiconductor process includes the following steps. A first gate structure and a second gate structure are formed on a substrate, wherein the top of the first gate structure includes a cap layer, so that the vertical height of the first gate structure is higher than the vertical height of the second gate structure. An interdielectric layer is formed on the substrate. A first chemical mechanical polishing process is performed to expose the top surface of the cap layer. A second chemical mechanical polishing process is performed to expose the top surface of the second gate structure or an etching process is performed to remove the interdielectric layer located on the second gate structure. A second chemical mechanical polishing process is then performed to remove the cap layer.

Abstract: A dielectric layer is deposited on a working surface of a substrate, wherein the dielectric layer contains or consists of a dielectric polymer. The dielectric layer is partially cured. A portion of the partially cured dielectric layer is removed using a chemical mechanical polishing process. Then the curing of remnant portions of the partially cured dielectric layer is continued to form a dielectric structure. The partially cured dielectric layer shows high removal rates during chemical mechanical polishing. With remnant portions of the dielectric layer provided in cavities, high volume insulating structures can be provided in an efficient manner.

Abstract: A method of manufacturing a semiconductor structure includes varying local chemical mechanical polishing (CMP) abrading rates of an insulator film by selectively varying a carbon content of the insulator film.

Abstract: The present invention provides chemical-mechanical polishing (CMP) compositions suitable for polishing a substrate comprising a germanium-antimony-tellurium (GST) alloy. The CMP compositions of the present invention are aqueous slurries comprising a particulate abrasive, a water-soluble surface active agent, a complexing agent, and a corrosion inhibitor. The ionic character of the surface active material (e.g., cationic, anionic, or nonionic) is selected based on the zeta potential of the particulate abrasive. A CMP method for polishing a GST alloy-containing substrate utilizing the composition is also disclosed.

Abstract: The present invention provides an acidic aqueous polishing composition suitable for polishing a silicon nitride-containing substrate in a chemical-mechanical polishing (CMP) process. The composition, at point of use, preferably comprises about 0.01 to about 2 percent by weight of at least one particulate ceria abrasive, about 10 to about 1000 ppm of at least one non-polymeric unsaturated nitrogen heterocycle compound, 0 to about 1000 ppm of at least one cationic polymer, optionally, 0 to about 2000 ppm of at least one polyoxyalkylene polymer, and an aqueous carrier therefor. The cationic polymer preferably is selected from a poly(vinylpyridine) polymer, a quaternary ammonium-substituted acrylate polymer, a quaternary ammonium-substituted methacrylate polymer, or a combination thereof. Methods of polishing substrates and of selectively removing silicon nitride from a substrate in preference to removal of polysilicon using the compositions are also provided.

Abstract: Closed loop control may be used to improve uniformity of within wafer uniformity using chemical mechanical planarization. For example, closed loop control may be used to determine a control profile for a chemical mechanical planarization process to more uniformly and consistently achieve the desired extent of variation of within wafer uniformity of a semiconductor wafer.

Abstract: A system and method for mitigating annealing fingerprints in semiconductor wafers is provided. An embodiment comprises aligning the semiconductor wafers prior to each annealing step. This alignment generates similar or identical fingerprints in each of the semiconductor wafers manufactured. With the fingerprint known, a single compensation model for a subsequent photoresist may be utilized to compensate for the fingerprint in each of the semiconductor wafers.

Abstract: The invention provides a chemical-mechanical polishing composition comprising coated ?-alumina particles, an organic carboxylic acid, and water. The invention also provides a chemical-mechanical polishing composition comprising an abrasive having a negative zeta potential in the polishing composition, an organic carboxylic acid, at least one alkyldiphenyloxide disulfonate surfactant, and water, wherein the polishing composition does not further comprise a heterocyclic compound. The abrasive is colloidally stable in the polishing composition. The invention further provides methods of polishing a substrate with the aforesaid polishing compositions.

Abstract: Chemical-Mechanical Polishing can be used to planarize a semiconductor wafer having a patterned overlapping layer. Isotropic etching can remove a portion of the patterned overlapping layer to produce tapered sidewalls of reduced height. A portion of the overlapping layer can be removed using CMP. The overlapping layer can have a higher polishing rate than the underlying layer so that the underlying layer remains substantially intact after removing the overlying layer.

Abstract: A nitride semiconductor substrate includes two principal surfaces including an upper surface that is a growth face and a lower surface on its opposite side. An FWHM in a surface layer region at depths of from 0 to 250 nm from the upper surface is narrower than an FWHM in an inner region at depths exceeding 5 ?m from the upper surface, where the FWHMs are obtained by X-ray rocking curve measurement using diffraction off a particular asymmetric plane inclined relative to the upper surface.

Abstract: The polishing solution for CMP of the invention comprises abrasive grains, a first additive and water, wherein the first additive is at least 1,2-benzoisothiazole-3(2H)-one or 2-aminothiazole. The polishing method of the invention is a polishing method for a substrate having a silicon oxide film on the surface, and the polishing method comprises a step of polishing the silicon oxide film with a polishing pad while supplying the polishing solution for CMP between the silicon oxide film and the polishing pad.

Abstract: A blanket stop layer is conformally formed on a layer with a large step height. A first chemical mechanical polishing process is performed to remove the blanket stop layer atop the layer in the raised region. A second chemical mechanical polishing process is performed to planarize the wafer using the blanket stop layer as a stop layer when the layer is lower than or at a same level as the blanket stop layer or using the layer as a stop layer when the blanket stop layer is lower than or at a same level as the layer, or a selective dry etch is performed to remove the layer in the raised region. Thus, the layer in the raised region can be easily removed without occurrence of dishing in the non-raised region which is protected by the blanket stop layer.

Abstract: According to one embodiment, a semiconductor device manufacturing method is disclosed. The method can include polishing a film on a semiconductor substrate by pressing the film against a polishing pad. Polishing the film comprises performing first polishing in which an entrance temperature of the polishing pad is adjusted to 40° C. (inclusive) to 50° C. (inclusive), and an exit temperature of the polishing pad is adjusted to be higher by 5° C. or more than the entrance temperature. Polishing the film comprises performing second polishing in which the entrance temperature is adjusted to 30° C. or less, and the exit temperature is adjusted to be higher by 5° C. or more than the entrance temperature.

Abstract: The present invention provides a final polishing method for a silicon single crystal wafer that performs final polishing with a polishing rate being set to 10 nm/min or below at a final polishing step as a final step among a plurality of polishing steps for polishing the silicon single crystal wafer with a polishing slurry being interposed between the silicon single crystal wafer and a polishing pad, and a silicon single crystal wafer subjected to final polishing by this method. Hereby, there can be provided the final polishing method that can obtain a silicon single crystal wafer with less PIDs (Polishing Induced Defects) and the silicon single crystal wafer subjected to final polishing by this method.

Abstract: A method for optimizing masks used for forming conductive features and a method for creating the mask features on an IC device are disclosed. An exemplary embodiment includes receiving a design database including a plurality of conductive features. First and second features suitable for joining are identified from the plurality of conductive features. A joined feature corresponding to the first and the second features is characterized. A cut shape configured to separate the first and second features from the joined feature is also characterized. The joined feature is categorized into a first conductive mask, the cut shape is categorized into a cut mask, and a third feature is categorized into a second conductive mask. The categorized shapes and features of the first conductive mask, the second conductive mask, and the cut mask are provided for manufacturing a mask set corresponding to the categorized shapes and features.

Abstract: A method of controlling a polishing operation includes polishing a substrate, during polishing obtaining a sequence over time of measured spectra from the substrate with an in-situ optical monitoring system, for each measured spectrum from the sequence of measured spectra applying a Fourier transform to the measured spectrum to generate a transformed spectrum thus generating a sequence of transformed spectra, for each transformed spectrum identifying a peak of interest from a plurality of peaks in the transformed spectrum, for each transformed spectrum determining a position value for the peak of interest in the transformed spectrum thus generating a sequence of position values, and determining at least one of a polishing endpoint or an adjustment of a pressure to the substrate from the sequence of position values.

Abstract: A polishing slurry includes an abrasive, a dispersion agent, a polish accelerating agent and an adhesion inhibitor. The adhesion inhibitor includes a benzene compound combined with a carboxyl group. Methods of planarizing an insulating layer using the slurry are also provided.

Abstract: A method includes providing a first mask pattern over a substrate, forming first spacers adjoining sidewalls of the first mask pattern, removing the first mask pattern, forming second spacers adjoining sidewalls of the first spacers, forming a filling layer over the substrate and between the second spacers, and forming a second mask pattern over the substrate.

Abstract: A polishing composition that can improve polishing property without foaming is provided. A polishing composition includes a pH regulator, a water-soluble polymer compound, and a compound containing an alkylene diamine structure having two nitrogens represented by the following general formula (1), and having at least one block type polyether bonded to the two nitrogens of the alkylene structure, the block type polyether having a bond of an oxyethylene group and an oxypropylene group: where R represents an alkylene group represented by CnH2n, in which n is an integer of 1 or more.

Abstract: Closed loop control may be used to improve uniformity of contact or via critical dimension using chemical mechanical planarization. For example, real-time closed loop control may be used to adjust oxide buffing or over-polishing time in a chemical mechanical planarization process to more uniformly and consistently achieve a target critical dimension of a semiconductor wafer.

Abstract: A method of fabricating a semiconductor device is disclosed. The exemplary method includes providing a substrate including a device layer and a sacrificial layer formed over the device layer and patterning the sacrificial layer thereby defining a cut pattern. The cut pattern of the sacrificial layer having an initial width. The method further includes depositing a mask layer over the device layer and over the cut pattern of the sacrificial layer. The method further includes patterning the mask layer thereby defining a line pattern including first and second portions separated by the cut pattern of the sacrificial layer and selectively removing the cut pattern of the sacrificial layer thereby forming a gap that separates the first and second portions of the line pattern of the mask layer. The method further includes patterning the device layer using the first and second portions of the line pattern of the mask layer.

Abstract: Hardmask films having high hardness and low stress are provided. In some embodiments a film has a stress of between about ?600 MPa and 600 MPa and hardness of at least about 12 GPa. In some embodiments, a hardmask film is prepared by depositing multiple sub-layers of doped or undoped silicon carbide using multiple densifying plasma post-treatments in a PECVD process chamber. In some embodiments, a hardmask film includes a high-hardness boron-containing film selected from the group consisting of SixByCz, SixByNz, SixByCzNw, BxCy, and BxNy. In some embodiments, a hardmask film includes a germanium-rich GeNx material comprising at least about 60 atomic % of germanium. These hardmasks can be used in a number of back-end and front-end processing schemes in integrated circuit fabrication.

Abstract: Methods and apparatus provide for a conformable polishing head for uniformly polishing a workpiece. The polishing head includes an elastic polishing pad mounted on an elastic membrane that seals a cavity in the polishing head. The cavity is pressurized to expand the membrane and press the polishing pad down on the top surface of the workpiece, such that the polishing pad conforms to the surface and applies a substantially uniform pressure distribution across the workpiece and thereby uniformly removes material across high and low spots on the workpiece.

Abstract: The present invention provides a polishing composition that can be suitably used in polishing of polysilicon, and a polishing method using the polishing composition. The polishing composition contains abrasive grains and an anionic surfactant having a monooxyethylene group or a polyoxyethylene group and has a pH of 9 to 12. If the anionic surfactant contained in the polishing composition has a polyoxyethylene group, the number of repeating oxyethylene units in the polyoxyethylene group is preferably 2 to 8. The anionic surfactant contained in the polishing composition can be an anionic surfactant that has a phosphate group, a carboxy group, or a sulfo group as well as a monooxyethylene group or a polyoxyethylene group. The content of the anionic surfactant in the polishing composition is preferably 20 to 500 ppm.

Abstract: A combination, composition and associated method for chemical mechanical planarization of a tungsten-containing substrate are described herein which afford tunability of tungsten/dielectric selectivity and low selectivity for tungsten removal in relation to dielectric material. Removal rates for both tungsten and dielectric are high and stability of the slurry (e.g., with respect to pH drift over time) is high.

Abstract: In accordance with an embodiment of the present invention, a method of polishing a device includes providing a layer having a non-uniform top surface. The non-uniform top surface includes a plurality of protrusions. The method further includes removing the plurality of protrusions by exposing the layer to a fluid that has gas bubbles and a liquid.

Abstract: A method for forming an integrated circuit is provided. In one embodiment, the method includes forming a stop layer comprising carbon doped silicon nitride on a gate region on a substrate, the gate region having a poly gate and one or more spacers formed adjacent the poly gate, forming a dielectric layer on the stop layer, and removing a portion of the dielectric layer above the gate region using a CMP process, wherein the stop layer is a strain inducing layer having a CMP removal rate that is less than the CMP removal rate of the dielectric layer and equal to or less than the CMP removal rate of the one or more spacers.

Abstract: The embodiments describe systems and methods for combinatorial processing of a substrate. In some embodiments, chemical mechanical polishing (CMP) techniques are combinatorially processed and evaluated. The CMP system is capable of providing a localized planarization surface to at least a region of a substrate being combinatorially processed. In some embodiments, the CMP system comprises a reactor assembly having plurality of reaction chambers, with at least a reaction chamber comprising a rotatable polishing head, slurry and chemical distribution, chemical and water rinse, and slurry and fluid removal. Accordingly, from a single substrate, a variety of materials, process conditions, and process sequences may be evaluated for desired planarization results.

Abstract: According to one embodiment, a planarizing method is proposed. In the planarizing method, a surface to be processed of an object to be processed including a silicon oxide film is planarized in a processing solution by bringing the surface to be processed into contact with or close proximity with the surface of a solid-state plate on which fluorine is adsorbed. The bonding energy between fluorine and the solid-state plate is lower than that between fluorine and silicon.

Abstract: A method of manufacturing a semiconductor structure includes varying local chemical mechanical polishing (CMP) abrading rates of an insulator film by selectively varying a carbon content of the insulator film.

Abstract: A novel polishing pad is described. The polishing pad includes a base plate, a main polishing body, a plurality of metal bottom portions, a positive electrode conductive wire and a negative electrode conductive wire. The main polishing body made from a non-conductive material and disposed on the base plate includes a plurality of cavities thereon. The metal bottom portions are disposed in the cavities with each of the cavities having one of the metal bottom portions therein. The positive electrode conductive wire electrically is connected to a positive electrode of a power supply. The negative electrode conductive wire electrically is connected to a negative electrode of the power supply. The positive electrode conductive wire and the negative electrode conductive wire alternatively pass through the base plate and connect to the metal bottom portions respectively.

Abstract: A semiconductor device manufacturing method, comprising: providing a semiconductor substrate, on which a gate conductor layer as well as a source region and a drain region positioned on both sides of the gate conductor layer are provided, forming an etch stop layer on the semiconductor substrate, forming an LTO layer on the etch stop layer, chemical mechanical polishing the LTO layer, forming an SOG layer on the polished LTO layer, the etch stop layer, LTO layer and SOG layer forming a front metal insulating layer, back etching the SOG layer and etch stop layer of the front metal insulating layer to expose the gate conductor layer, and removing the gate conductor layer.

Abstract: A method for manufacturing a semiconductor device makes it possible to efficiently polish with a polishing tape a peripheral portion of a silicon substrate under polishing conditions particularly suited for a deposited film and for silicon underlying the deposited film. The method includes pressing a first polishing tape against a peripheral portion of a device substrate having a deposited film on a silicon surface while rotating the device substrate at a first rotational speed, thereby removing the deposited film lying in the peripheral portion of the device substrate and exposing the underlying silicon. A second polishing tape is pressed against the exposed silicon lying in the peripheral portion of the device substrate while rotating the device substrate at a second rotational speed, thereby polishing the silicon to a predetermined depth.

Abstract: A smoothing method for semiconductor material and semiconductor wafers produced by the method are disclosed. Semiconductor wafers with reduced atomic steps, as well with reduced scratches and subsurface defects can be produced. Such wafers feature an improved growth surface that can provide for the growth of an epilayer with reduced macroscopic defects and defect densities. A method of smoothing the surface of a wafer according to example embodiments of the invention includes planarizing the surface of a semiconductor wafer, and then oxidizing the wafer to achieve a specified thickness of oxide on the surface of the wafer. The oxide can then be stripped from the surface of the semiconductor wafer.

Abstract: A process for chemical mechanical polishing of a substrate having a polysilicon overburden deposited over silicon nitride is provided using multiple dilutions of a chemical mechanical polishing composition concentrate to polish the substrate, wherein a first dilution of the concentrate used to polish the substrate is tuned to exhibit a first polysilicon removal rate and a first polysilicon to silicon nitride removal rate selectivity; and wherein a second dilution of the concentrate used to polish the substrate is tuned to exhibit a second polysilicon removal rate and a second polysilicon to silicon nitride removal rate selectivity.

Abstract: A process for chemical mechanical polishing of a substrate having a polysilicon overburden deposited over silicon dioxide is provided using multiple dilutions of a chemical mechanical polishing composition concentrate to polish the substrate, wherein a first dilution of the concentrate used to polish the substrate is tuned to exhibit a first polysilicon removal rate and a first polysilicon to silicon dioxide removal rate selectivity; and wherein a second dilution of the concentrate used to polish the substrate is tuned to exhibit a second polysilicon removal rate and a second polysilicon to silicon dioxide removal rate selectivity.

Abstract: A method for chemical mechanical polishing of a substrate is provided, comprising: providing a substrate, wherein the substrate comprises silicon oxide; providing a chemical mechanical polishing composition, comprising, as initial components: water; an abrasive; and a substance according to formula I wherein R1, R2 and R3 are each independently selected from a C1-4 alky group; providing a chemical mechanical polishing pad with a polishing surface; moving the polishing surface relative to the substrate; dispensing the chemical mechanical polishing composition onto the polishing surface; and, abrading at least a portion of the substrate to polish the substrate; wherein the substance according to formula I included in the chemical mechanical polishing composition provides an enhanced silicon oxide removal rate and an improved polishing defectivity performance; and, wherein at least some of the silicon oxide is removed from the substrate.

Abstract: A semiconductor manufacturing apparatus includes at least one inner retaining ring, and an outer retaining ring. The at least one inner retaining ring applies a first pressure to the polishing pad, and retains a substrate on the polishing pad. The outer retaining ring applies a second pressure to the polishing pad, and retains the at least one inner retaining ring on the polishing pad. Control of the first pressure is independent with respect to control of the second pressure.

Abstract: According to one embodiment, a CMP method includes starting a polishing of a silicon oxide film by using a slurry including a silicon oxide abrasive and a polishing stopper film including a silicon nitride film, and stopping the polishing when the polishing stopper is exposed. The slurry includes a first water-soluble polymer with a weight-average molecular weight of 50000 or more and 5000000 or less, and a second water-soluble polymer with a weight-average molecular weight of 1000 or more and 10000 or less.

Abstract: A method for manufacturing semiconductor substrates. The method includes providing a semiconductor wafer, which has an upper surface, a backside surface, and an edge region around a periphery of the semiconductor wafer. In a preferred embodiment, the upper surface is often for the manufacture of the integrated circuit device elements themselves. The method includes subjecting the semiconductor wafer to one or more process steps to form one or more films of materials on the backside surface. The method mounts the semiconductor wafer to expose the backside surface. The method rotates the semiconductor wafer in a circular manner. In a specific embodiment, the method includes supplying an acid solution containing fluorine bearing species, a nitric acid species, a surfactant species, and an organic acid species, on at least the backside surface as the semiconductor wafer rotates.

Abstract: A process to thin semiconductor wafers to less than 50 microns employs a dissolvable photoresist or polyimide or other glue material to hold a thick carrier plate such as a perforated glass to the top surface of a thick processed wafer and to grind or otherwise remove the bulk of the wafer from its rear surface, leaving only the preprocessed top surface, which may include semiconductor device diffusions and electrodes. A thick metal such as copper or a more brittle copper alloy is then conductively secured to the ground back surface and the glue is dissolved and the carrier plate is removed. The wafer is then cleaned and diced into plural devices such as MOSFETs; integrated circuits and the like.

Abstract: A chemical mechanical polishing pad comprising an acrylate polyurethane polishing layer, wherein the polishing layer exhibits a tensile modulus of 65 to 500 MPa; an elongation to break of 50 to 250%; a storage modulus, G?, of 25 to 200 MPa; a Shore D hardness of 25 to 75; and a wet cut rate of 1 to 10 ?m/min.

Abstract: A composition and a method for chemical mechanical polishing. The composition includes a surfactant anion an alkyl alcohol and a diluent. The composition further includes abrasive particles and an oxidizer. The method includes providing the composition on a surface to be polished and polishing the surface by contacting the surface with a polishing pad.