Abstract: Fine patterns are formed by forming an etch-target layer on a substrate; forming support patterns on the etch-target layer; forming first spacer patterns on sidewalls of the support patterns; forming second spacer patterns coming in contact with the first spacer patterns; removing the support patterns; and etching the etch-target layer by using the first spacer patterns and the second spacer patterns as an etch mask.

Abstract: Provided is a method for manufacturing a photovoltaic device which is capable of easily forming a texture having an aspect ratio larger than 0.5. The method for manufacturing a photovoltaic device include the steps of: forming an etching-resistant film on a silicon substrate; forming a plurality of fine holes in the etching-resistant film with an irradiated laser beam which has a focal depth adjusted to 10 ?m or more to expose a surface of the silicon substrate which is a base layer; and etching the exposed surface of the silicon substrate, in which the step of exposing the surface of the silicon substrate includes forming a fine recess at a concentric position to each of the fine holes in the surface of the silicon substrate which lies under the etching-resistant film.

Abstract: A method for cleaning structured surfaces of semiconductor components to remove photoresist and etching residues after the etching of the surface, comprising: a) removal of the photoresist, b) treatment of the surface with an acidic aqueous solution comprising one or more acids and one or more oxidizing agents, c) treatment of the surface with an alkaline aqueous solution and d) washing of the surface with demineralized water, the steps a), b) and c) being effected before step d).

Abstract: A high-amplitude magnetic angle sensor is described along with a process for its manufacture. A thin tantalum nitride hard mask, used to pattern the device, is left in place within the completed structure but, by first converting most of it to tantalum oxide, its effect on current shunting is greatly reduced.

Abstract: There is provided a semiconductor device manufacturing apparatus and a semiconductor device manufacturing method capable of recovering a damage of a low dielectric insulating film exposed to CO2 plasma to obtain the low dielectric insulating film in a good state, thus improving performance and reliability of a semiconductor device. The semiconductor device manufacturing method includes: an etching process for etching a low dielectric insulating film formed on a substrate; a CO2 plasma process for exposing the substrate to CO2 plasma after the etching process; and a UV process for irradiating UV to the low dielectric insulating film after the CO2 plasma process.

Abstract: A method in the fabrication of a semiconductor device simultaneously forms different patterns on the same level of the device. The device has a first area and a second area. A low density mask pattern of at least one relatively wide topographic feature is formed on the second area, a plurality of relatively narrow topographic features is formed on the first area, first spacers are formed on side walls of the narrow topographic features in the first area, the relatively narrow topographic features are removed, and the patterns of the first spacers and the relatively wide topographic feature(s) are simultaneously transcribed in the first and second areas, respectively.

Abstract: The present invention relates, in general, to a method for three-dimensional (3D) microfabrication of complex, high aspect ratio structures with arbitrary surface height profiles in metallic materials, and to devices fabricated in accordance with this process. The method builds upon anisotropic deep etching methods for metallic materials previously developed by the inventors by enabling simplified realization of complex, non-prismatic structural geometries composed of multiple height levels and sloping and/or non-planar surface profiles. The utility of this approach is demonstrated in the fabrication of a sloping electrode structure intended for application in bulk micromachined titanium micromirror devices, however such a method could find use in the fabrication of any number of other microactuator, microsensor, microtransducer, or microstructure devices as well.

Abstract: A method of forming an improved static random access memory (SRAM) interconnect structure is provided. The method includes forming a sidewall spacer around a periphery of a patterned poly-silicon layer formed over a silicon layer of a semiconductor substrate; removing the patterned poly-silicon layer for exposing a portion of a cap layer; etching the exposed portion of the cap layer for revealing a portion of the silicon layer; etching the portion of the silicon layer, in which a portion of said silicon layer connects at least a portion of pull-down device of said SRAM to at least a portion of pull-up device of said SRAM; forming a gate oxide; and forming a gate conductor over the gate oxide. An interconnect structure is also provided.

Abstract: An electronic device including a shielded electronic element, and a method for manufacturing a shielding structure. An oxide film is formed on the surface of a silicon substrate having a [100] face. Part of the oxide film is removed to form a first window region. Silicon substrates are joined together to form an SOI substrate, which includes a buried mask having a second window region. Substrate thinning is then performed, and oxide films are formed on the two surfaces of the SOI substrate so that the first window region has a large area and includes the region above the buried second window region. Then, anisotropic etching is performed to form a cap that includes a step. Wire bonding for shielding is performed on the step.

Abstract: A method for fabricating a saddle type fin transistor includes: preparing a substrate where a device isolation structure is already formed; forming a hard mask pattern over the substrate, the hard mask pattern including a coating layer obtained through a coating method; and performing an etching process using the hard mask pattern as an etch mask to form a saddle type fin. The hard mask pattern may be formed in a stack structure including an amorphous carbon layer and the coating layer.

Abstract: Disclosed herein is a method for forming a semiconductor device that stacks an etched layer and a first hard mask layer on a semiconductor substrate, patterns the first hard mask layer in a high density region and a low density region, using a first exposure mask, forms a first spacer on a sidewall of the first hard mask layer in the high density region, forms a second spacer on a sidewall of the first hard mask layer in the low density region at the same time, etches an end with the first spacer connected thereto using a second exposure mask to thereby form a first spacer pattern, forms a planarized second hard mask layer that exposes the first spacer pattern and the second spacer, removes the first spacer pattern and the second spacer such that the second hard mask layer is left, and etches the etched layer using the second hard mask layer as an mask. This method makes it possible to easily form a micro pattern in the high density region and the low density region.

Abstract: Provided is a method of manufacturing a semiconductor device including at least two processes. Under an atmosphere comprising hydrogen and oxygen, a sacrificial oxide film is formed on a silicon substrate that is provided with at least one nitride region. Then, the sacrificial oxide film and the nitride region are removed from the silicon substrate.

Abstract: Methods of patterning features of semiconductor devices and methods of processing and fabricating semiconductor devices are disclosed. In one embodiment, a method of processing a semiconductor device includes forming first sidewall spacers on a first hard mask, removing the first hard mask, and forming a first material layer over the first sidewall spacers. A second hard mask is formed over the first material layer and the first sidewall spacers. Second sidewall spacers are formed on the second hard mask, and the second hard mask is removed. At least the first sidewall spacers are patterned using the second sidewall spacers as a mask.

Abstract: In an embodiment, a 3-dimensional flash memory device includes: a gate extending in a vertical direction on a semiconductor substrate; a charge storing layer surrounding the gate; a silicon layer surrounding the charge storing layer; a channel region vertically formed in the silicon layer; and source/drain regions vertically formed on both sides of the channel region in the silicon layer. Integration can be improved by storing data in a 3-dimensional manner; a 2-bit operation can be performed by providing transistors on both sides of the gate.

Abstract: There is provided a resist underlayer film forming composition used in a lithography process for producing semiconductor devices. A method of producing a semiconductor device comprising: forming a coating film by applying a resist underlayer film forming composition containing a polymer, a crosslinker and a photoacid generator on a semiconductor substrate; forming an underlayer film by irradiating light to the coating film; and forming a photoresist by applying a photoresist composition on the underlayer film and heating the resultant layer. The polymer polymer is a polymer having a benzene ring or a hetero ring in a main chain or a side chain bonded to the main chain, and the content rate of a benzene ring in the polymer is 30 to 70% by mass. The polymer may be a polymer containing a lactone structure.

Abstract: A semiconductor device includes a device isolation structure formed on a semiconductor substrate to define an active region. A first Si-based epitaxial pattern is formed over the active region corresponding to a bit line contact region and a portion of a gate region at both sides adjacent to the bit line contact region. A second Si-based epitaxial layer is formed over the semiconductor substrate which is stepped up on the first Si-based epitaxial pattern. A stepped gate pattern is formed over the stepped second Si-based epitaxial layer.

Abstract: A semiconductor device including a circuit structure and a protective layer is provided. The circuit structure has multiple contacts. The protective layer is located on the circuit structure and has multiple openings and multiple protrusions, wherein the contacts are exposed by the openings and the protrusions are located on the contacts.

Abstract: A method for patterning a semiconductor device can include forming a conductive layer over a semiconductor substrate; alternatively forming positive photoresists and negative photoresists over the conductive layer, forming a plurality of first conductive lines by selectively removing a portion of the conductive layer using the positive photoresist and the negative photoresist as masks; forming an oxide film over the semiconductor substrate including the first conductive lines and the conductive layer; performing a planarization process over the oxide film using the uppermost surface of the first conductive line as a target; removing the plurality of first conductive lines using the oxide film as a mask; forming a plurality if trenches in the semiconductor substrate and removing a portion of the oxide film to expose the uppermost surface of the conductive layer; and then forming a plurality of second conductive lines by removing the exposed conductive layer using the oxide film as a mask.

Abstract: Apparatus and methods are provided that enable processing of patterned layers on substrates using a detachable mask. Unlike prior art where the mask is formed directly over the substrate, according to aspects of the invention the mask is made independently of the substrate. During use, the mask is positioned in close proximity or in contact with the substrate so as to expose only portions of the substrate to processing, e.g., sputtering or etch. Once the processing is completed, the mask is moved away from the substrate and may be used for another substrate. The substrate may be cycled for a given number of substrates and then be removed for cleaning or disposal.

Abstract: A method of sealing a microelectromechanical system (MEMS) device from ambient conditions is described, wherein the MEMS device is formed on a substrate and a substantially hermetic seal is formed as part of the MEMS device manufacturing process. The method comprises forming a metal seal on the substrate proximate a perimeter of the MEMS device using a method such as photolithography. The metal seal is formed on the substrate while the MEMS device retains a sacrificial layer between conductive members of MEMS elements, and the sacrificial layer is removed after formation of the seal and prior to attachment of a backplane.

Abstract: Disclosed is a method for manufacturing an image sensor. The method includes forming a polysilicon layer on a semiconductor substrate having an active region, forming a sacrificial layer on the polysilicon layer, forming a photoresist pattern on the sacrificial layer, implanting conductive impurities onto the polysilicon layer using the photoresist pattern as an ion implantation mask, removing the photoresist pattern, and removing the sacrificial layer from the polysilicon layer, thereby removing photoresist residues remaining on the sacrificial layer.

Abstract: A method for double patterning lithography includes: (a) forming a first pattern on a first material layer that is formed on a semiconductor substrate, the first pattern having a plurality of first parts extending in a first direction and spaced apart along a second direction transverse to the first direction, and a plurality of first gaps among the first parts; (b) forming a second pattern on the first pattern, the second pattern having a plurality of second parts extending in the second direction and spaced apart along the first direction, and a plurality of second gaps among the second parts, the first and second gaps intersecting each other and cooperatively defining a plurality of uncovering regions where the first and second gaps intersect each other; and (c) etching portions of the first material layer exposed via the uncovering regions.

Abstract: A solid surface is processed while corner portions of a relief structure are protected from deformation. A method of processing a solid surface with a gas cluster ion beam includes a cluster protection layer formation step of forming, on the solid surface, a relief structure having protrusions with a cluster protection layer formed to cover an upper part thereof and recesses without the cluster protection layer; an irradiation step of emitting a gas cluster ion beam onto the solid surface having the relief structure formed in the cluster protection layer formation step; and a removal step of removing the cluster protection layer. A thickness T of the cluster protection layer satisfies T > nY + ( b 2 ? Y 2 ? n - nY 2 ? ( b 4 - 16 ? a 2 ) 1 2 2 ) 1 2 , where n is a dose of the gas cluster ion beam, and Y is an etching efficiency of the cluster protection layer, expressed as an etching volume per cluster (a and b are constants).

Abstract: In an embodiment, a method of forming a lower electrode of a capacitor in a semiconductor memory device includes etching a mold oxide layer to have at a cylindrical structure, resulting in an electrode with increased surface area. The cylindrical structure may have more than one radius. This increased surface area results in an increased capacitance. An excessive etch phenomenon, which occurs because a sacrificial oxide layer is etched at a higher rate than the mold oxide layer, is avoided.

Abstract: Disclosed is a method of forming a pattern. A first organic polymer layer is formed on a substrate on which an underlying layer, and then a second organic polymer layer, which has an opening partially exposing the first organic polymer layer, is formed on the first organic polymer layer. Next, a silicon-containing polymer layer is formed on the second organic polymer layer to cover the opening. The silicon-containing polymer layer is oxidized and simultaneously the second organic polymer layer and the first organic polymer layer are ashed by oxygen plasma to form a pattern having an anisotropy-shape. The underlying layer is etched using the silicon-containing polymer layer and the first organic polymer layer as an etching mask to form a pattern.

Abstract: A method for fabricating a semiconductor device includes: forming an etch stop pattern over a conductive layer, the etch stop pattern having a first opening exposing a top surface of the conductive layer; forming an insulation layer over the etch stop pattern; selectively etching the insulation layer to form a second opening exposing the top surface of the conductive layer; and enlarging the second opening until the etch stop pattern is exposed.

Abstract: A method for forming semi-insulating portions in a semiconductor substrate provides depositing a hardmask film over a semiconductor substructure to a thickness sufficient to prevent charged particles from passing through the hardmask. The hardmask is patterned creating openings through which charged particles pass and enter the substrate during an implantation process. The semi-insulating portions may extend deep into the semiconductor substrate and electrically insulate devices formed on opposed sides of the semi-insulating portions. The charged particles may advantageously be protons and further substrate portions covered by the patterned hardmask film are substantially free of the charged particles.

Abstract: According to one aspect of the invention, there is provided a qsemiconductor device fabrication method having: forming a film on a semiconductor substrate; forming a mask comprising a predetermined pattern on the film; etching one of the film and the semiconductor substrate by using the mask; and performing at least one of the steps of performing a treatment using one of an aqueous solution of at least one of ammonia and amine, the amine being selected from primary amine, secondary amine, tertiary amine, and quaternary amine, a treatment using a liquid chemical containing fluorine and at least one of amine, the amine being selected from primary amine, secondary amine, tertiary amine, and quaternary amine and fluorine, and a treatment using a liquid chemical containing at least ammonia and fluorine and including a pH of not less than 6, particularly, not less than 9.

Abstract: The invention discloses a method of forming a finFET device. A hard mask layer is formed on an active area of a semiconductor substrate. A portion of the hard mask layer is etched to form a recess. A conformal gate defining layer is deposited on the recess and a tilt angle ion implantation process is performed. A part of the gate defining layer is removed to define a fin pattern. The fin pattern is subsequently transferred to the hard mask layer. The patterned hard mask layer having the fin pattern is utilized as an etching mask, and the semiconductor substrate is etched to form a fin structure.

Abstract: A semiconductor substrate is provided in which an alignment mark is formed that can be used for an aligment even after the formation of an impurity diffused layer by the planarization of an epitaxial film. A trench 11 is formed in an alignment region of an N+-type substrate 1. This trench 11 is used to leave voids 3 after the formation of an N?-type layer 2. Then, the voids 3 formed in the N+-type substrate 1 can be used as an alignment mark. Thus, such a semiconductor substrate can be used to provide an alignment in the subsequent step of manufacturing the semiconductor apparatus. Thus, the respective components constituting the semiconductor apparatus can be formed at desired positions accurately.

Abstract: Embodiments relate to a semiconductor device and a method of manufacturing a semiconductor. In embodiments, the method may include a first exposure step of performing an exposure process for forming a first photoresist on a semiconductor substrate at one side of the outside of a trench pattern which will be formed, a first etching step of performing a predetermined dry etching method with respect to the first photoresist, a second exposure step of performing an exposure process for forming a second photoresist at the other side of the outside of the trench pattern, which is a side opposite to the first photoresist, and a second etching step of performing the predetermined dry etching method with respect to the second photoresist.

Abstract: A method for fabricating a semiconductor device includes forming an etch target layer over a substrate that includes a cell region and a peripheral region. A first hard mask layer, a second hard mask layer, and an anti-reflective coating layer are formed over the etch target layer. A photosensitive pattern is formed over the anti-reflective coating layer. The anti-reflective coating layer is etched to have a width smaller than the width of the photosensitive pattern. The second hard mask layer is etched. A main etching and an over-etching are performed on the first hard mask layer. The etch target layer is then etched.

Abstract: A semiconductor device with a WLP structure that enables the improvement of heat resistance. A dam layer which spreads over a PI film and an Si substrate for a chip is formed between the Si substrate and a sealing resin so as to surround the chip on all sides. A material for the dam layer is selected so that good adhesion will be obtained between the dam layer and the Si substrate, between the dam layer and the PI film, and between the dam layer and the sealing resin. As a result, even if a crack appears at a portion on a side of the semiconductor device where the Si substrate and the sealed resin are joined in a heating environment, the crack does not run inside the dam layer. This prevents the peeling of the sealing resin or peeling inside the chip and the performance of the semiconductor device is maintained.

Abstract: A method for removing defects due to edge chips of a semiconductor wafer is disclosed. This method includes forming a molding layer over a semiconductor wafer. The molding layer is patterned to form a plurality of storage node holes, where the plurality of storage node holes include at least one first storage node hole formed on an effective chip area and at least one second storage node hole formed on an edge chip area. First storage nodes and second storage nodes are formed in the first and second storage node holes, respectively. A photoresist pattern is formed on the wafer having the storage nodes. The photoresist pattern is preferably formed to expose the effective chip areas and to cover the edge chip areas. The molding layer is etched, using the photoresist pattern as an etching mask, to expose portions of the first storage nodes.

Abstract: Methods are provided for etching during fabrication of a semiconductor device. The method includes initially etching to partially remove a portion of one or more lithographic-aiding layers overlying an oxide layer while etching a first portion of the oxide layer in accordance with a mask formed by the one or more lithographic-aiding layers, and thereafter additionally etching to remove remaining portions of the one or more lithographic-aiding layers while etching a remaining portion of the oxide layer.

Abstract: It is an object of the present invention to provide a semiconductor device including a wiring having a preferable shape. A manufacturing method includes the steps of forming a first conductive layer connected to an element and a second conductive layer thereover; forming a resist mask over the second conductive layer; processing the second conductive layer by dry etching with the use of the mask; and processing the first conductive layer by wet etching with the mask left, wherein the etching rate of the second conductive layer is higher than that of the first conductive layer in the dry etching, and wherein the etching rate of the second conductive layer is the same as or more than that of the first conductive layer in the wet etching.

Abstract: A semiconductor device includes a first well formed in a predetermined region of a semiconductor substrate, a second well formed in a predetermined region in the first well, and a third well formed in the first well with the third well being spaced apart from the second well at a predetermined distance. A multiple well of the semiconductor substrate, the first well, the second well, the first well, and the third well, which are sequentially disposed, is formed. Accordingly, a breakdown voltage can be increased and a leakage current can be reduced. It is therefore possible to prevent the drop of an erase voltage and to reduce the error of an erase operation.

Abstract: The present invention provides a substrate and a semiconductor light emitting device. Convexes having a curved surface are formed on the substrate. The semiconductor light emitting device comprises a substrate on which convexes having a curved surface are formed and a semiconductor layer on the substrate.

Abstract: The present invention provides a method for fabricating an embedded static random access memory, including providing a semiconductor substrate; defining a logic area and a memory cell area on the semiconductor substrate and defining at least a first conductive device area and at least a second conductive device area in the logic area and the memory cell area respectively; forming a patterned mask on the memory cell area and on the second conductive device area in the logic area and exposing the first conductive device area in the logic area; performing a first conductive ion implantation process on the exposed first conductive device area in the logic area; and removing the patterned mask.

Abstract: A method of manufacturing an exposure mask includes generating or preparing flatness variation data relating to a mask blanks substrate to be processed into an exposure mask, the flatness variation data being data relating to change of flatness of the mask blank substrate caused when the mask blank substrate is chucked by a chuck unit of an exposure apparatus, generating position correction data of a pattern to be drawn on the mask blanks substrate based on the flatness variation data such that a mask pattern of the exposure mask comes to a predetermined position in a state that the exposure mask is chucked by the chuck unit, and drawing a pattern on the mask blanks substrate, the drawing the pattern including drawing the pattern with correcting a drawing position of the pattern and inputting drawing data corresponding to the pattern and the position correction data into a drawing apparatus.

Abstract: A method of creating a sensor that may include applying a first conductive material on a first portion of a substrate to form a reference electrode and depositing a first mask over the substrate, the first mask having an opening that exposes the reference electrode and a second portion of the substrate. The method may also include depositing a second conductive material into the opening in the first mask, the second conductive material being in direct contact with the reference electrode and depositing a second mask over the second conductive material, the second mask having an opening over the second portion of the substrate, the opening exposing a portion of the second conductive material, which forms a working surface to receive a fluid of interest.

Abstract: In one aspect of the present invention, a method of manufacturing a semiconductor device may include forming a first film on an amorphous silicon layer to be patterned, the first film and the amorphous film having a line-and-space ratio of approximately 3:1, sliming down, after processing the first film, a line portion of the pattern from both longitudinal sides of the line portion until the width of the line portion is reduced to approximately one third, reforming a part of the amorphous silicon layer where the first film is not provided such that reformed part has different etching ratio, and removing the first film and the amorphous silicon layer other than reformed part.

Abstract: A method of manufacturing a nonvolatile semiconductor memory device may include forming a pad oxide layer pattern and a mask pattern on a semiconductor substrate, forming a trench within the semiconductor substrate with the mask pattern functioning as an etching mask, sequentially forming a first device isolation layer and a second device isolation layer that may fill the trench, forming an opening by removing the mask pattern to expose an upper surface of the pad oxide layer pattern and a sidewall of the second device isolation layer, and forming a floating gate forming region having a width wider than the opening by simultaneously removing the pad oxide layer pattern and a sidewall portion of the second device isolation layer exposed by the opening.

Abstract: In general, in one aspect, a method includes forming a hard mask on a semiconductor substrate. A first resist layer is patterned on the hard mask as a first plurality of lines separated by a first defined pitch. The hard mask is etched to a portion of formed thickness to create a first plurality of fins in alignment with the first plurality of lines and the first resist layer is removed. A second resist layer is patterned on the hard mask as a second plurality of lines separated by a second defined pitch. The second plurality of lines is patterned between the first plurality of lines. The hard mask is etched to the portion of the formed thickness to create a second plurality of fins in alignment with the second plurality of lines. The first plurality of hard mask fins and the second plurality of hard mask fins are interwoven and have same thickness.

Abstract: In a method of forming patterns of a semiconductor device, first etch mask patterns are formed over a semiconductor substrate. An auxiliary film is formed over the first etch mask patterns to a thickness in which a step corresponding to the first etch mask patterns can be maintained. Second etch mask patterns are formed in spaces defined by the auxiliary film between adjacent first etch mask patterns. First auxiliary film patterns are formed by removing the auxiliary film formed on the first etch mask patterns. Each first auxiliary film pattern has opposite ends projecting upwardly. The first etch mask patterns and the second etch mask patterns are removed. Second auxiliary film patterns are formed by etching between the ends of the first auxiliary film patterns such that the opposite ends of the first auxiliary film patterns are isolated from each other.

Abstract: Different portions of a continuous loop of semiconductor material are electrically isolated from one another. In some embodiments, the end of the loop is electrically isolated from mid-portions of the loop. In some embodiments, loops of semiconductor material, having two legs connected together at their ends, are formed by a pitch multiplication process in which loops of spacers are formed on sidewalls of mandrels. The mandrels are removed and a block of masking material is overlaid on at least one end of the spacer loops. In some embodiments, the blocks of masking material overlay each end of the spacer loops. The pattern defined by the spacers and the blocks are transferred to a layer of semiconductor material. The blocks electrically connect together all the loops. A select gate is formed along each leg of the loops. The blocks serve as sources/drains.

Abstract: A method of fabricating memory devices is provided. First, a charge storage structure including a gate dielectric structure is formed on the substrate in sequence to form a charge trapping layer. Then, a gate conductive layer is formed above the charge storage structure. Afterwards, the gate conductive layer and at least a part of the charge storage structure are patterned. The cross section of the patterned charge storage structure is then become a trapezoid or a trapezoid analogue, which has the shorter side near the gate conductive layer and the longer side near the substrate.

Abstract: A semiconductor device with improved reliability and its manufacturing method is offered. The semiconductor device of this invention includes a pad electrode formed on a semiconductor substrate through a first insulation layer, and a via hole formed in the semiconductor substrate and extending from a back surface of the semiconductor substrate to the pad electrode, wherein the via hole includes a first opening of which a diameter in a portion close to the pad electrode is larger than a diameter in a portion close to the back surface of the semiconductor substrate, and a second opening formed in the first insulation layer and continuing from the first opening, of which a diameter in a portion close to the pad electrode is smaller than a diameter in a portion close to the front surface of the semiconductor substrate.

Abstract: A known method of forming organic semiconductor devices employs the deposition of a conductive polymer onto a substrate to form electrodes or conductive tracks and then to apply an electrical material such as an organic semiconductor on top of these tracks. Although the conductive polymer serves as a highly efficient injector of electrons into the semiconductor, it is not a good conductor. This introduces undesirable inefficient in the supply of current to and from the semiconductor. Worse still the conductivity may deteriorate with time. A solution to this problem has been found by printing the polymer (7) onto a conductive layer (6) carried on a substrate (5). The printed polymer (7) is then used as a resist during a process in which parts of the conductive polymer not protected by the polymer are removed. The resulting device benefits from the good electron injection qualities of the conductive polymer (7) and efficient conduction by virtue of the underlying conductive layer (6).

Abstract: A method for fabricating a pattern in a semiconductor device includes a single polysilicon hard mask by appropriately selecting spacer material in an SPT, thereby decreasing the number of fabrication processes. Furthermore, since the spacers are easily removed, it is possible to prevent the formation of a step between patterns of a cell region and a peripheral region.