Abstract: A method for manufacturing a metal-oxide semiconductor (MOS) transistor includes providing a substrate having at least a gate structure and a shallow trench isolation (STI) formed thereon, performing a first etching process to form recesses in the substrate respectively at two sides of the gate structure, performing a selective epitaxial growth (SEG) process to form epitaxial silicon layers in the recesses respectively, accordingly a seam is formed in between the epitaxial silicon layer and the STI, forming a dielectric layer in the seam, and performing a self-aligned silicide (salicide) process.

Abstract: A method for forming patterns in a semiconductor memory device, wherein first spacers arranged at a first spacing and second spacers arranged at a second spacing are formed on a target layer which is formed on a semiconductor substrate. A mask pattern is formed to cover a portion of the target layer defined by the two adjacent second spacers. At least two first patterns and at least one second pattern is formed by patterning the target layer using the first spacers, the second spacers and the mask pattern as an etch mask. Here, the second pattern is wider than the first pattern.

Abstract: An integrated circuit of a semiconductor device has a line type of pattern that is not prone to serious RC delays. The integrated circuit has a line formed of at least a layer of polycrystalline silicon, a layer of metal having a low sheet resistance, and a layer of a barrier metal interposed between the polycrystalline silicon and the metal having a low sheet resistance, and first spacers disposed on the sides of the line, respectively, and is characterized in that the line has recesses at the sides of the barrier layer and the first spacers fill the recesses. The integrated circuit may constitute a gate line of a semiconductor device. The integrated circuit is formed by forming layers of polycrystalline silicon, metal having a low sheet resistance, and a barrier metal one atop the other, patterning the layers into a line, etching the same to form the recesses, and then forming the first spacers.

Abstract: A method for forming a semiconductor structure having a deep sub-micron or nano scale line-width is disclosed. Structure consisting of multiple photoresist layers is first formed on the substrate, then patterned using adequate exposure energy and development condition so that the bottom photoresist layer is not developed while the first under-cut resist groove is formed on top of the bottom photoresist layer. Anisotropic etching is then performed at a proper angle to the normal of the substrate surface, and a second resist groove is formed by the anisotropic etching. Finally, the metal evaporation process and the lift-off process are carried out and the ?-shaped metal gate with nano scale line-width can be formed.

Abstract: A capacitor is formed by forming a mold insulating layer with a plurality of storage node holes over a semiconductor substrate. A metal storage node is formed on the surface of each of the storage node holes in the mold insulating layer. The mold insulating layer is removed by performing the following steps: loading the semiconductor substrate with the storage node in the chamber for in-situ cleaning, rinsing, and drying processes; removing the mold insulating layer by an etchant in the chamber; then rinsing the semiconductor substrate by introducing deionized water into the chamber while discharging the etchant out of the chamber; finally rinsing the rinsed semiconductor substrate with a mixed solution of the deionized water and organic solvent; drying the finally rinsed semiconductor substrate by IPA vapor in the chamber while discharging the mixed solution of the deionized water and organic solvent out of the chamber.

Abstract: There is provided a photo mask for forming a specific pattern and a specific pattern formed using the photo mask. Unlike in a related method of forming a specific pattern using a photo mask including cell lines and pad lines, the photo mask is manufactured with cell lines and pad lines, the pad lines each including at least one space line. The photoresist layer is exposed and developed using the photomask to form the photoresist pattern. The etched layer is etched in accordance with the photoresist pattern to form the specific pattern. Therefore, it is possible to improve the pattern uniformity of the semiconductor device and thus to improve yield.

Abstract: A method of fabricating a floating gate of a flash memory device is provided. The method includes: forming a tunneling oxide layer on a substrate; forming a conductive thin layer on the tunneling oxide layer; applying a photoresist on the conductive thin layer; defining a floating gate region by patterning the photoresist; forming polymer sidewalls on the sides of the patterned photoresist; and selectively removing the conductive thin layer using the photoresist and the polymer sidewalls as a mask to form a floating gate.

Abstract: A semiconductor structure includes a plurality of conductive lines formed within an interlevel dielectric (ILD) layer and a non-planar cap layer formed over the ILD layer and the conductive lines, wherein the cap layer is raised with respect to the conductive lines at locations between the conductive lines.

Abstract: Disclosed are radiation-resistant zone plates for use in laser-produced plasma (LPP) devices, and methods of manufacturing such zone plates. In one aspect, a method of manufacturing a zone plate provides for forming a masking layer over a supporting membrane, and creating openings through the masking layer in a diffractive grating pattern. Such a method also provides depositing radiation absorbent material in the openings in the masking layer and on the supporting membrane, and then stripping the remaining portions of the masking layer. Then, portions of the supporting membrane not covered by the absorbent material are removed, wherein the remaining portions of the supporting membrane covered by the absorbent material form separate grates. Also in such methods, cross-members are coupled to the grates for holding positions of the grates with respect to each other.

Abstract: Methods and apparatus are provided for magnetoresistive memories employing magnetic tunnel junction (MTJ). The apparatus comprises a MTJ (61, 231), first (60, 220) and second (66, 236) electrodes coupled, respectively, to first (62, 232) and second (64, 234) magnetic layers of the MTJ (61, 231), first (54, 204) and second (92, 260) write conductors magnetically coupled to the MTJ (61, 231) and spaced apart from the first (60, 220) and second (66, 236) electrodes, and at least one etch-stop layer (82, 216) located between the first write conductor (54, 204) and the first electrode (60, 220), having an etch rate in a reagent for etching the MTJ (61, 231) and/or the first electrode (60, 220) that is at most 25% of the etch rate of the MTJ (61, 231) and/or first conductor (60, 220) to the same reagent, so as to allow portions of the MTJ (61, 231) and first electrode (60, 220) to be removed without affecting the underlying first write conductor (54, 204).

Abstract: Methods of manufacturing a semiconductor device including a high-voltage device region and a low-voltage device region are provided. An illustrated method includes forming, on a substrate, a gate pattern for a high-voltage device and a low-voltage device; implanting ions into opposite sides of the gate pattern, to form a lightly doped drain structure while implanting ions into a portion of the high-voltage device region under the same conditions as the low-voltage device region to form an electrostatic discharge protecting device region; forming a spacer at the side surface of the gate pattern; forming a source region and a drain source at field regions disposed at the opposite sides of the gate pattern, respectively; and forming a metal layer on the front surface of the substrate including the gate pattern.

Abstract: A method for fabrication of single crystal silicon micromechanical resonators using a two-wafer process, including either a Silicon-on-insulator (SOI) or insulating base and resonator wafers, wherein resonator anchors, a capacitive air gap, isolation trenches, and alignment marks are micromachined in an active layer of the base wafer; the active layer of the resonator wafer is bonded directly to the active layer of the base wafer; the handle and dielectric layers of the resonator wafer are removed; viewing windows are opened in the active layer of the resonator wafer; masking the single crystal silicon semiconductor material active layer of the resonator wafer with photoresist material; a single crystal silicon resonator is machined in the active layer of the resonator wafer using silicon dry etch micromachining technology; and the photoresist material is subsequently dry stripped.

Abstract: Variations in the pitch of features formed using pitch multiplication are minimized by separately forming at least two sets of spacers. Mandrels are formed and the positions of their sidewalls are measured. A first set of spacers is formed on the sidewalls. The critical dimension of the spacers is selected based upon the sidewall positions, so that the spacers are centered at desired positions. The mandrels are removed and the spacers are used as mandrels for a subsequent spacer formation. A second material is then deposited on the first set of spacers, with the critical dimensions of the second set of spacers chosen so that these spacers are also centered at their desired positions. The first set of spacers is removed and the second set is used as a mask for etching a substrate. By selecting the critical dimensions of spacers based partly on the measured position of mandrels, the pitch of the spacers can be finely controlled.

Abstract: A semiconductor device comprises a semiconductor layer including a plurality of paralleled linear straight sections extending in a first direction. The layer also includes a plurality of connecting sections each having a width in the first direction sufficient to form a wire-connectable contact therein and arranged to connect between adjacent ones of the straight sections in a second direction. The connecting sections have respective ends formed aligned with a first straight line parallel to the second direction.

Abstract: A method for preparing a bottle-shaped deep trench first forms a first mask with at least one opening on a substrate including a first epitaxy layer, an insulation layer on the first epitaxy layer and a second epitaxy layer on the insulation layer. A first etching process is performed to remove a portion of the substrate under the opening down to the interior of the insulation layer to form a trench, and a thermal treating process is then performed to form a second mask on the inner sidewall of the trench. Subsequently, a second etching process is performed to remove a portion of the substrate under the opening down to the interior of the first epitaxy layer to form a deep trench, and a third etching process is performed to remove a portion of the first epitaxy layer so as to form the bottle-shaped deep trench with an enlarged surface.

Abstract: Processes for forming isolation structures for semiconductor devices include forming a submerged floor isolation region and a filed trench which together enclose an isolated pocket of the substrate. One process aligns the trench to the floor isolation region. In another process a second, narrower trench is formed in the isolated pocket and filled with a dielectric material while the dielectric material is deposited so as to line the walls and floor of the first trench. The substrate does not contain an epitaxial layer, thereby overcoming the many problems associated with fabricating the same.

Abstract: A method of manufacturing a through conductor that penetrates from an upper surface of a silicon substrate to its lower surface. The through conductor is manufactured in steps which provide a first conductor which extends in the direction of thickness of the silicon substrate from the upper surface of the silicon substrate, and a second conductor which has a size in the direction orthogonal to the thickness direction is smaller than that of the first conductor and which penetrates the silicon substrate from a bottom face of the first conductor to the lower surface of the silicon substrate.

Abstract: According to the present invention, there is a provided a semiconductor device fabrication method having, forming a mask material in a surface portion of a semiconductor substrate, and forming a step having a projection by using the mask material; forming a dielectric film on the semiconductor substrate so as to fill the step and planarize an entire surface; annealing the dielectric film; etching back the dielectric film such that a surface of the dielectric film is positioned between upper and lower surfaces of the mask material; and removing the mask material to expose a surface of the projection of the semiconductor substrate.

Abstract: A partially manufactured semiconductor device includes a semiconductor substrate. The device includes a first oxide layer formed on the substrate, with a mask placed over the oxide-covered substrate, a plurality of first trenches and at least one second trench etched through the oxide layer forming mesas. The at least one second trench is deeper and wider than each of the first trenches. The device includes a second oxide layer that is disposed over an area of mesas and the plurality of first trenches. The device includes a layer of masking material that is deposited over a an area of an edge termination region adjacent to an active region. The area of mesas and first trenches not covered by the masking layer is etched to remove the oxidant seal. The device includes an overhang area that is formed by a wet process etch.

Abstract: Generally disclosed is a method of a device comprising forming a polysilicon stack including a first and a second polysilicon layer with an intervening etch stop layer, wherein the first polysilicon layer height is at least one third a height of the polysilicon stack height, removing the second polysilicon layer and the etch stop layer, and reacting the first polysilicon layer with a metal to fully silicide the first polysilicon layer. Fully silicided (FUSI) gates can hence be formed with uniform gate height. The thin first polysilicon layer allows for siliciding with a lower thermal budge and with better uniformity of the silicide concentration throughout the layer.

Abstract: A method for manufacturing a probe card is provided. A first inactive layer, a first patterned photoresist layer and a first metal layer are sequentially formed on a substrate. The first metal layer has first through holes exposing a portion of the first patterned photoresist layer. A second inactive layer and a second patterned photoresist layer are sequentially formed thereon. The second patterned photoresist layer has second through holes exposing the first through holes. Pins are formed inside the first and the second through holes. A second metal layer is formed on the second patterned photoresist layer. One end of each pin is connected to the second metal layer. The pins and the second metal layer are taken out. A circuit carrier having third through holes is provided. The pins are inserted into the third through holes. The second metal layer is patterned to form pinheads.

Abstract: A method for fabricating a semiconductor device includes forming an etch target layer over a substrate including a cell region and a peripheral region, forming a first mask pattern having a first portion and a second portion over the etch target layer in the cell region and forming a second mask pattern having a first portion and a second portion over the etch target layer in the peripheral region, forming a photoresist pattern over the cell region, trimming the first portion of the second mask pattern, removing the photoresist pattern and the second portion of the first mask pattern and the second portion of the second mask pattern, and etching the etch target layer to form a pattern in the cell region and a pattern in the peripheral region.

Abstract: A method of a CMOS image sensor is disclosed. A method of manufacturing a CMOS image sensor includes forming an epi layer formed over a semiconductor substrate including a pixel region and a peripheral region. At least one oxide film may be formed over the epi layer, including the peripheral region and an upper pad formed therein. A nitride film may be formed over the oxide film. A primary array etching process may be performed with respect to the nitride film using a first photoresist pattern for opening a main pixel region in the pixel region. A secondary array etching process may be performed with respect to the nitride film and the oxide film using a second photoresist pattern for opening the upper pad. The oxide film of the pixel region may be obliquely removed to a predetermined depth. A plurality of color filters and a plurality of micro lenses may be formed over the pixel region after the secondary array etching process.

Abstract: A method of forming a hardmask pattern over a semiconductor device semiconductor device includes forming a first hardmask layer over a semiconductor substrate. First and second structures are formed over the first hardmask layer, the first and second structures formed of the same material, the first and second structures defining a first pitch. First and second overcoats are formed over the first and second structures, respectively, the first and second overcoats being conformal to the first and second structures, respectively. The first and second overcoats define a space therebetween and are configured to expose an underlying layer. A filling layer is formed to fill the space defined between the first and second overcoats. The first and second overcoats are removed to provide the first structure, the second structure, and a third structure provided between the first and second structures, the first and third structures defining a second pitch, the second and third structures defining a third pitch.

Abstract: In one embodiment, a self-aligned contact (SAC) trench structure is formed through a dielectric layer to expose an active region of a MOS transistor. The SAC trench structure not only exposes the active region for electrical connection but also removes portions of a stress liner over the active region. This leaves the stress liner mostly on the sidewall and top of the gate of the MOS transistor. Removing portions of the stress liner over the active region substantially removes the lateral component of the strain imparted by the stress liner on the substrate, allowing for improved drive current without substantially degrading a complementary MOS transistor.

Abstract: A semiconductor substrate (100) is acquired by forming a mask with a target thickness on a major surface of a single-crystal silicon substrate, implanting oxygen ions to the major surface at a high temperature, forming a surface protection layer for blocking oxygen on the major surface, performing annealing, and then stripping off the mask and the surface protection layer. A silicon dioxide layer (102) has a first tip surface (102a) corresponding to an area where the mask has not existed and having a relatively long distance from the major surface (100a), and a second top surface (102b) corresponding to an area where the mask has existed and having a relatively short distance from the major surface (100a). As this major surface (100a) is polished by a predetermined quantity, a semiconductor substrate is provided in which only a part of a single-crystal silicon substrate is a SOI substrate.

Abstract: A semiconductor device having small electrical contacts to impurity doped regions and a method for fabrication of such a device are provided. In accordance with one embodiment of the invention the semiconductor device comprises a semiconductor substrate having a doped region formed therein. The doped region has a nucleating layer comprising nickel on its surface, and a nanowire structure comprising silicon and carbon electrically contacts the nucleating layer.

Abstract: The invention relates to a method for the fabrication of a membrane oriented in a (111) plane of a (100) silicon wafer. To this end the method comprises the following steps: applying a mask to both sides of the wafer, wherein portions of the sides are covered by the mask; and the at least partial removal by etching away silicon material from the portions of the two sides of the wafer that are not covered. This method is characterised in that the etching step substantially removes the silicon material forming recesses in the two surfaces of the wafer, such that the walls of the recesses are formed by (111) planes, and in that not covered portions at both sides of the wafer are aligned in relation to one another such that a (111) plane is formed and the distance d between said two planes is less than the thickness of the silicon wafer, so as to form a membrane in the (111) plane having a thickness d.

Abstract: A single crystal silicon etching method includes providing single crystal silicon substrate having at least one trench therein. The substrate is exposed to an anisotropic etchant which undercuts the silicon. By controlling the length of the etch, single crystal silicon islands or smooth vertical walls in the single crystal silicon may be created.

Abstract: A mask includes a silicon member, and a portion defining an opening penetrating the silicon member; and the corner of the opening is rounded.

Abstract: The present invention is a multi-layer shadow mask and method of use thereof. The multi-layer shadow mask includes a sacrificial mask bonded to a deposition mask. The sacrificial mask provides protection against an accumulation of evaporant on the deposition mask which would cause the deposition mask to deform.

Abstract: A method for fabricating a semiconductor device includes forming a layer to be etched, forming a hard mask pattern over the layer, and etching the layer to form a pattern. The hard mask pattern has an atomic percentage of a silicon-hydrogen bond varying with a thickness of the hard mask pattern.

Abstract: The invention provides a semiconductor device having less defectives in shape of a patterned wiring layer even in a case of having a wiring layer for which patterning is required to be carried out over a longer period of etching time, and a method for producing the same. By carrying out dry etching using a fluorine-based gas with a photoresist 17a used as a mask, an auxiliary mask 15a is formed by patterning the insulation membrane. Next, by carrying out dry etching using a chlorine-based gas using the auxiliary mask 15a and the remaining photoresist 17a as masks, wiring 13a is formed by patterning the wiring layer 13. In the second etching, the auxiliary mask 15a is scarcely etched. Therefore, if the thickness of the photoresist 17a is equivalent to that in the prior arts, it is possible to pattern a thicker wiring layer 13 than in the prior arts.

Abstract: A method of forming a MOS transistor in an upper surface of a semiconductor substrate. A gate oxide layer covers the upper surface of the substrate. A gate stack including one or more thin film layers covers the gate oxide layer. A gate electrode pattern is partially etched into the gate stack, the partial etching step being completed before any of the gate oxide layer is exposed. Sidewall spacers are formed on edge surfaces of the partially formed gate electrode. Source and drain regions are created by ion implantation using the partially etched gate electrode and the sidewall spacers as a mask. The sidewall spacers are removed and lightly doped drain regions are formed by ion implantation using the partially etched gate electrode as a mask.

Abstract: A partially manufactured semiconductor device includes a semiconductor substrate. The device includes a first oxide layer formed on the substrate, with a mask placed over the oxide-covered substrate, a plurality of first trenches and at least one second trench etched through the oxide layer forming mesas. The at least one second trench is deeper and wider than each of the first trenches. The device includes a second oxide layer that is disposed over an area of mesas and the plurality of first trenches. The device includes a layer of masking material that is deposited over a an area of an edge termination region adjacent to an active region. The area of mesas and first trenches not covered by the masking layer is etched to remove the oxidant seal. The device includes an overhang area that is formed by a wet process etch.