Making Grooves, E.g., Cutting (epo) Patents (Class 257/E21.238)
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Patent number: 8357567Abstract: It is an object of the present invention to provide a manufacturing method of a semiconductor device where a semiconductor element is prevented from being damaged and throughput speed thereof is improved, even in a case of thinning or removing a supporting substrate after forming the semiconductor element over the supporting substrate.Type: GrantFiled: March 22, 2011Date of Patent: January 22, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Ryosuke Watanabe
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Patent number: 8343805Abstract: A method and structure for uncovering captive devices in a bonded wafer assembly comprising a top wafer and a bottom wafer. One embodiment method includes forming a plurality of cuts in the top wafer and removing a segment of the top wafer defined by the plurality of cuts. The bottom wafer remains unsingulated after the removal of the segment.Type: GrantFiled: September 4, 2012Date of Patent: January 1, 2013Assignee: Texas Instruments IncorporatedInventors: Clayton Lee Stevenson, Jason C. Green, Daryl Ross Koehl, Buu Quoc Diep
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Patent number: 8334173Abstract: A method for manufacturing a semiconductor apparatus includes: forming a protrusion made of a conductor on each of the electrodes provided on a semiconductor wafer top face side of a plurality of semiconductor devices formed in a semiconductor wafer; making a trench in the top face between the plurality of semiconductor devices; filling an insulator into a gap between the protrusions and into the trench to form a sealing member; grinding a bottom face of the semiconductor wafer opposing the top face until the sealing member being exposed to divide the semiconductor wafer into each of the semiconductor devices; forming a first lead made of a conductor on each of the protrusions, the first lead forming a portion of a first external electrode; forming a conductive material layer directly to form a second lead on the bottom face of the plurality of semiconductor devices, the second lead forming the second external electrode; and cutting the sealing member between the plurality of semiconductor devices to separateType: GrantFiled: January 27, 2010Date of Patent: December 18, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Takao Nogi, Tomoyuki Kitani, Akira Tojo, Kentaro Suga
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Patent number: 8324081Abstract: An electrically insulative conformal coating is applied at least to the active (front) side and one or more sidewalls of the die during wafer processing. Also, a die has an electrically insulative conformal coating applied to at least the active (front) side and sidewalls. Also, assemblies include a stack of such die, electrically interconnected die-to-die; and assemblies include such a die or a stack of such die, electrically interconnected to underlying circuitry (for example in a substrate or a circuit board).Type: GrantFiled: March 4, 2011Date of Patent: December 4, 2012Inventors: Simon J. S. McElrea, Terrence Caskey, Scott McGrath, DeAnn Eileen Melcher, Reynaldo Co, Lawrence Douglas Andrews, Jr., Weiping Pan, Grant Villavicencio, Yong Du, Scott Jay Crane, Zongrong Liu
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Publication number: 20120302041Abstract: In a pressure-sensitive adhesive composition or a pressure-sensitive adhesive sheet containing an energy ray-curable polymer, problems associated with the volatilization of a low molecular weight compound contained in the composition are overcome. An energy ray-curable polymer characterized by comprising a radical generating group, which is capable of initiating a polymerization reaction upon excitation with an energy ray, and an energy ray-polymerizable group bonded together in the main or side chain.Type: ApplicationFiled: August 9, 2012Publication date: November 29, 2012Applicant: LINTEC CorporationInventors: Jun Maeda, Keiko Tanaka
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Patent number: 8309433Abstract: A method of manufacturing an optical sensor includes the steps of providing a semiconductor wafer having a plurality of pixel areas; forming a grid-like rib enclosing each pixel area on the semiconductor wafer, the grid-like rib having a predetermined width and being formed from a fixing member; providing a light-transmissive substrate having a gap portion on a main surface thereof, the gap portion having at least one of a groove having a width smaller than the grid-like rib and a plurality of through-holes; fixing the semiconductor wafer and the light-transmissive substrate such that the grid-like rib and the gap portion face each other; and cutting the fixed semiconductor wafer and light-transmissive substrate into pieces such that each piece includes one pixel area.Type: GrantFiled: August 16, 2011Date of Patent: November 13, 2012Assignee: Canon Kabushiki KaishaInventors: Yasuhiro Matsuki, Takanori Suzuki, Koji Tsuduki, Shin Hasegawa, Tadashi Kosaka, Akiya Nakayama
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Patent number: 8309435Abstract: Crack stops for semiconductor devices, semiconductor devices, and methods of manufacturing semiconductor devices are disclosed. In one embodiment, a barrier structure for a semiconductor device includes a plurality of substantially V-shaped regions. Each of the plurality of substantially V-shaped regions is disposed adjacent another of the plurality of substantially V-shaped regions.Type: GrantFiled: June 14, 2011Date of Patent: November 13, 2012Assignee: Infineon Technologies AGInventors: Erdem Kaltalioglu, Michael Beck
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Patent number: 8304920Abstract: In a pressure-sensitive adhesive composition or a pressure-sensitive adhesive sheet containing an energy ray-curable polymer, problems associated with the volatilization of a low molecular weight compound contained in the composition are overcome. An energy ray-curable polymer characterized by comprising a radical generating group, which is capable of initiating a polymerization reaction upon excitation with an energy ray, and an energy ray-polymerizable group bonded together in the main or side chain.Type: GrantFiled: March 12, 2009Date of Patent: November 6, 2012Assignee: LINTEC CorporationInventors: Jun Maeda, Keiko Tanaka
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Patent number: 8298862Abstract: A layered chip package includes a main body and wiring. The main body includes a plurality of layer portions stacked. The wiring is disposed on at least one side surface of the main body. In the method of manufacturing the layered chip package, first, a plurality of substructures each of which includes an array of a plurality of preliminary layer portions are used to fabricate a layered substructure that includes a plurality of pre-separation main bodies arranged in rows. Next, the layered substructure is cut into a plurality of blocks each of which includes a row of a plurality of pre-separation main bodies, and the wiring is formed on the plurality of pre-separation main bodies included in each block simultaneously. The plurality of pre-separation main bodies are then separated from each other. Each of the plurality of blocks includes a row of three, four, or five pre-separation main bodies.Type: GrantFiled: February 4, 2010Date of Patent: October 30, 2012Assignees: Headway Technologies, Inc., SAE Magnetics (H.K.) Ltd.Inventors: Yoshitaka Sasaki, Hiroyuki Ito, Atsushi Iijima
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Patent number: 8298916Abstract: The invention relates to a process for fabricating a multilayer structure comprising: bonding a first wafer onto a second wafer, at least the first wafer having a chamfered edge; and thinning the first wafer so as to form in a transferred layer, the thinning comprising a grinding step and a chemical etching step. After the grinding step and before the chemical etching step, a trimming step of the edge of the first wafer is carried out using a grinding wheel, the working surface of which comprises grit particles having an average size of less than or equal to 800-mesh or greater than or equal to 18 microns, the trimming step being carried out to a defined depth in the first wafer so as to leave a thickness of the first wafer of less than or equal to 35 ?m in the trimmed region.Type: GrantFiled: March 8, 2011Date of Patent: October 30, 2012Assignee: SoitecInventors: Alexandre Vaufredaz, Sebastien Molinari
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Patent number: 8293584Abstract: An integrated circuit package system is provided including forming a wafer having a back side and an active side, forming a recess in the wafer from the back side, forming a cover in the recess, and singulating the wafer at the recess filled with the cover.Type: GrantFiled: August 4, 2006Date of Patent: October 23, 2012Assignee: STATS ChipPAC Ltd.Inventors: Dennis Guillermo, Sheila Rima C. Magno, Ma. Shirley Asoy, Pandi Chelvam Marimuthu
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Patent number: 8268656Abstract: An optical device wafer processing method including a protective plate attaching step of attaching a transparent protective plate through a double-sided adhesive tape to the front side of a sapphire substrate constituting an optical device wafer, the double-sided adhesive tape being composed of a sheet capable of blocking ultraviolet radiation and adhesive layers formed on both sides of the sheet, wherein the adhesive force of each adhesive layer can be reduced by applying ultraviolet radiation; a sapphire substrate grinding step of grinding the back side of the sapphire substrate; a modified layer forming step of applying a laser beam to the sapphire substrate from the back side thereof to thereby form a modified layer in the sapphire substrate along each street; a protective plate removing step of removing the protective plate in the condition where the double-sided adhesive tape is left on the sapphire substrate; and a wafer dividing step of breaking the sapphire substrate along each street where the modifType: GrantFiled: April 13, 2010Date of Patent: September 18, 2012Assignee: Disco CorporationInventor: Keiichi Kajiyama
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Patent number: 8257985Abstract: A method and structure for uncovering captive devices in a bonded wafer assembly comprising a top wafer and a bottom wafer. One embodiment method includes forming a plurality of cuts in the top wafer and removing a segment of the top wafer defined by the plurality of cuts. The bottom wafer remains unsingulated after the removal of the segment.Type: GrantFiled: September 25, 2008Date of Patent: September 4, 2012Assignee: Texas Instruments IncorporatedInventors: Clayton Lee Stevenson, Jason C. Green, Daryl Ross Koehl, Buu Quoc Diep
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Patent number: 8241960Abstract: Semiconductor device manufacturing equipment in which in the process of dividing a substrate into individual semiconductor devices using a dicing blade, the possibility of an odd piece flying off a supporting member is prevented. A supporting member supports a substrate for semiconductor devices on one surface thereof. A dicing blade dices the substrate supported by the supporting member along dicing lines provided on the substrate to divide the substrate into a plurality of semiconductor devices. In a plan view, the edge of the supporting member's surface supporting the substrate overlaps a semiconductor device located at an outermost position of the substrate and lies inside a dicing line at an outermost position of the substrate.Type: GrantFiled: December 3, 2010Date of Patent: August 14, 2012Assignee: Renesas Electronics CorporationInventor: Nobuo Yamashita
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Patent number: 8227277Abstract: A method of fabricating a group-III nitride semiconductor laser device includes: preparing a substrate of a hexagonal group-III nitride semiconductor, where the substrate has a semipolar primary surface; forming a substrate product having a laser structure, an anode electrode and a cathode electrode, where the laser structure includes the substrate and a semiconductor region, and where the semiconductor region is formed on the semipolar primary surface; scribing a first surface of the substrate product in part in a direction of the a-axis of the hexagonal group-III nitride semiconductor; and carrying out breakup of the substrate product by press against a second surface of the substrate product, to form another substrate product and a laser bar.Type: GrantFiled: October 20, 2011Date of Patent: July 24, 2012Assignee: Sumitomo Electric Industries, Ltd.Inventors: Yusuke Yoshizumi, Yohei Enya, Takashi Kyono, Masahiro Adachi, Katsushi Akita, Masaki Ueno, Takamichi Sumitomo, Shinji Tokuyama, Koji Katayama, Takao Nakamura, Takatoshi Ikegami
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Patent number: 8227287Abstract: Provided herein are methods and systems for scribing solar cell structures to create isolated solar cells. According to various embodiments, the methods involve scanning an excimer laser beam along a scribe line of a solar cell structure to ablate electrically active layers of the structure. A photomask having variable transmittance is disposed between the beam source and the solar cell structure. The transmittance is calibrated to produce variable fluence levels such that a stepped scribed profile is obtained. In certain embodiments, a front contact/absorber/back contact stack is removed along a portion of the scribe line, while a front contact/absorber stack is simultaneously removed along a parallel portion, with the back contact layer unremoved. In this manner, the scribe electrically isolates solar cells on either side of the scribe line, while providing a contact point to the back contact layer of one of the solar cells for subsequent cell-cell interconnection.Type: GrantFiled: October 14, 2010Date of Patent: July 24, 2012Assignee: MiasoleInventor: Osman Ghandour
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Patent number: 8222101Abstract: A MOS transistor suppressing a short channel effect includes a substrate, a first diffusion region and a second diffusion region separated from each other by a channel region in an upper portion of the substrate, a gate insulating layer including a first gate insulating layer disposed on a surface of the substrate in the channel region and a second gate insulating layer having a specified depth from the surface of the substrate to be disposed between the first diffusion region and the channel region, and a gate electrode disposed on the first gate insulating layer.Type: GrantFiled: June 28, 2007Date of Patent: July 17, 2012Assignee: Hynix Semiconductor Inc.Inventor: Kyoung-Bong Rouh
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Patent number: 8217499Abstract: A structure for reducing partially etched materials is described. The structure includes a layout of an intersection area between two trenches. First, a large intersection area having a trapezoidal corner may be replaced with an orthogonal intersection between two trenches. The layout reduces the intersection area as well as the possibility of having partially etched materials left at the intersection area. The structure also includes an alternative way to fill the intersection area with either an un-etched small trapezoidal area or multiple un-etched square areas, so that the opening area at the intersection point is reduced and the possibility of having partially etched materials is reduced too.Type: GrantFiled: November 23, 2010Date of Patent: July 10, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsung-Yuan Yu, Hsien-Wei Chen, Chung-Ying Yang
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Patent number: 8211781Abstract: A manufacturing method for semiconductor devices having a metal support is provided. The method in one aspect includes growing a semiconductor film on a growth substrate; forming a metal support on a surface of said semiconductor film opposite to the growth substrate; thereafter removing said growth substrate from said semiconductor film; forming a street groove reaching said metal support in the said semiconductor film; radiating a first laser beam onto said metal support to form a first dividing groove having a substantially flat bottom in said metal support; and radiating a second laser beam onto said metal support to form a second dividing groove that penetrates through a portion of said metal support that remains where the first dividing groove is formed.Type: GrantFiled: November 10, 2009Date of Patent: July 3, 2012Assignee: Stanley Electric Co., Ltd.Inventors: Tatsuma Saito, Shinichi Tanaka, Yusuke Yokobayashi
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Patent number: 8212345Abstract: A backgrinding machine 10 of a semiconductor wafer W includes: a table 13 set on the working plane of a mount 11; a multiple number of holding jigs 20 arranged via check tables 15 on table 13; a grinding machine 30 for performing a grinding process of the rear side of semiconductor wafer W held by holding jig 20; and a washing device 40 for ground semiconductor wafers W. Each holding jig 20 is constructed of a concave 22 depressed on the surface of a base plate 21, a multiple number of supporting projections 23 projectively arrayed on the bottom surface of concave 22, a deformable contact film 24, covering the concave 22, being supported by the multiple supporting projections 23, for detachably holding semiconductor wafer W in close contact with it; and an exhaust path 25 for conducting air from the concave 22 covered by contact film 24 to the outside.Type: GrantFiled: November 12, 2010Date of Patent: July 3, 2012Assignees: Shin-Etsu Polymer Co., Ltd., Lintec CorporationInventors: Kiyofumi Tanaka, Satoshi Odashima, Noriyoshi Hosono, Hironobu Fujimoto, Takeshi Segawa
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Patent number: 8207018Abstract: A semiconductor package is disclosed. One embodiment provides a semiconductor package singulated from a wafer includes a chip defining an active surface, a back side opposite the active surface, and peripheral sides extending between the active surface and the back side; a contact pad disposed on the active surface; and a metallization layer extending from the contact pad onto a portion of the peripheral sides of the chip.Type: GrantFiled: October 13, 2010Date of Patent: June 26, 2012Assignee: Infineon Technologies AGInventors: Horst Theuss, Adolf Koller
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Publication number: 20120153294Abstract: A semiconductor structure is bonded directly to a diamond substrate by Van der Waal forces. The diamond substrate is formed by polishing a surface of diamond to a first degree of smoothness; forming a material, such as diamond, BeO, GaN, MgO, or SiO2 or other oxides, over the polished surface to provide an intermediate structure; and re-polishing the material formed on the intermediate structure to a second degree of smoothness smoother than the first degree of smoothness. The diamond is bonded to the semiconductor structure, such as GaN, by providing a structure having bottom surfaces of a semiconductor on an underlying material; forming grooves through the semiconductor and into the underlying material; separating semiconductor along the grooves into a plurality of separate semiconductor structures; removing the separated semiconductor structures from the underlying material; and contacting the bottom surface of at least one of the separated semiconductor structures to the diamond substrate.Type: ApplicationFiled: December 17, 2010Publication date: June 21, 2012Applicant: RAYTHEON COMPANYInventors: Ralph Korenstein, Mary K. Herndon, Chae Deok Lee
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Patent number: 8198175Abstract: A processing method for a package substrate having a base substrate partitioned by a plurality of crossing division lines to form a plurality of chip forming areas where a plurality of semiconductor chips are respectively formed and molded with resin. The package substrate has a resin surface and an electrode surface opposite to the resin surface. The processing method includes a warp correcting step of cutting the package substrate from the resin surface or the electrode surface along the division lines by using a cutting blade to form a cut groove, thereby correcting a warp of the package substrate, and a grinding step of grinding the resin surface of the package substrate in the condition where the electrode surface of the package substrate is held on a holding table after performing the warp correcting step, thereby reducing the thickness of the package substrate to a predetermined thickness.Type: GrantFiled: February 8, 2011Date of Patent: June 12, 2012Assignee: Disco CorporationInventors: Kazuma Sekiya, Koichi Kondo
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Patent number: 8193016Abstract: A semiconductor laser device includes a substrate and a semiconductor layer formed on a surface of the substrate and having a waveguide extending in a first direction parallel to the surface, wherein the waveguide is formed on a region approaching a first side from a center of the semiconductor laser device in a second direction parallel to the surface and intersecting with the first direction, a first region separated from the waveguide on a side opposite to the first side of the waveguide and extending parallel to the first direction and a first recess portion separated from the waveguide on an extension of a facet of the waveguide, intersecting with the first region and extending in the second direction are formed on an upper surface of the semiconductor laser device, and a thickness of the semiconductor layer on the first region is smaller than a thickness of the semiconductor layer on a region other than the first region.Type: GrantFiled: January 6, 2011Date of Patent: June 5, 2012Assignee: Sanyo Electric Co., Ltd.Inventors: Ryoji Hiroyama, Daijiro Inoue, Yasuyuki Bessho, Masayuki Hata
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Patent number: 8178423Abstract: A laser beam machining method wherein machining areas in which to form machined grooves and machining start point areas in which to form shallow grooves shallower than the machined grooves are alternately set in each of streets formed on a wafer, and the machined grooves and the shallow grooves are continuously formed by scanning an irradiation point of a laser beam along each of the streets.Type: GrantFiled: September 1, 2009Date of Patent: May 15, 2012Assignee: Disco CorporationInventor: Tomohiro Endo
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Patent number: 8178425Abstract: An optical device wafer processing method for dividing an optical device wafer into a plurality of individual optical devices. The optical device wafer is composed of a substrate and a semiconductor layer formed on the front side of the substrate. The optical devices are partitioned by a plurality of crossing division lines formed on the semiconductor layer.Type: GrantFiled: January 21, 2011Date of Patent: May 15, 2012Assignee: Disco CorporationInventors: Tasuku Koyanagi, Hiroshi Morikazu
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Patent number: 8148240Abstract: A semiconductor wafer is prepared. The wafer has a first and a second surface opposite to each other, and has a recess portion and a rim portion. The semiconductor wafer has semiconductor elements formed on the first surface. The rim portion surrounds the recess portion. The recess portion and the rim portion are composed of the first and second surfaces. The recess portion is formed so as to recede toward the first surface. A tape is adhered to the second surface of the semiconductor wafer. At least the recess portion of the semiconductor wafer is placed on a stage. The tape is sandwiched between the recess portion and the stage. Laser beam is irradiated to the recess portion from the side of the first surface and along predetermined dicing lines. The recess portion is cut off to divide the semiconductor wafer into chips.Type: GrantFiled: August 21, 2009Date of Patent: April 3, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Motoshige Kobayashi, Hideki Nozaki
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Patent number: 8148184Abstract: An optical device wafer processing method for dividing an optical device wafer into a plurality of individual optical devices. The optical device wafer is composed of a substrate and a semiconductor layer formed on the front side of the substrate. The optical devices are partitioned by a plurality of crossing division lines formed on the semiconductor layer.Type: GrantFiled: January 24, 2011Date of Patent: April 3, 2012Assignee: Disco CorporationInventors: Tasuku Koyanagi, Hiroshi Morikazu
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Patent number: 8139619Abstract: Provided are a group-III nitride semiconductor laser device with a laser cavity to enable a low threshold current on a semipolar surface of a hexagonal group-III nitride, and a method for fabricating the group-III nitride semiconductor laser device on a stable basis. Notches, e.g., notch 113a and others, are formed at four respective corners of a first surface 13a located on the anode side of a group-III nitride semiconductor laser device 11. The notch 113a or the like is a part of a scribed groove provided for separation of the device 11. The scribed grooves are formed with a laser scriber and the shape of the scribed grooves is adjusted by controlling the laser scriber. For example, a ratio of the depth of the notch 113a or the like to the thickness of the group-III nitride semiconductor laser device 11 is not less than 0.05 and not more than 0.Type: GrantFiled: August 12, 2011Date of Patent: March 20, 2012Assignee: Sumitomo Electric Industries, Ltd.Inventors: Shimpei Takagi, Yusuke Yoshizumi, Koji Katayama, Masaki Ueno, Takatoshi Ikegami
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Publication number: 20120038019Abstract: A method and structure for uncovering captive devices in a bonded wafer assembly comprising a top wafer and a bottom wafer. One embodiment method includes forming a plurality of cuts in the top wafer and removing a segment of the top wafer defined by the plurality of cuts. The bottom wafer remains unsingulated after the removal of the segment.Type: ApplicationFiled: September 25, 2008Publication date: February 16, 2012Inventors: Clayton Lee Stevenson, Jason C. Green, Daryl Ross Koehl, Buu Quoc Diep
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Publication number: 20120034728Abstract: The linear semiconductor substrate 1 or 2 of the present invention comprises at least one desired thin film 4 formed on a linear substrate 3 having a length ten or more times greater than a width, thickness, or diameter of the linear substrate itself. Adopting semiconductor as the thin film 4 forms a linear semiconductor thin film. The linear semiconductor substrate 1 or 2 of the present invention is produced by utilizing a fiber-drawing technique which is a fabricating technique of optical fibers.Type: ApplicationFiled: September 6, 2011Publication date: February 9, 2012Applicant: Furukawa Electric Co, Ltd.Inventors: Toshihiro NAKAMURA, Nobuaki ORITA, Hisashi KOAIZAWA, Kenkichi SUZUKI, Hiroshi KURASEKO, Michio KONDO
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Patent number: 8088649Abstract: A radiation-emitting semiconductor body with a carrier substrate and a method for producing the same. In the method, a structured connection is produced between a semiconductor layer sequence (2) and a carrier substrate wafer (1). The semiconductor layer sequence is subdivided into a plurality of semiconductor layer stacks (200) by means of cuts (6) through the semiconductor layer sequence, and the carrier substrate wafer (1) is subdivided into a plurality of carrier substrates (100) by means of cuts (7) through the carrier substrate wafer (1). In the method, the structured connection is formed in such a way that at least one semiconductor layer stack (200) is connected to one and only one associated carrier substrate (100). In addition, at least one cut (7) through the carrier substrate wafer is not extended by any of the cuts (6) through the semiconductor layer sequence such that a straight cut results through the carrier substrate wafer and the semiconductor layer sequence.Type: GrantFiled: May 3, 2007Date of Patent: January 3, 2012Assignee: OSRAM Opto Semiconductors GmbHInventors: Volker Härle, Zeljko Spika
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Patent number: 8084333Abstract: An object cutting method which can reliably remove particles remaining on cut sections of chips is provided. An expandable tape 23 is electrically charged in a state where a plurality of semiconductor chips 25 obtained by cutting a planar object to be processed along a line to cut are separated from each other on the expandable tape 23. This electric action causes particles remaining on cut sections of the semiconductor chips 25 to eject therefrom even when a molten processed region is formed in the cut sections. Therefore, particles remaining on the cut sections of the chips 25 can reliably be removed.Type: GrantFiled: February 14, 2008Date of Patent: December 27, 2011Assignee: Hamamatsu Photonics K.K.Inventor: Takeshi Sakamoto
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Publication number: 20110312158Abstract: A method and apparatus for dividing a thin film device having a first layer which is a lower electrode layer, a second layer which is an active layer and a third layer which is an upper electrode layer, the layers each being continuous over the device, into separate cells which are electrically interconnected in series.Type: ApplicationFiled: July 15, 2011Publication date: December 22, 2011Inventor: Adam North Brunton
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Patent number: 8076167Abstract: Provided are a group-III nitride semiconductor laser device with a laser cavity to enable a low threshold current on a semipolar surface of a hexagonal group-III nitride, and a method for fabricating the group-III nitride semiconductor laser device on a stable basis. Notches, e.g., notch 113a and others, are formed at four respective corners of a first surface 13a located on the anode side of a group-III nitride semiconductor laser device 11. The notch 113a or the like is a part of a scribed groove provided for separation of the device 11. The scribed grooves are formed with a laser scriber and the shape of the scribed grooves is adjusted by controlling the laser scriber. For example, a ratio of the depth of the notch 113a or the like to the thickness of the group-III nitride semiconductor laser device 11 is not less than 0.05 and not more than 0.Type: GrantFiled: July 14, 2010Date of Patent: December 13, 2011Assignee: Sumitomo Electric Industries, Ltd.Inventors: Shimpei Takagi, Yusuke Yoshizumi, Koji Katayama, Masaki Ueno, Takatoshi Ikegami
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Patent number: 8071429Abstract: Embodiments of a method for separating dies from a wafer having first and second sides. The process embodiment includes masking the first side of the wafer, the mask including openings therein to expose parts of the first side substantially aligned with scribe lines of the wafer. The process embodiment also includes etching from the exposed parts of the first side of the wafer until an intermediate position between the first and second sides and sawing the remainder of the wafer, starting from the intermediate position until reaching the second surface.Type: GrantFiled: November 24, 2010Date of Patent: December 6, 2011Assignee: OmniVision Technologies, Inc.Inventors: Yin Qian, Hsin-Chih Tai, Duli Mao, Vincent Venezia, Wei Zheng, Keh-Chiang Ku, Howard E. Rhodes
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Patent number: 8071481Abstract: A multi-step etching process produces trench openings in a silicon substrate that are immediately adjacent transistor structures formed over the substrate surface. The multi-step etching process is a Br-based etching operation with one step including nitrogen and a further step deficient of nitrogen. The etching process does not attack the transistor structure and forms an opening bounded by upper surfaces that extend downwardly from the substrate surface and are substantially vertical, and lower surfaces that bulge outwardly from the upper vertical sections and undercut the transistor structure. The aggressive undercut produces a desirable stress in the etched silicon surface. The openings are then filled with a suitable source/drain material and SSD transistors with desirable Idsat characteristics may then be formed.Type: GrantFiled: April 23, 2009Date of Patent: December 6, 2011Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ta-Wei Kao, Shiang-Bau Wang, Ming-Jie Huang, Chi-Hsi Wu, Shu-Yuan Ku
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Patent number: 8071405Abstract: Provided is a group-III nitride semiconductor laser device with a laser cavity enabling a low threshold current, on a semipolar surface of a support base the c-axis of a hexagonal group-III nitride of which tilts toward the m-axis. In a laser structure 13, a first surface 13a is a surface opposite to a second surface 13b and first and second fractured faces 27, 29 extend each from an edge 13c of the first surface 13a to an edge 13d of the second surface 13b. A scribed mark SM1 extending from the edge 13c to the edge 13d is made, for example, at one end of the first fractured face 27, and the scribed mark SM1 or the like has a depressed shape extending from the edge 13c to the edge 13d. The fractured faces 27, 29 are not formed by dry etching and thus are different from the conventional cleaved facets such as c-planes, m-planes, or a-planes. It is feasible to use emission of a band transition enabling a low threshold current.Type: GrantFiled: July 14, 2010Date of Patent: December 6, 2011Assignee: Sumitomo Electric Industries, Ltd.Inventors: Shimpei Takagi, Yusuke Yoshizumi, Koji Katayama, Masaki Ueno, Takatoshi Ikegami
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Patent number: 8062960Abstract: The present invention provides a method of manufacturing a compound semiconductor device capable of improving yield when a wafer is divided into device regions. The method of manufacturing a compound semiconductor device includes a division step. The division step includes: a first division step of dividing a wafer 30 in a first direction ? to obtain first strip wafers each having at least two rows of device portions 10 arranged in the first direction ?; a second division step of dividing the first strip wafer in a second direction ? to obtain second strip wafers each having a row of the device portions 10 arranged in the second direction ?; and a third division step of dividing the second strip wafer into the device portions 10, thereby forming compound semiconductor devices including the device portions 10.Type: GrantFiled: February 13, 2008Date of Patent: November 22, 2011Assignee: Showa Denko K.K.Inventor: Kazuhiro Kato
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Patent number: 8058151Abstract: A structure includes a substrate having a plurality of scribe line areas surrounding a plurality of die areas. Each of the die areas includes at least one first conductive structure formed over the substrate. Each of the scribe line areas includes at least one active region and at least one non-active region. The active region includes a second conductive structure formed therein. The structure further includes at least one first passivation layer formed over the first conductive structure and second conductive structure, wherein at least a portion of the first passivation layer within the non-active region is removed, whereby die-sawing damage is reduced.Type: GrantFiled: April 6, 2010Date of Patent: November 15, 2011Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shin-Puu Jeng, Hao-Yi Tsai
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Patent number: 8048706Abstract: Provided herein are improved methods of laser scribing photovoltaic structures to form monolithically integrated photovoltaic modules. The methods involve forming P1, P2 or P3 scribes by an ablative scribing mechanism having low melting, and in certain embodiments, substantially no melting. In certain embodiments, the methods involve generating an ablation shockwave at an interface of the film to be removed and the underlying layer. The film is then removed by mechanical shock. According to various embodiments, the ablation shockwave is generated by using a laser beam having a wavelength providing an optical penetration depth on the order of the film thickness and a minimum threshold intensity. In one embodiment, material including an absorber layer is scribed using an infrared laser source and a picosecond pulse width.Type: GrantFiled: October 14, 2010Date of Patent: November 1, 2011Assignee: MiasoleInventors: Osman Ghandour, Alex Austin, Daebong Lee, Jason Stephen Corneille, James Teixeira
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Patent number: 8039283Abstract: The present invention is directed to a production method for a nitride compound semiconductor element including a substrate and a multilayer structure 40 supported by an upper face of the substrate. First, a wafer 1 to be split into individual substrates is provided. A plurality of semiconductor layers composing the multilayer structure 40 are grown on the wafer 1. By cleaving the wafer 1 and the semiconductor layers, a cleavage plane in the multilayer structure 40 is formed. In the present invention, a plurality of voids are arranged at positions in the multilayer structure at which a cleavage plane is to be formed. Thus, cleavage can be performed with a good yield.Type: GrantFiled: December 20, 2006Date of Patent: October 18, 2011Assignee: Panasonic CorporationInventors: Yoshiaki Hasegawa, Toshiya Yokogawa, Atsushi Yamada, Yoshiaki Matsuda
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Patent number: 8008750Abstract: Crack stops for semiconductor devices, semiconductor devices, and methods of manufacturing semiconductor devices are disclosed. In one embodiment, a barrier structure for a semiconductor device includes a plurality of substantially V-shaped regions. Each of the plurality of substantially V-shaped regions is disposed adjacent another of the plurality of substantially V-shaped regions.Type: GrantFiled: February 1, 2008Date of Patent: August 30, 2011Assignee: Infineon Technologies AGInventors: Erdem Kaltalioglu, Michael Beck
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Patent number: 7998840Abstract: A wafer laser processing method for forming deteriorated layers in the inside of a wafer having a device area and a peripheral excess area surrounding the device area, the surface of the device area being higher than the surface of the peripheral excess area, involving a first step for forming a deteriorated layer in the insides of the peripheral excess area and device area by applying a laser beam to the peripheral excess area and the device area with its focal point set in the material of the peripheral excess area and the device area from the front surface side of the wafer; and a second step for forming a deteriorated layer in the inside of the device area by applying a laser beam to the device area with its focal point set in the material of the device area without applying the laser beam to the peripheral excess area.Type: GrantFiled: May 19, 2009Date of Patent: August 16, 2011Assignee: Disco CorporationInventor: Yosuke Watanabe
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Publication number: 20110193200Abstract: A method for forming a semiconductor device can include electrically testing a plurality of semiconductor dies in wafer form subsequent to performing a first wafer dicing process, then performing a second wafer dicing process to dice the wafer and to singularize the plurality of semiconductor dies. Electrically testing the plurality of semiconductor dies in wafer form subsequent to the first dicing process can identify chips damaged during the first dicing process. The method can also include forming a plurality of grooves between adjacent dies which leaves a full wafer thickness at a perimeter of the wafer to result in a wafer which is more resistant to deflection and damage during handling.Type: ApplicationFiled: September 14, 2010Publication date: August 11, 2011Inventors: Kevin P. Lyne, Stanley Craig Beddingfield, Elida I. De Obaldia, Raymundo Monasterio Camenforte, David Charles Stepniak
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Patent number: 7994024Abstract: An object cutting method which can reliably remove particles remaining on cut sections of chips is provided. An expandable tape 23 is electrically charged in a state where a plurality of semiconductor chips 25 obtained by cutting a planar object to be processed along a line to cut are separated from each other on the expandable tape 23. This electric action causes particles remaining on cut sections of the semiconductor chips 25 to eject therefrom even when a molten processed region is formed in the cut sections. Therefore, particles remaining on the cut sections of the chips 25 can reliably be removed.Type: GrantFiled: February 14, 2008Date of Patent: August 9, 2011Assignee: Hamamatsu Photonics K.K.Inventor: Takeshi Sakamoto
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Patent number: 7977213Abstract: A solution to failure mechanisms caused by mechanical sawing of a mechanical semiconductor workpiece entails use of a laser beam to cut and remove the electrically conductive and low-k dielectric material layers from a dicing street before saw dicing to separate semiconductor devices. A laser beam forms a laser scribe region such as a channel in the electrically conductive and low-k dielectric material layers, the bottom of the channel ending on a laser energy transparent stop layer of silicon oxide lying below all of the electrically conductive and low-k dielectric material layers. The disclosed process entails selection of laser parameters such as wavelength, pulse width, and fluence that cooperate to leave the silicon oxide layer stop layer completely or nearly undamaged. A mechanical saw cuts the silicon oxide layer and all other material layers below it, as well as the substrate, to separate the semiconductor devices.Type: GrantFiled: March 31, 2010Date of Patent: July 12, 2011Assignee: Electro Scientific Industries, Inc.Inventors: Andy E. Hooper, David Barsic, Clint R. Vandergiessen, Haibin Zhang, James N. O'Brien
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Publication number: 20110158276Abstract: In a III-nitride semiconductor laser device, a laser structure includes a support base comprised of a hexagonal III-nitride semiconductor and having a semipolar primary surface, and a semiconductor region provided on the semipolar primary surface of the support base. An electrode is provided on the semiconductor region of the laser structure. The c-axis of the hexagonal III-nitride semiconductor of the support base is inclined at an angle ALPHA with respect to a normal axis toward the m-axis of the hexagonal III-nitride semiconductor. The angle ALPHA is in the range of not less than 45 degrees and not more than 80 degrees or in the range of not less than 100 degrees and not more than 135 degrees. The laser structure includes first and second fractured faces that intersect with an m-n plane defined by the m-axis of the hexagonal III-nitride semiconductor and the normal axis. A laser cavity of the III-nitride semiconductor laser device includes the first and second fractured faces.Type: ApplicationFiled: July 15, 2010Publication date: June 30, 2011Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Shimpei TAKAGI, Yusuke YOSHIZUMI, Koji KATAYAMA, Masaki UENO, Takatoshi IKEGAMI
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Publication number: 20110158277Abstract: A III-nitride semiconductor laser device is provided with a laser structure and an electrode. The laser structure includes a support base which comprises a hexagonal III-nitride semiconductor and has a semipolar primary surface, and a semiconductor region provided on the semipolar primary surface. The electrode is provided on the semiconductor region. The semiconductor region includes a first cladding layer of a first conductivity type GaN-based semiconductor, a second cladding layer of a second conductivity type GaN-based semiconductor, and an active layer provided between the first cladding layer and the second cladding layer. The laser structure includes first and second fractured faces intersecting with an m-n plane defined by the m-axis of the hexagonal III-nitride semiconductor and an axis normal to the semipolar primary surface. A laser cavity of the III-nitride semiconductor laser device includes the first and second fractured faces.Type: ApplicationFiled: July 16, 2010Publication date: June 30, 2011Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Yusuke YOSHIZUMI, Yohei ENYA, Takashi KYONO, Takamichi SUMITOMO, Nobuhiro SAGA, Masahiro ADACHI, Kazuhide SUMIYOSHI, Shinji TOKUYAMA, Shimpei TAKAGI, Takatoshi IKEGAMI, Masaki UENO, Koji KATAYAMA
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Patent number: 7968379Abstract: A method for the separation of multiple dies during semiconductor fabrication is described. On an upper surface of a semiconductor wafer containing multiple dies, metal layers are deposited everywhere except where a block of stop electroplating material exists. The stop electroplating material is obliterated, and a barrier layer is formed above the entire remaining structure. A sacrificial metal element is added above the barrier layer, and then the substrate is removed. After the semiconductor material between the individual dies is eradicated, any desired bonding pads and patterned circuitry are added to the semiconductor surface opposite the sacrificial metal element, a passivation layer is added to this surface, and then the sacrificial metal element is removed. Tape is added to the now exposed barrier layer, the passivation layer is removed, the resulting structure is flipped over, and the tape is expanded to separate the individual dies.Type: GrantFiled: November 18, 2008Date of Patent: June 28, 2011Assignee: SemiLEDs Optoelectronics Co., Ltd.Inventors: Chen-Fu Chu, Trung Tri Doan, Hao-Chun Cheng, Feng-Hsu Fan, Fu-Hsien Wang