Making Grooves, E.g., Cutting (epo) Patents (Class 257/E21.238)
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Patent number: 7968430Abstract: A compound semiconductor device includes a laminated body including a crystal substrate and a compound semiconductor multilayer film. The laminated body has a major surface, a first side face, a second side face, a third side face, and a fourth side face. The first and the second side faces are opposed to each other, substantially perpendicular to the major surface of the laminated body, made of cleaved surfaces. The third and the fourth side faces are perpendicular to the major surface and to the first and the second side faces, opposed to each other, and made of uncleaved surfaces. A groove is provided on the third side face, and the groove has a depth varied with position as viewed from the major surface, and has ends not reaching the first and second side face.Type: GrantFiled: September 5, 2007Date of Patent: June 28, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Takayuki Matsuyama, Tadaaki Hosokawa, Seiji Iida, Akira Tanaka
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Patent number: 7955897Abstract: A chip structure according to the present invention is provided. A plurality of pedestals extends from the back surface of the chip structure. Each of the pedestals is located at a position away from the edge of the back surface for a non-zero distance so that the pedestals of an upper chip structure will not damage the bonding pads positioned on the edge of the active surface of a lower chip structure when the upper chip structure is stacked on the active surface of the lower chip structure with the pedestals.Type: GrantFiled: August 8, 2008Date of Patent: June 7, 2011Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Tsung Yueh Tsai, Yi Shao Lai, Cheng Wei Huang
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Patent number: 7947575Abstract: A method of laser machining a feature in a substrate includes machining the substrate with a pulsed laser along a scan line so that the successive pulses 81 at the substrate do not overlap but are either contiguous or spaced apart. Pulses 82, 83, 84 in respective succeeding scans of the laser along the scan line, are offset with respect to the starting point of pulses 81, 82, 83 in a previous scan so that multiple successive laser scans provide machining to a required depth while successively smoothing edges, 91, 92, 93, 94 of the feature with each pass.Type: GrantFiled: November 27, 2007Date of Patent: May 24, 2011Assignee: Electro Scientific Industries, Inc.Inventors: Kali Dunne, Callian Cillian O'Briain Fallon
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Publication number: 20110104874Abstract: In a pressure-sensitive adhesive composition or a pressure-sensitive adhesive sheet containing an energy ray-curable polymer, problems associated with the volatilization of a low molecular weight compound contained in the composition are overcome. An energy ray-curable polymer characterized by comprising a radical generating group, which is capable of initiating a polymerization reaction upon excitation with an energy ray, and an energy ray-polymerizable group bonded together in the main or side chain.Type: ApplicationFiled: March 12, 2009Publication date: May 5, 2011Applicant: LINTEC CORPORATIONInventors: Jun Maeda, Keiko Tanaka
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Patent number: 7923349Abstract: An electrically insulative conformal coating is applied at least to the active (front) side and one or more sidewalls of the die during wafer processing. Also, a die has an electrically insulative conformal coating applied to at least the active (front) side and sidewalls. Also, assemblies include a stack of such die, electrically interconnected die-to-die; and assemblies include such a die or a stack of such die, electrically interconnected to underlying circuitry (for example in a substrate or a circuit board).Type: GrantFiled: June 19, 2008Date of Patent: April 12, 2011Assignee: Vertical Circuits, Inc.Inventors: Simon J. S. McElrea, Terrence Caskey, Scott McGrath, DeAnn Eileen Melcher, Reynaldo Co, Lawrence Douglas Andrews, Jr., Weiping Pan, Grant Villavicencio, Yong Du, Scott Jay Crane, Zongrong Liu
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Patent number: 7923350Abstract: A method of manufacturing a semiconductor device. The method includes providing a wafer having a first face and a second face opposite the first face, selectively doping the wafer via the first face to selectively form etch stop regions in the wafer and etching the wafer at the second face to the etch stop regions.Type: GrantFiled: September 9, 2008Date of Patent: April 12, 2011Assignee: Infineon Technologies AGInventors: Joachim Mahler, Edward Fuergut, Werner Kroeninger
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Patent number: 7902076Abstract: A method of fabricating a semiconductor device according to one embodiment includes: forming a porous film above a semiconductor substrate; forming an altered layer by applying alteration treatment to a first pattern region of the porous film up to a predetermined depth; forming a first concave portion by etching a second pattern region to a depth deeper than the predetermined depth, the second pattern region at least partially overlapping the first pattern region of the porous film having the altered layer formed therein; and forming a second concave portion by selectively removing the altered layer from the porous film after forming the first concave portion.Type: GrantFiled: June 3, 2009Date of Patent: March 8, 2011Assignee: Kabushiki Kaisha ToshibaInventor: Tsubasa Imamura
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Publication number: 20110053376Abstract: Example embodiments are directed to a wafer dividing apparatus and method thereof. The wafer dividing apparatus includes a chuck unit having upper and lower chucks, a cutting wire that is provided in a space between the upper and lower chucks to cut a wafer and driven by a first driving unit, and an etchant supplying nozzle supplying etchant to a groove of the wafer, which is formed by the cutting wire.Type: ApplicationFiled: August 11, 2010Publication date: March 3, 2011Applicant: Samsung Electronics Co., Ltd.Inventors: Hotae Jin, Seonju Oh, HeuiSeog Kim
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Patent number: 7897483Abstract: Objects are to reduce damage to a semiconductor integrated circuit by external stress and to increase the manufacturing yield of a thinned semiconductor integrated circuit. A single crystal semiconductor layer separated from a single crystal semiconductor substrate is used for a semiconductor element included in the semiconductor integrated circuit. Moreover, a substrate which is formed into a thin shape and provided with the semiconductor integrated circuit is covered with a resin layer. In a separation step, a groove for separating a semiconductor element layer is formed in the supporting substrate, and a resin layer is provided over the supporting substrate in which the groove is formed. After that, the resin layer and the supporting substrate are cut in the groove so as to be divided into a plurality of semiconductor integrated circuits.Type: GrantFiled: December 19, 2008Date of Patent: March 1, 2011Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Hidekazu Takahashi, Daiki Yamada, Yohei Monma, Hiroki Adachi
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Publication number: 20110045656Abstract: An assembly for cutting a plurality of substrates into individual integrated circuit units includes a first block for receiving a first substrate. The first block is movable between a first loading position, a first alignment inspection station and a first cutting zone. A second block for receiving a second substrate is movable between a second loading position, a second alignment inspection station and a second cutting zone. A cutting device for cutting a substrate into individual integrated circuit units is movable between the first cutting zone and the second cutting zone. An alignment inspection device for determining the alignment of a substrate positioned on either the first or second block is movable between the first alignment inspection station and the second alignment inspection station.Type: ApplicationFiled: May 30, 2008Publication date: February 24, 2011Applicant: ROKKO VENTURES PTE, LTD.Inventor: Chong Chen Lim
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Patent number: 7892950Abstract: A method (20, 104) for processing a panel (26, 128) during semiconductor device (52) fabrication entails forming grooves (72, 142) in a surface (34, 132) of the panel (26, 128) coincident with a dicing pattern (54) for the panel (26, 128). The grooves (72, 142) extend partially through the panel (26, 128) so that the panel (26, 128) remains intact. The grooves (72, 142) relieve stress in the panel (26, 128) to reduce panel (26, 128) warpage, thus enabling the panel (26, 128) to be reliably held on a support structure (88, 98, 138) via vacuum when undergoing further processing, such as solder printing (86). The method (20, 104) further entails, dicing (96, 152) through the panel (26, 128) from the surface (34, 132) in accordance with the dicing pattern (54) while the panel (26, 128) is mounted on the support structure (98, 138) to singularize the semiconductor devices (52).Type: GrantFiled: April 29, 2009Date of Patent: February 22, 2011Assignee: Freescale Semiconductor, Inc.Inventors: Alan J. Magnus, Justin E. Poarch, Jason R. Wright
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Patent number: 7888180Abstract: A semiconductor apparatus includes a semiconductor device having electrodes on its opposed frontside and backside, respectively, a first external electrode connected to the electrode at the frontside, the first external electrode having a first major surface generally parallel to the frontside of the semiconductor device, and a first side surface generally perpendicular to the first major surface, and a second external electrode having a second major surface generally parallel to the backside of the semiconductor device, a second side surface generally perpendicular to the second major surface, and a projection protruding perpendicular to the second major surface and connected to the electrode at the backside, The first side surface of the first external electrode and the second side surface of the second external electrode serve as mount surfaces. The semiconductor device is located between the first external electrode and the second external electrode.Type: GrantFiled: May 30, 2008Date of Patent: February 15, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Takao Nogi, Kentaro Suga
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Patent number: 7883992Abstract: A laser beam is applied to an intersection area of each second street of a wafer by using a dicing apparatus to thereby form a first modified layer along the intersection area. Thereafter, the wafer is divided along each first street intersecting each second street at right angles to obtain a plurality of wafer strips. Thereafter, the laser beam is applied along the remaining area of each second street other than the intersection area to form a second modified layer along the remaining area of each second street. Thereafter, an external force is applied to each wafer strip in which the first and second modified layers have been formed along each second street, thereby dividing each wafer strip along each second street to obtain a plurality of devices.Type: GrantFiled: November 21, 2008Date of Patent: February 8, 2011Assignee: Disco CorporationInventor: Kenji Furuta
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Patent number: 7883965Abstract: A semiconductor device includes a device isolation structure, a recess channel structure, and a gate electrode. The device isolation structure is formed in a semiconductor substrate to define an active region. The recess channel structure is disposed in the semiconductor substrate under the active region. The gate electrode includes a holding layer disposed in a gate region to fill the recess channel structure. The holding layer prevents a seam and a shift of the seam occurring in the recess channel structure.Type: GrantFiled: December 30, 2006Date of Patent: February 8, 2011Assignee: Hynix Semiconductor Inc.Inventors: Shin Gyu Choi, Seung Chul Oh
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Publication number: 20110027927Abstract: A light-emitting diode (LED) cutting method includes the following steps: (A) positioning and retaining an LED chip or an LED epitaxial substrate on a chip retainer; (B) introducing a liquid medium to serve as a sound wave reflection layer medium between a cutting tool and the chip; (C) activating a power source to drive a magnetostrictive or piezoelectric ceramic material mounted on a machine to serve as a power source by inducing volume expansion/compression that generates up-and-down piston-like movement; and (D) operating the cutting tool of a proper shape that has a surface on which super hard micro-particles of diamond, CBN, or SiC are electroformed to carry out up-and-down piston-like reciprocal motion on the material retained on the chip retainer to drive the super hard micro-particles on the surface of the cutting tool into a pre-cut workpiece to perform breaking cutting.Type: ApplicationFiled: July 29, 2009Publication date: February 3, 2011Inventor: TIEN-TSAI LIN
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Patent number: 7875501Abstract: A backgrinding machine 10 of a semiconductor wafer W includes: a table 13 set on the working plane of a mount 11; a multiple number of holding jigs 20 arranged via check tables 15 on table 13; a grinding machine 30 for performing a grinding process of the rear side of semiconductor wafer W held by holding jig 20; and a washing device 40 for ground semiconductor wafers W. Each holding jig 20 is constructed of a concave 22 depressed on the surface of a base plate 21, a multiple number of supporting projections 23 projectively arrayed on the bottom surface of concave 22, a deformable contact film 24, covering the concave 22, being supported by the multiple supporting projections 23, for detachably holding semiconductor wafer W in close contact with it; and an exhaust path 25 for conducting air from the concave 22 covered by contact film 24 to the outside.Type: GrantFiled: March 9, 2007Date of Patent: January 25, 2011Assignees: Shin-Etsu Polymer Co., Ltd., Lintec CorporationInventors: Kiyofumi Tanaka, Satoshi Odashima, Noriyoshi Hosono, Hironobu Fujimoto, Takeshi Segawa
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Publication number: 20110005566Abstract: A photovoltaic cell module and a method of making the same are provided. The photovoltaic cell module includes a first cell including a first transparent conductive substrate, a first photovoltaic conversion layer, and a first electrode layer, at least a second cell electrically connected to the first cell in series; and a second electrode layer electrically connected to the second cell. In the first cell, the first photovoltaic conversion layer is disposed on the first transparent conductive substrate. The first electrode layer is disposed on the first photovoltaic conversion layer and electrically connected to the first transparent conductive substrate. In addition, the present invention also provides the method of making the photovoltaic cell module.Type: ApplicationFiled: July 7, 2009Publication date: January 13, 2011Applicant: CHI-MEI ENERGY CORP.Inventors: Chih-Jeng HUANG, Yu-Hua WU, Liang-Tang WANG, Wei-Teng CHANG
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Patent number: 7863151Abstract: A manufacturing method for manufacturing a super-junction semiconductor device forms an oxide film and a nitride film on an n-type epitaxial layer exhibiting high resistance on an n-type semiconductor substrate exhibiting low resistance. The portion of the nitride film in the scribe region is left unremoved by patterning and an alignment marker is opened through the nitride film. After opening a trench pattern in the oxide film, trenches having a high aspect ratio are formed. The portion of the oxide film outside the scribe region is removed and a p-type epitaxial layer is buried in the trenches. The overgrown p-type epitaxial layer is polished with reference to the nitride film, the polished surface is finished by etching, and the n-type epitaxial layer surface is exposed.Type: GrantFiled: June 23, 2009Date of Patent: January 4, 2011Assignee: Fuji Electric Systems Co., Ltd.Inventor: Manabu Takei
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Patent number: 7825010Abstract: Some embodiments include methods in which a front side region of a semiconductor substrate is placed against a surface. While the front side region is against the surface, the semiconductor substrate is thinned, and then cut into a plurality of dice. The surface may be a pliable material, and may be stretched after the cutting to increase separation between at least some of the dice. While the pliable surface is stretched, at least some of the dice may be picked from the surface. In some embodiments, the semiconductor substrate is retained to the surface with a radiation-curable material. The material is in an uncured and tacky form during the thinning of the substrate, and is subsequently cured into a less tacky form prior to the picking of dice from the surface.Type: GrantFiled: June 7, 2007Date of Patent: November 2, 2010Assignee: Micron Technology, Inc.Inventor: Paul Clawson
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Publication number: 20100261334Abstract: A semiconductor device wherein destruction of a sealing ring caused by cracking of an interlayer dielectric film is difficult to occur, as well as a method for manufacturing the semiconductor device, are provided. A first laminate comprises first interlayer dielectric films having a first mechanical strength. A second laminate comprises second interlayer dielectric films having a mechanical strength higher than the first mechanical strength. A first region includes first metallic layers and vias provided within the first laminate. A second region includes second metallic layers and vias provided within the second laminate. When seen in plan, the second region overlaps at least a part of the first region, is not coupled with the first region by vias, and sandwiches the second interlayer dielectric film between it and the first region.Type: ApplicationFiled: June 23, 2010Publication date: October 14, 2010Applicant: Renesas Technology Corp.Inventors: Hiroyuki CHIBAHARA, Atsushi Ishii, Naoki Izumi, Masahiro Matsumoto
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Patent number: 7807482Abstract: The invention concerns a method for preparing a thin layer (28) or a chip to be transferred onto another substrate, this method including the realization, above the surface of said thin layer or said chip, of at least one layer, called adhesive layer (25), and of at least one layer, called first barrier layer (22), the adhesive layer being made of a material of which etching presents selectivity in relation to the material of the barrier layer.Type: GrantFiled: June 2, 2005Date of Patent: October 5, 2010Assignee: S.O.I.Tec Silicon On Insulator TechnologiesInventors: Bernard Aspar, Chrystelle Lagahe-Blanchard
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Publication number: 20100197113Abstract: To provide a thin semiconductor device having flexibility. A groove is formed in one surface of a substrate; an element layer including an element is formed, the element being disposed within the groove; the substrate is thinned from the other surface of the substrate until one surface of the element layer is exposed, to form a layer which is to be transposed, having the element; and the layer to be transposed is transposed onto the film.Type: ApplicationFiled: April 7, 2010Publication date: August 5, 2010Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventor: Takuya TSURUME
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Patent number: 7767554Abstract: An object is to provide a semiconductor chip manufacturing method capable of removing test patterns in a higher efficiency in simple steps, while a general-purpose characteristic can be secured. In a method in which a semiconductor wafer 1 having integrated circuits 3 formed in a plurality of chip regions and test patterns 4 formed in scribe lines 2a is divided by a plasma etching process so as to manufacture individual semiconductor chips, laser light 5a is irradiated from the side of a circuit forming plane 1a so as to remove the test patterns 4; and thereafter, under such a condition that a circuit protection seat 6 is adhered onto a circuit forming plane 1a, a rear plane of the circuit forming plane 1a is mechanically thinned; a mask-purpose seat is adhered onto the rear plane 1b of the semiconductor wafer 1 after the plane thinning process; and then, a plasma dicing-purpose mask is work-processed by irradiating laser light.Type: GrantFiled: March 5, 2008Date of Patent: August 3, 2010Assignee: Panasonic CorporationInventors: Kiyoshi Arita, Atsushi Harikai
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Patent number: 7767555Abstract: A method for cutting a substrate is disclosed which uses a femtosecond laser capable of preventing thermal expansion and generation of shock waves from occurring around a region where a cutting process is carried out when the femtosecond laser is used to cut the substrate, thereby being capable of achieving a reduction in costs. The method includes the steps of arranging the substrate on a stage, and irradiating a femtosecond laser to a predetermined portion of the substrate arranged on the stage, thereby cutting the substrate along the predetermined substrate portion.Type: GrantFiled: June 28, 2005Date of Patent: August 3, 2010Assignee: LG. Display Co., Ltd.Inventor: Jeong Kweon Park
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Patent number: 7763916Abstract: A substrate table used for manufacturing a chip is provided. The substrate table includes a substrate stage, a substrate placement surface formed on the substrate stage, and on which a substrate is placed, and a guiding member that can project and retract from the substrate placement surface. The guiding member positions the substrate when the guiding member is at a projected position abutting an edge portion of the substrate placed on the substrate placement surface, and the guiding member retracts at a time of applying a tape to the substrate.Type: GrantFiled: April 17, 2008Date of Patent: July 27, 2010Assignee: Oki Semiconductor Co., Ltd.Inventor: Hiromi Morita
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Patent number: 7754583Abstract: A laser processing method which can securely prevent particles from attaching to chips obtained by cutting a planar object is provided. When applying a stress to an object to be processed 1 through an expandable tape 23, forming materials of the object 1 (the object 1 formed with molten processed regions 13, semiconductor chips 25 obtained by cutting the object 1, particles produced from cut sections of the semiconductor chips 25, and the like) are irradiated with soft x-rays. As a consequence, the particles produced from the cut sections of the semiconductor chips 25 obtained by cutting the object 1 fall on the expandable tape 23 without dispersing randomly. This can securely prevent the particles from attaching to the semiconductor chips 25 obtained by cutting the object 1.Type: GrantFiled: November 16, 2006Date of Patent: July 13, 2010Assignee: Hamamatsu Photonics K.K.Inventor: Takeshi Sakamoto
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Patent number: 7754581Abstract: A method for manufacturing a semiconductor device includes the steps of forming first and second semiconductor wafers each including an array of chips and elongate electrodes, forming a groove on scribe lines separating the chips from one another; coating a surface of one of the semiconductor wafers with adhesive; bonding together the semiconductor wafers while allowing the groove to receive therein excessive adhesive; and heating the wafers to connect the elongate electrodes of both the semiconductor wafers.Type: GrantFiled: December 14, 2007Date of Patent: July 13, 2010Assignee: Elpida Memory, Inc.Inventors: Hiroaki Ikeda, Masakazu Ishino, Hiroyuki Tenmei, Naoya Kanda, Yasuhiro Naka, Kunihiko Nishi
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Patent number: 7750478Abstract: A semiconductor device with improved reliability and its manufacturing method is offered. The semiconductor device of this invention includes a semiconductor substrate, a pad electrode formed on the semiconductor substrate through an insulation layer made of silicon oxide, silicon nitride or the like, a supporting plate bonded to a top surface of the semiconductor substrate to cover the pad electrode and a via hole formed in the semiconductor substrate and extending from a back surface of the semiconductor substrate to the pad electrode, wherein an aperture of the via hole at a portion close to the pad electrode is larger than an aperture of the via hole at a portion close to the back surface of the semiconductor substrate.Type: GrantFiled: June 12, 2007Date of Patent: July 6, 2010Assignees: Sanyo Electric Co., Ltd., Kabushiki Kaisha Toshiba, Fujitsu Microelectronics Limited, NEC CorporationInventors: Koujiro Kameyama, Akira Suzuki, Yoshio Okayama, Mitsuo Umemoto, Kenji Takahashi, Hiroshi Terao, Masataka Hoshino
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Patent number: 7741701Abstract: A method for treating an area of a semiconductor wafer surface with a laser for reducing stress concentrations is disclosed. The wafer treatment method discloses treating an area of a wafer surface with a laser beam, wherein the treated area is ablated or melted by the beam and re-solidifies into a more planar profile, thereby reducing areas of stress concentration and stress risers that contribute to cracking and chipping during wafer singulation. Preferably, the treated area has a width less than that of a scribe street, but wider than the kerf created by a wafer dicing blade. Consequently, when the wafer is singulated, the dicing blade will preferably saw through treated areas only. It will be understood that the method of the preferred embodiments may be used to treat other areas of stress concentration and surface discontinuities on the wafer, as desired.Type: GrantFiled: March 13, 2006Date of Patent: June 22, 2010Assignee: Texas Instruments IncorporatedInventors: Richard L. Mahle, Peter J. Sakakini
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Patent number: 7732897Abstract: A structure includes a substrate having a plurality of scribe line areas surrounding a plurality of die areas. Each of the die areas includes at least one first conductive structure formed over the substrate. Each of the scribe line areas includes at least one active region and at least one non-active region. The active region includes a second conductive structure formed therein. The structure further includes at least one first passivation layer formed over the first conductive structure and second conductive structure, wherein at least a portion of the first passivation layer within the non-active region is removed, whereby die-sawing damage is reduced.Type: GrantFiled: June 15, 2006Date of Patent: June 8, 2010Assignee: Taiwan Semiconductor Manufacturing Co., LtdInventors: Shin-Puu Jeng, Hao-Yi Tsai
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Patent number: 7727810Abstract: A method of dividing a wafer having a plurality of areas, which are sectioned by the streets formed on the front surface in a lattice pattern and a plurality of devices, which are formed in the sectioned areas, along streets, the method comprising a first cutting step for holding the front surface of the wafer on a chuck table of a cutting machine and forming a first groove having a depth that is about half of the thickness of the wafer, along the streets from the rear surface of the wafer; a second cutting step for holding the rear surface of the wafer on a chuck table and forming a second groove which does not reach the first groove, along the streets from the front surface of the wafer; and a dividing step for breaking an uncut portion between the first groove and the second groove by exerting external force along the streets of the wafer, on which the first grooves and the second grooves have been formed.Type: GrantFiled: July 21, 2006Date of Patent: June 1, 2010Assignee: Disco CorporationInventors: Kazuhisa Arai, Masatoshi Nanjo
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Publication number: 20100127409Abstract: A microelectronic device wafer includes an adhesive molded in-situ on the wafer. Adhesives and wafers are positioned in molds and a method that includes drawing in the molds at least a partial vacuum and partially curing the adhesive provides an in-situ molded adhesive that is positioned on the wafer. The adhesives can be in liquid, solid, or other forms prior to molding. During molding, the adhesive can be partially cured by heating or irradiating.Type: ApplicationFiled: November 26, 2008Publication date: May 27, 2010Applicant: MICRON TECHNOLOGY, INC.Inventors: Tongbi Jiang, Shijian Luo
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Patent number: 7718454Abstract: A method of manufacturing semiconductor laser device including a GaN wafer includes forming a semiconductor layer on the GaN wafer and on which ridge portions are formed. Grooves are formed in the semiconductor layer such that each groove is disposed in line with the scribe marks, between each of the ridge portions and an upstream scribe mark. The grooves are curved and convex outwardly towards a downstream side, and each groove has an apex on a cleavage line. The side extending from the apex preferably does not form an angle of 60 degrees with respect to a cleavage direction or the cleavage line.Type: GrantFiled: February 12, 2008Date of Patent: May 18, 2010Assignee: Mitsubishi Electric CorporationInventors: Hitoshi Nakamura, Shinji Abe, Harumi Nishiguchi
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Publication number: 20100109115Abstract: Integrated circuits are made by bonding to a substrate one or more slices of material, and forming circuits using the slices of material.Type: ApplicationFiled: November 3, 2008Publication date: May 6, 2010Inventor: Michael J. Ure
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Publication number: 20100109156Abstract: The present invention provides a semiconductor device package, comprising a die having a back surface and an active surface formed thereon; a conductive layer formed upon the back surface of the die; and a protection substrate formed on the conductive layer. An adhesive layer is formed between the conductive layer and the protective layer, if necessary. The present invention further provides a method for forming a semiconductor device package, comprising providing a plurality of die having a back surface and an active surface on a wafer; forming a conductive layer upon the back surface of the die; forming protection substrates on the conductive layer; forming a plurality of bumps on the active surface of each die; and dicing the plurality of die into individual die for singulation by exerting external force on the substrate. An adhesive layer is formed between the conductive layer and the protective layer, if necessary.Type: ApplicationFiled: November 4, 2008Publication date: May 6, 2010Inventors: Yu-Shan Hu, Shih-Chuan Wei, Dyi-Chung Hu
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Patent number: 7709932Abstract: A conveyance system for a semiconductor wafer can be used without any change before and after a support plate is adhered to the wafer. Also, the finish accuracy of the wafer and the positioning accuracy between the wafer and the support plate can be relaxed, thus improving the manufacturing efficiency. The wafer is formed on its peripheral portion with a stepped portion, which is deeper than a finished thickness obtained by partial removal of the rear surface thereof and which can be eliminated by the partial removal of the wafer rear surface. The separation portion has a length which extends radially outward from a flat surface, and which is greater than a total sum of a maximum-minimum difference between the finish allowances of the diameters of the wafer and the support plate, and a maximum value of a positioning error between the wafer and the support plate generated upon adhesion thereof.Type: GrantFiled: October 7, 2005Date of Patent: May 4, 2010Assignee: Renesas Technology Corp.Inventors: Yoshihiko Nemoto, Masahiro Sunohara, Kenji Takahashi
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Publication number: 20100087023Abstract: A laser beam machining method wherein machining areas in which to form machined grooves and machining start point areas in which to form shallow grooves shallower than the machined grooves are alternately set in each of streets formed on a wafer, and the machined grooves and the shallow grooves are continuously formed by scanning an irradiation point of a laser beam along each of the streets.Type: ApplicationFiled: September 1, 2009Publication date: April 8, 2010Applicant: DISCO CORPORATIONInventor: Tomohiro Endo
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Patent number: 7687374Abstract: Provided is a method of isolating semiconductor laser diodes (LDs), the method including the steps of: preparing a substrate; forming a plurality of semiconductor LDs on the substrate, each semiconductor LD including an n-type semiconductor layer, an active layer, a p-type semiconductor layer, an n-electrode, a ridge portion, and a p-electrode, the ridge portion being formed by etching the p-type semiconductor layer such that a portion of the p-type semiconductor layer protrudes, the p-electrode being formed on the ridge portion; partially forming base cut lines on the surface of the substrate excluding the ridge portions; and isolating the semiconductor LDs into a bar shape along the base cut lines.Type: GrantFiled: April 30, 2008Date of Patent: March 30, 2010Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Youn Joon Sung, Su Hee Chae
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Patent number: 7687322Abstract: Techniques for fabricating metal devices, such as vertical light-emitting diode (VLED) devices, power devices, laser diodes, and vertical cavity surface emitting laser devices, are provided. Devices produced accordingly may benefit from greater yields and enhanced performance over conventional metal devices, such as higher brightness of the light-emitting diode and increased thermal conductivity. Moreover, the invention discloses techniques in the fabrication arts that are applicable to GaN-based electronic devices in cases where there is a high heat dissipation rate of the metal devices that have an original non- (or low) thermally conductive and/or non- (or low) electrically conductive carrier substrate that has been removed.Type: GrantFiled: October 11, 2006Date of Patent: March 30, 2010Assignee: SemiLEDs Optoelectronics Co., Ltd.Inventors: Trung Tri Doan, Chuong Anh Tran, Chen-Fu Chu, Chao-Chen Cheng, Jiunn-Yi Chu, Wen-Huang Liu, Hao-Chun Cheng, Feng-Hsu Fan, Jui-Kang Yen
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Patent number: 7687373Abstract: In the case of cutting streets on the rear surface of a wafer by laser beam irradiation, even if the wafer is variously doped or thermally-treated, the streets of a wafer front surface can accurately be detected and cut. Infrared light is emitted from an infrared light source to the front surface side of the wafer to penetrate the wafer. The penetrating image is captured by an infrared microscope disposed on the rear surface side of the wafer. The streets are detected by the image pattern of a wafer front surface captured. A laser beam is emitted from a laser head to the wafer rear surface along the streets detected, thus processing the streets for cutting.Type: GrantFiled: October 19, 2007Date of Patent: March 30, 2010Assignee: Disco CorporationInventor: Kazuma Sekiya
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Publication number: 20100072594Abstract: Exemplary embodiments provide methods and systems for assembling electronic devices, such as integrated circuit (IC) chips, using a release member having a phase change material. Specifically, IC elements/components can be selectively received, stored, inspected, repaired, and/or released in a scalable manner during the assembly of IC chips by inducing phase change of the phase change material. The release member can be flexible or rigid. In some embodiments, the release member can be used for a low cost placement of the IC elements in combination with an SOI (silicon on insulator) wafer and/or an intermediate transfer member. In other embodiments, the release member can be used for a low cost placement of the IC elements in combination with a release wafer.Type: ApplicationFiled: September 24, 2008Publication date: March 25, 2010Inventors: Roger S. Kerr, Timothy J. Tredwell, Seung-Ho Baek
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Method of treating a substrate, method of processing a substrate using a laser beam, and arrangement
Patent number: 7682937Abstract: A method and arrangement for treating a substrate processed using a laser beam, wherein said substrate comprises at least a body of semiconductor material. The method comprises a step of etching said substrate for removing from said body of semiconductor material recast material deposited on said body during said laser processing. The step of etching is controlled for removing in addition to said recast layer, at least a part of said semiconductor material of said body for improving mechanical strength of said substrate.Type: GrantFiled: November 25, 2005Date of Patent: March 23, 2010Assignee: Advanced Laser Separation International B.V.Inventors: Rogier Evertsen, Hans Peter Chall -
Publication number: 20100068849Abstract: A translucent solar cell and a manufacturing method thereof are provided. The translucent solar cell at least includes a substrate, a front electrode layer, a photoconductive layer, and a back electrode layer stacked in order. Therein, a plurality of apertures are formed on the front electrode layer. In addition, a plurality of light-transmissive regions are formed on the back electrode layer and further extended in a depth direction so as to reach the plurality of apertures on the front electrode layer. Thus, the projected area of each light-transmissive region is within and smaller than that of the corresponding aperture.Type: ApplicationFiled: September 14, 2009Publication date: March 18, 2010Inventors: Chun-Hsiung LU, Chien-Chung BI
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Patent number: 7678673Abstract: The present invention provides a method of strengthening a structure, to heal the imperfection of the structure, to reinforce the structure, and thus strengthening the dielectric without compromising the desirable low dielectric constant of the structure. The inventive method includes the steps of providing a semiconductor structure having at least one interconnect structure; dicing the interconnect structure; applying at least one infiltrant into the interconnect structure; and infiltrating the infiltrant to infiltrate into the interconnect structure.Type: GrantFiled: August 1, 2007Date of Patent: March 16, 2010Assignee: International Business Machines CorporationInventors: Elbert Huang, William F. Landers, Michael Lane, Eric G. Liniger, Xiao H. Liu, David L. Questad, Thomas M. Shaw
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Patent number: 7679202Abstract: A plurality of device patterns constituting part of an electronic circuit are formed over the surface of a substrate. A symbol pattern to be used for an identification sign is formed in the same layer as the device patterns. A width of the device pattern is within a pattern width range on a design rule. The symbol pattern is formed by a plurality of isolated element patterns. The element pattern is either a linear pattern or a dot pattern. A width of the element pattern is equal to or larger than 0.8 time a lower limit value of the pattern width range and equal to or smaller than 1.2 times an upper limit value of the pattern width range.Type: GrantFiled: April 24, 2007Date of Patent: March 16, 2010Assignee: Fujitsu Microelectronics LimitedInventors: Shigeki Yoshida, Fumio Ushida, Nobuhisa Naori, Yasutaka Ozaki
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Publication number: 20100059864Abstract: A method of manufacturing a semiconductor device. The method includes providing a wafer having a first face and a second face opposite the first face, selectively doping the wafer via the first face to selectively form etch stop regions in the wafer and etching the wafer at the second face to the etch stop regions.Type: ApplicationFiled: September 9, 2008Publication date: March 11, 2010Applicant: Infineon Technologies AGInventors: Joachim Mahler, Edward Fuergut, Werner Kroeninger
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Patent number: 7674690Abstract: A method divides a wafer into at least one chip. The chip includes internal metallic features. The dividing deposits at least one metallic substance on the outer surface of the chip. After so dividing the chip, the process exposes the chip to a heated ambient environment having a given pressure (e.g., less than one atmosphere). The environment comprises a chemical agent capable of bonding with the metallic substance. Additionally, wet chemical etch can be performed on the chip.Type: GrantFiled: July 15, 2008Date of Patent: March 9, 2010Assignee: International Business Machines CorporationInventors: Mukta G. Farooq, Robert Hannon, Da-Young Jung
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Publication number: 20100048000Abstract: A semiconductor wafer is prepared. The wafer has a first and a second surface opposite to each other, and has a recess portion and a rim portion. The semiconductor wafer has semiconductor elements formed on the first surface. The rim portion surrounds the recess portion. The recess portion and the rim portion are composed of the first and second surfaces. The recess portion is formed so as to recede toward the first surface. A tape is adhered to the second surface of the semiconductor wafer. At least the recess portion of the semiconductor wafer is placed on a stage. The tape is sandwiched between the recess portion and the stage. Laser beam is irradiated to the recess portion from the side of the first surface and along predetermined dicing lines. The recess portion is cut off to divide the semiconductor wafer into chips.Type: ApplicationFiled: August 21, 2009Publication date: February 25, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Motoshige Kobayashi, Hideki Nozaki
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Patent number: 7662661Abstract: A method of manufacturing a substrate structure includes the steps of: (1) providing a metal substrate having a metal portion; (2) chemically etching a plurality of trenches in the metal substrate; (3) applying a polymer composite material into the trenches to form a substrate having a polymer composite portion abutted to the metal portion; (4) polishing a surface of the substrate to make a height of the polymer composite portion equal to that of the metal portion; (5) forming a covering material on the surface of the substrate; and (6) cutting the substrate via the polymer composite portion for decreasing cutting bur produced on the metal portion. Furthermore, the method is provided for combining the metal substrate and the polymer composite material, thereby to increase cutting precision and strength of the substrate structure.Type: GrantFiled: December 16, 2005Date of Patent: February 16, 2010Assignee: Harvatek CorporationInventors: Bily Wang, Jonnie Chuang, Hui-Yen Huang
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Patent number: 7655540Abstract: A method and jig structure for positioning bare dice is disclosed. The jig structure for positioning at least one bare dice includes a trap having at least one positioning groove wherein the depth of the positioning groove is less than the height of the bare dice. Basing on the positioning groove formed in the tray, once a bare dice is placed in the positioning groove, the partially exposed bare dice can be located directly and precisely vacuum-grabbed by a sucker, so that the number of positioning steps is reduced.Type: GrantFiled: March 21, 2008Date of Patent: February 2, 2010Assignee: Universal Scientific Industrial Co., Ltd.Inventor: Cho-Hsin Chang