Abstract: This semiconductor memory device comprises a semiconductor substrate, a plurality of tunnel insulator films formed on the semiconductor substrate along a first direction and a second direction orthogonal to the first direction with certain spaces in each directions, a plurality of charge accumulation layers formed on the plurality of tunnel insulator films, respectively, a plurality of element isolation regions formed on the semiconductor substrate, the plurality of element isolation regions including a plurality of trenches formed along the first direction between the plurality of tunnel insulator films, a plurality of element isolation films filled in the plurality of trenches, a plurality of inter poly insulator films formed over the plurality of element isolation regions and on the upper surface and side surfaces of the plurality of charge accumulation layer along the second direction in a stripe shape, a plurality of air gaps formed between the plurality of element isolation films filled in the plurality

Abstract: A semiconductor embedded module 1 of the present invention has a configuration in which a semiconductor device 20, which is an electronic component such as a semiconductor IC (die) in a bare chip state, is embedded in a resin layer 10 (second insulating layer). In the semiconductor device 20, a redistribution layer 22 is connected to land electrodes. A protective layer 24 (first insulating layer) is provided on the redistribution layer 22, and is provided with openings such that external connection pads P of the redistribution layer 22 are exposed. Also, the resin layer 10 is formed to cover the protective layer 24, and vias V are formed at the positions of the respective external connection pads P of the redistribution layer 22. The grinding rate of the resin layer 10 is larger than that of the protective layer 24.

Abstract: A method of cutting an object which can accurately cut the object is provided. An object to be processed 1 such as a silicon wafer is irradiated with laser light L while a light-converging point P is positioned therewithin, so as to form a modified region 7 due to multiphoton absorption within the object 1, and cause the modified region 7 to form a starting point region for cutting 8 shifted from the center line CL of the thickness of the object 1 toward the front face 3 of the object 1 along a line along which the object should be cut. Subsequently, the object 1 is pressed from the rear face 21 side thereof. This can generate a fracture from the starting point region for cutting 8 acting as a start point, thereby accurately cutting the object 1 along the line along which the object should be cut.

Abstract: Adherence of contaminant residues or particles is suppressed, corrosion of exposed surfaces is substantially reduced or eliminated during the process of dicing a wafer by sawing. A fluoride-free aqueous composition comprising a dicarboxylic acid and/or salt thereof; a hydroxycarboxylic acid and/or salt thereof or amine group containing acid, a surfactant and deionized water is employed.

Abstract: Provided are a light emitting diode and a method for manufacturing the same. In the method, a semiconductor layer is formed, and a mask layer is formed on the semiconductor layer. Laser is irradiated onto a scribing region of the mask layer to divide the semiconductor layer into a plurality of light emitting diodes. The scribing region is etched, and then the mask layer is removed. The plurality of light emitting diodes are then separated from each other.

Abstract: A semiconductor device includes: a substrate having a main surface, a rear surface and four side surfaces; a semiconductor element formed on the main surface of the substrate; a notch formed in at least one bottom part of the side surfaces of the substrate; and a curved surface provided at an intersection of a side surface of the notch and the rear surface of the substrate.

Abstract: A manufacturing method for manufacturing a super-junction semiconductor device forms an oxide film and a nitride film on an n-type epitaxial layer exhibiting high resistance on an n-type semiconductor substrate exhibiting low resistance. The portion of the nitride film in the scribe region is left unremoved by patterning and an alignment marker is opened through the nitride film. After opening a trench pattern in the oxide film, trenches having a high aspect ratio are formed. The portion of the oxide film outside the scribe region is removed and a p-type epitaxial layer is buried in the trenches. The overgrown p-type epitaxial layer is polished with reference to the nitride film, the polished surface is finished by etching, and the n-type epitaxial layer surface is exposed.

Abstract: A semiconductor power component using flat conductor technology includes a vertical current path through a semiconductor power chip. The semiconductor power chip includes at least one large-area electrode on its top side and a large-area electrode on its rear side. The rear side electrode is surface-mounted on a flat conductor chip island of a flat conductor leadframe and the top side electrode is electrically connected to an internal flat conductor of the flat conductor leadframe via a connecting element. The connecting element includes a bonding strip extending from the top side electrode to the internal flat conductor and further includes, on the top side of the bonding strip, bonding wires extending from the top side electrode to the internal flat conductor.

Abstract: In an embodiment, a method of forming a lower electrode of a capacitor in a semiconductor memory device includes etching a mold oxide layer to have at a cylindrical structure, resulting in an electrode with increased surface area. The cylindrical structure may have more than one radius. This increased surface area results in an increased capacitance. An excessive etch phenomenon, which occurs because a sacrificial oxide layer is etched at a higher rate than the mold oxide layer, is avoided.

Abstract: A semiconductor device is made by creating a gap between semiconductor die on a wafer. An insulating material is deposited in the gap. A first portion of the insulating material is removed from a first side of the semiconductor wafer to form a first notch. The first notch is less than a thickness of the semiconductor die. A conductive material is deposited into the first notch to form a first portion of the conductive via within the gap. A second portion of the insulating material is removed from a second side of the semiconductor wafer to form a second notch. The second notch extends through the insulating material to the first notch. A conductive material is deposited into the second notch to form a second portion of the conductive via within the gap. The semiconductor wafer is singulated through the gap to separate the semiconductor die.

Abstract: A separation groove having a depth corresponding to a finished thickness of a semiconductor chip is formed in a boundary between a device region and an outer peripheral surplus region of a wafer, a protection tape whose adhesion is deteriorated by irradiation of ultraviolet rays is adhered on a surface, a portion of a back surface corresponding to the device region is ground, a thick reinforcing portion is formed on a portion corresponding to the outer peripheral surplus region. Next, only a portion of the protection tape adhered on the reinforcing portion is irradiated with ultraviolet rays, the reinforcing portion 8 is separated from the protection tape and is separated from the device region. A dicing frame is mounted on the back surface of the wafer having only the device region through a dicing tape, and the wafer is divided into semiconductor chips.

Abstract: A semiconductor device includes a substrate which is composed of a zinc oxide semiconductor having a hexagonal crystal structure and includes a first principal surface which is a polar plane; and four side surfaces which are adjacent to the first principal surface, the side surfaces being orthogonal to the principal surface and are at angles of 40 to 50 degrees to a base nonpolar plane orthogonal to the first principal surface; and a semiconductor layer provided on the first principal surface.

Abstract: A semiconductor device is made by disposing a plurality of semiconductor die on a carrier and creating a gap between each of the semiconductor die. A first insulating material is deposited in the gap. A portion of the first insulating material is removed. A conductive layer is formed over the semiconductor die. A conductive lining is conformally formed on the remaining portion of the first insulating material to form conductive via within the gap. The conductive vias can be tapered or vertical. The conductive via is electrically connected to a contact pad on the semiconductor die. A second insulating material is deposited in the gap over the conductive lining. A portion of the conductive via may extend outside the first and second insulating materials. The semiconductor die are singulated through the gap. The semiconductor die can be stacked and interconnected through the conductive vias.

Abstract: In a semiconductor wafer including a plurality of element forming regions formed on a front surface of a semiconductor substrate, a scribe line groove is formed along a periphery of the each of the element forming regions, and stoppers are located at an intersection of the scribe line groove, so as to block the scribe line groove.

Abstract: A method for manufacturing a semiconductor optical device comprises: forming a groove on a first semiconductor layer; forming a second semiconductor layer containing aluminum in the groove; forming a third semiconductor layer on the first semiconductor layer and the second semiconductor layer; forming an insulating layer on the third semiconductor layer covering the region opposite the second semiconductor layer; forming a stripe-shaped structure by etching the first semiconductor layer and the third semiconductor layer without exposing the second semiconductor layer, using the insulating layer as a mask; and burying the stripe-shaped structure with burying layers.

Abstract: A semiconductor device with a charge carrier compensation structure in a semiconductor body and to a method for its production. The semiconductor body includes drift zones of a first conduction type and charge compensation zones of a second conduction type complementing the first conduction type. The drift zones include a semiconductor material applied in epitaxial growth zones, wherein the epitaxial growth zones include an epitaxially grown semiconductor material which is non-doped to lightly doped. Towards the substrate, the epitaxial growth zones are provided with a first conduction type incorporated by ion implantation over the entire surface and with selectively introduced doping material zones of a second, complementary conduction type. Towards the front side, the epitaxial growth zones are provided with a second, complementary conduction type incorporated by ion implantation over the entire surface and with selectively introduced doping material zones of the first conduction type.

Abstract: A ZnO-based semiconductor light emitting element includes a ZnO-based semiconductor layer formed on a rectangular sapphire A-plane substrate having a principal surface lying in the A-plane {11-20}. The substrate has a thickness of 50 to 200 ?m and is surrounded by two parallel first side edges forming an angle in a range of 52.7° to 54.7° with respect to the m-axis orthogonal to the c-axis and two parallel second side edges orthogonal to the first side edges. The light emitting element is obtained by: forming, on a surface of the sapphire A-plane substrate opposite to the surface on which the ZnO-based semiconductor layer is formed, first scribed grooves forming an angle in a range of 52.7° to 54.7° with respect to the m-axis and second scribed grooves orthogonal to the first scribed grooves; and breaking the substrate along the first scribed grooves and then along the second scribed grooves.

Abstract: Semiconductor wafer sawing systems and methods are described in which a wafer may be secured in a sawing position having a surface exposed to incur sawing with at least a portion of the exposed wafer surface positioned below the center of gravity of the wafer such that prevailing force of gravity may be used to assist in the removal of contaminants from the wafer.

Abstract: The method of making a GaN single crystal substrate comprises a mask layer forming step of forming on a GaAs substrate 2 a mask layer 8 having a plurality of opening windows 10 disposed separate from each other; and an epitaxial layer growing step of growing on the mask layer 8 an epitaxial layer 12 made of GaN.

Abstract: A microelectronic device assembly with an integrated conductive shield is disclosed herein. The microelectronic device assembly includes a semiconductor substrate, an integrated circuit carried by the semiconductor substrate, a dielectric encapsulant encasing at least a portion of the semiconductor substrate. The microelectronic device assembly also includes a conductive shield in direct contact with at least a portion of the dielectric encapsulant and an interconnect extending through the semiconductor substrate and in direct contact with the conductive shield.

Abstract: For forming the separating lines, (5, 6, 7) which are produced in the functional layers (2, 3, 4) deposited on a transparent substrate (1) during manufacture of a photovoltaic module with series-connected cells (C1, C2, . . . ), there are used laser scanners (8) whose laser beam (14) produces in the field (17) scanned thereby a plurality of adjacent separating line sections (18) in the functional layer (2, 3, 4). The laser scanners (8) are then moved relative to the coated substrate (1) in the direction (Y) of the separating lines (5, 6, 7) by a distance corresponding at the most to the length (L) of the scanned field (17) to thereby form continuous separating lines (5, 6, 7) through mutually flush separating line sections (18).

Abstract: A chip structure according to the present invention is provided. A plurality of pedestals extends from the back surface of the chip structure. Each of the pedestals is located at a position away from the edge of the back surface for a non-zero distance so that the pedestals of an upper chip structure will not damage the bonding pads positioned on the edge of the active surface of a lower chip structure when the upper chip structure is stacked on the active surface of the lower chip structure with the pedestals.

Abstract: In a wafer dividing method of dividing a wafer into individual devices, the wafer being sectioned by streets to form the devices each made of a laminated body in which an insulating film and a function film are laminated on a front surface of a semiconductor substrate, the method includes a laser processing groove forming step for forming a laser processing groove on the laminated body so as to reach the semiconductor substrate by applying a laser beam formed with an annular spot to the laminated body side of the wafer along the street, the annular spot having an outer diameter larger than a width of a cutting blade and smaller than a width of the street; and a cutting step for allowing a cutting blade to cut the semiconductor substrate of the semiconductor wafer along the laser processing groove formed at the street.

Abstract: Illumination devices (7a) and (7b) which irradiate light having a wavelength of 1.1 ?m or less are arranged on a front surface and a rear surface of a cover (8) of a dicing device (1). After a wafer is placed on a dicing stage (3), when the wafer is diced by a blade (4a) attached to a spindle (5), light is irradiated on an entire surface of an upper surface (element forming surface) of the wafer by the illumination devices (7a) and (7b). At this time, an illuminance of light on the wafer is set at 70 lux or more and 2000 lux or less. By this means, during a dicing operation, an area to be a light-shielded area by the spindle (5) or the like is not present on the wafer.

Abstract: Crack stops for semiconductor devices, semiconductor devices, and methods of manufacturing semiconductor devices are disclosed. In one embodiment, a barrier structure for a semiconductor device includes a plurality of substantially V-shaped regions. Each of the plurality of substantially V-shaped regions is disposed adjacent another of the plurality of substantially V-shaped regions.

Abstract: Power wafer level chip scale package (CSP) and process of manufacture are enclosed. The power wafer level chip scale package includes all source, gate and drain electrodes located on one side of the device, which is convenient for mounting to a printed circuit board (PCB) with solder paste.

Abstract: Disclosed is a method for singulating semiconductor devices. The substrate has a plurality of scribe lines between the substrate units. A protecting film is provided having a patterned adhesive layer formed thereon corresponding to the scribe lines. The protecting film is attached and aligned to the substrate in a manner that the patterned adhesive layer adheres to the scribe lines without covering the substrate units. The substrate is cut by a laser beam aimed at the protecting film firstly and cut through the substrate along the peripheries of the scribe lines to singulate the substrate units. Therefore, the residue films of the protecting film on the substrate units can easily be removed. The contaminations of the substrate units by the sputtered particles and the melted protecting film during laser cutting can be eliminated. The shapes of the substrate units can be diverse.

Abstract: The present invention is related to a method for singulating chips from a stack of layers, such as the layers on a wafer or substrate. The stack of layers includes a front end of line (FEOL) layer upon the substrate layer, with the substrate layer having a first surface and a second surface. The FEOL is positioned on top of the first surface, and a back end of line (BEOL) layer is positioned on top of the FEOL. The method includes etching singulating trenches through the BEOL, through the FEOL and at least partially through the substrate layer, depositing a passivation layer on the stack provided with singulating trenches, whereby the sidewalls of the etched singulating trenches are at least partially passivated. Dicing, such as blade dicing, laser dicing or trench etch dicing is performed, releasing the chip from the stack of layers.

Abstract: Method of inhibiting metal diffusion arising from laser dicing is provided. The method includes dividing a wafer into at least one chip. The chip includes internal metallic features. The dividing deposits at least one metallic substance on the outer surface of the chip. After so dividing the chip, the method exposes the chip to a heated ambient environment having a given pressure (e.g., less than one atmosphere). The environment includes a chemical agent capable of bonding with the metallic substance. Additionally, wet chemical etch may be performed on the chip.

Abstract: A nitride semiconductor laser device is formed by growing a group III nitride semiconductor multilayer structure on a substrate. The group III nitride semiconductor multilayer structure has a laser resonator including an n-type semiconductor layer, a p-type semiconductor layer and a light emitting layer held between the n-type semiconductor layer and the p-type semiconductor layer. The laser resonator is arranged to be offset from the center with respect to a device width direction orthogonal to a resonator direction toward one side edge of the device. A wire bonding region having a width of not less than twice the diameter of an electrode wire to be bonded to the device is formed between the laser resonator and the other side edge of the device.

Abstract: A semiconductor element is formed on a first surface of the substrate. A resin layer is formed over a second surface of the substrate which is opposite to the first surface of the substrate and on a part of the side surface of the substrate. A step is formed on the side surface of the substrate. The width of the upper section of the substrate with a step is narrower than the lower section of the substrate with a step. Therefore, the substrate can also be a protrusion.

Abstract: A damaged layer repairing method repairs a damaged layer formed in a surface of a SiOCH film having a low dielectric constant film, containing silicon, carbon, oxygen and hydrogen and formed on a substrate through the elimination of carbon atoms by the decarbonizing effect of plasmas used in an etching process and an ashing process. CH3 radicals are produced through the thermal decomposition of C8H18O2 gas represented by a structural formula: (CH3)3COOH(CH3)3. CH3 radicals are brought into contact with the damaged layer in the SiOCH film and are made to bond to the damaged layer to repair the damaged layer.

Abstract: A laser beam is applied to an intersection area of each second street of a wafer by using a dicing apparatus to thereby form a first modified layer along the intersection area. Thereafter, the wafer is divided along each first street intersecting each second street at right angles to obtain a plurality of wafer strips. Thereafter, the laser beam is applied along the remaining area of each second street other than the intersection area to form a second modified layer along the remaining area of each second street. Thereafter, an external force is applied to each wafer strip in which the first and second modified layers have been formed along each second street, thereby dividing each wafer strip along each second street to obtain a plurality of devices.

Abstract: A method for making back-to-front electrical connections in a wafer level chip scale packaging process is disclosed. A wafer containing a plurality of semiconductor chips is mounted on a package substrate. Each semiconductor chip in the plurality includes one or more electrodes on an exposed back side. Scribe lines between two or more adjacent chips on the wafer are removed to form relatively wide gaps. A conductive material is applied to the back side of the semiconductor chips and in the gaps. The conductive material in the gaps between two or more of the chips is then cut through leaving conductive material on the back side and on side walls of the two or more chips. As a result, the conductive material provides an electrical connection from the electrode on the back side of the chip to the front side of the chip.

Abstract: A method to create piezoresistive sensing elements and electrostatic actuator elements on trench sidewalls is disclosed. P-type doped regions are formed in the upper surface of an n-type substrate. A trench is formed in the substrate (e.g. by DRIE process) intersecting with the doped regions and defining a portion of the substrate which is movable in the plane of the substrate relative to the rest of the substrate. Then diffusion of P-type dopant into the trench side-walls creates piezoresistive elements and electrode elements for electrostatic actuation. Owing to the intersection of two doped regions, there are good electrical paths between the electrical elements on the trench side-walls and the previously P-type doped portions on the wafer surface. The trench intersects with insulating elements, so that insulating elements mutually insulate adjacent electrical elements. P-n junctions between the electrical elements and the substrate insulate the electrical elements from the substrate.

Abstract: Method of inhibiting metal diffusion arising from laser dicing is provided. The method includes dividing a wafer into at least one chip. The chip includes internal metallic features. The dividing deposits at least one metallic substance on the outer surface of the chip. After so dividing the chip, the method exposes the chip to a heated ambient environment having a given pressure (e.g., less than one atmosphere). The environment includes a chemical agent capable of bonding with the metallic substance. Additionally, wet chemical etch may be performed on the chip.

Abstract: Provided is a method of isolating semiconductor laser diodes (LDs), the method including the steps of: preparing a substrate; forming a plurality of semiconductor LDs on the substrate, each semiconductor LD including an n-type semiconductor layer, an active layer, a p-type semiconductor layer, an n-electrode, a ridge portion, and a p-electrode, the ridge portion being formed by etching the p-type semiconductor layer such that a portion of the p-type semiconductor layer protrudes, the p-electrode being formed on the ridge portion; partially forming base cut lines on the surface of the substrate excluding the ridge portions; and isolating the semiconductor LDs into a bar shape along the base cut lines.

Abstract: A method divides a wafer into at least one chip. The chip includes internal metallic features. The dividing deposits at least one metallic substance on the outer surface of the chip. After so dividing the chip, the process exposes the chip to a heated ambient environment having a given pressure (e.g., less than one atmosphere). The environment comprises a chemical agent capable of bonding with the metallic substance. Additionally, wet chemical etch can be performed on the chip.

Abstract: One aspect of the invention pertains to a semiconductor die with rounded sidewall junction edge corners. Such rounding reduces stress accumulations at those corners. In other embodiments of the invention, the sharpness of other corners and edges in the die are reduced. For example, reducing the sharpness of the bottom edge corners formed by the intersection of a sidewall and the back surface of a die can further diminish stress accumulations. One embodiment pertains to a wafer carried on a wafer support, where the wafer includes a multiplicity of such dice. Another embodiment involves a semiconductor package containing such dice. Methods of fabricating the dice are also described.

Abstract: A method for manufacturing a semiconductor device has preparation step of preparing a semiconductor substrate having a plurality of semiconductor chip formation regions and a scribe region arranged between the plurality of the semiconductor chip formation regions and including a substrate cutting position, a semiconductor chip formation step of forming semiconductor chips having electrode pads on the plurality of semiconductor chip formation regions, a first insulation layer formation step of forming a first insulation layer on the semiconductor chips and the scribe region of the semiconductor substrate, a second insulation layer formation step of forming a second insulation layer on the first insulation layer except for a region corresponding to the substrate cutting position, and a cutting step of cutting the semiconductor substrate at the substrate cutting position.

Abstract: A semiconductor device with TSV and its fabrication method are revealed. The semiconductor device primarily comprises a chip and a flexible metal wire inside. A redistributed trace layer and a passivation layer are formed on the active surface of the chip. A through hole penetrates the chip from the active surface to the back surface, in which an insulation layer is disposed. The flexible metal wire has a first terminal and a second terminal where the first terminal is bonded to a redistributed pad of the redistributed trace layer and the second terminal passes through the through hole and protrudes from the back surface of the chip. Therefore, the flexible metal wire passing through the chip has two protruded integral terminals to achieve high stress resistance TSV with lower costs for good electrical connections of vertical stacking chips.

Abstract: A method for manufacturing a semiconductor device includes setting cut lines in parallel to a normal direction of a (1-100) plane orthogonal to the principal plane and in parallel to a normal direction of a (11-20) plane orthogonal to the (1-100) plane; forming, along the cut line parallel to the normal direction of the (1-100) plane, a trench from the principal plane of the semiconductor layer to a midpoint of a boundary plane between the semiconductor layer and the substrate; and cutting the wafer along the cut lines to divide the wafer into the plurality of semiconductor device where four side faces which are nonpolar planes orthogonal to the principal plane are set adjacent to the principal plane.

Abstract: Various embodiments are directed to providing an electronic device with an integrated thermal heat spreader. In one embodiment, an electronic device may comprise an integrated circuit fabricated on a substrate and a heat spreader integrated with the electronic device after fabrication of the integrated circuit. The heat spreader may comprise one or more layers of composite plating material including solid particles incorporated into a metal plating material. The composite plating material may be patterned to the substrate to define the heat spreader. Other embodiments are described and claimed.

Abstract: A semiconductor package is disclosed. One embodiment provides a semiconductor package singulated from a wafer includes a chip defining an active surface, a back side opposite the active surface, and peripheral sides extending between the active surface and the back side; a contact pad disposed on the active surface; and a metallization layer extending from the contact pad onto a portion of the peripheral sides of the chip.

Abstract: There are provided a semiconductor package comprising: a semiconductor substrate including an integrated circuit unit, and a crack-propagation preventing unit at least partially formed around a peripheral of the integrated circuit unit of the semiconductor substrate and filled with a heterogeneous material different from a material of the semiconductor substrate, and a method of fabricating the semiconductor package, comprising: at least partially forming a trench around the peripheral of the integrated circuit unit of the semiconductor substrate, and filling the trench with a heterogeneous material different from that of the semiconductor substrate. In accordance with the present invention, the structural and mechanical strength and durability of the semiconductor package, specifically, the wafer level semiconductor package, are improved and the reliability of the product is significantly improved.

Abstract: A method for the separation of multiple dies during semiconductor fabrication is described. On an upper surface of a semiconductor wafer containing multiple dies, metal layers are deposited everywhere except where a block of stop electroplating material exists. The stop electroplating material is obliterated, and a barrier layer is formed above the entire remaining structure. A sacrificial metal element is added above the barrier layer, and then the substrate is removed. After the semiconductor material between the individual dies is eradicated, any desired bonding pads and patterned circuitry are added to the semiconductor surface opposite the sacrificial metal element, a passivation layer is added to this surface, and then the sacrificial metal element is removed. Tape is added to the now exposed barrier layer, the passivation layer is removed, the resulting structure is flipped over, and the tape is expanded to separate the individual dies.

Abstract: A backgrinding machine 10 of a semiconductor wafer W includes: a table 13 set on the working plane of a mount 11; a multiple number of holding jigs 20 arranged via check tables 15 on table 13; a grinding machine 30 for performing a grinding process of the rear side of semiconductor wafer W held by holding jig 20; and a washing device 40 for ground semiconductor wafers W. Each holding jig 20 is constructed of a concave 22 depressed on the surface of a base plate 21, a multiple number of supporting projections 23 projectively arrayed on the bottom surface of concave 22, a deformable contact film 24, covering the concave 22, being supported by the multiple supporting projections 23, for detachably holding semiconductor wafer W in close contact with it; and an exhaust path 25 for conducting air from the concave 22 covered by contact film 24 to the outside.

Abstract: A laser processing method is provided, which, when cutting an object to be processed comprising a substrate and a multilayer part, formed on a front face of the substrate, including a functional device, can cut the multilayer part with a high precision in particular. In a state where a protective tape 22 is attached to the front face 16a of a multilayer part 16, a substrate 4 is irradiated with laser light L while using its rear face 4b as a laser light entrance surface, so as to form a modified region 7 within the substrate 4 along a line to cut, thereby generating a fracture 24 reaching the front face 4a of the substrate 4 from a front-side end part 7a of the modified region 7. Attaching an expandable tape to the rear face 4b of the substrate 4 and expanding it in the state where such a fracture 24 is generated can cut not only the substrate 4 but also the multilayer part 16 on the line to cut, i.e., interlayer insulating films 17a, 17b, with a favorable precision along the line to cut.

Abstract: Alignment patterns are formed in scribe regions of a semiconductor substrate, and through grooves for exposing the scribe regions are disposed in an insulating layer formed on the semiconductor substrate. Formation positions of wiring patterns are aligned based on the alignment patterns, and a metal layer is patterned and the wiring patterns are formed.

Abstract: A die pick-up apparatus and method using a die stage having an adherence surface, a suction window formed in the adherence surface and larger than a semiconductor die to be picked up, and a cover plate that slides along the adherence surface and opens and closes the suction window. When picking up the semiconductor die, the surface of the cover plate is caused to be closely contacted to a dicing sheet that is attached to the die so that the die is within the boundary of the upper surface of the cover plate that closes the suction window, and then the dicing sheet is sequentially peeled off as, while the die is being suctioned by a collet, the cover plate gradually slides to sequentially open the suction window and allow the dicing sheet to be suctioned into the opened suction window.