Abstract: A method of manufacturing an integrated circuit (IC) chip is provided. The method includes the following steps. First, a substrate is provided. The substrate is divided into an internal region and an external region by a die seal ring region. A plurality of circuit units is then formed in the internal region on the substrate. Thereafter, a dielectric layer is formed over the substrate, interconnects are formed in the dielectric layer within the internal region, and a plurality of bonding pad structures is formed in the dielectric layer within the external region. Finally, a cutting process is performed along a plurality of scribed lines on the substrate to form a plurality of chips. The bonding pad structures are exposed at the sides of each chip.

Abstract: A chip module having a chip with a flexible multilayer redistribution thin film attached thereto for connection to a substrate. The thin film acts as both a redistribution medium with multiple layers of redistribution metallurgy for chip power and signals and as a compliant medium to relieve stresses caused by thermal expansion mismatch between chip and substrate. Modules comprising chip and thin film may be fabricated at the chip or wafer level. The upper surface of the thin film has an array of pads matching the array of pads on the chip or wafer while the lower surface has pads matching those of the substrate. The multilayer thin film is first formed on a temporary substrate and then the chip is to the thin film before release from the temporary substrate. After release, the module is ready for mounting to the second level packaging substrate, such as a chip carrier or PCB. Where the multilayer thin film is formed directly on a wafer, the wafer is then diced to form the module.

Abstract: According to one exemplary embodiment, an extreme ultraviolet (EUV) pellicle for protecting a lithographic mask includes an aerogel film. The pellicle further includes a frame for mounting the aerogel film over the lithographic mask. The aerogel film causes the pellicle to have increased EUV light transmittance.

Abstract: A cutter blade movably in a radial direction of a wafer is pressed for biasing to an outer circumferential edge of the semiconductor wafer. Simultaneously, the pushing biasing force of the cutter blade is controlled constant with automatic regulation corresponding to a traveling speed variation of the cutter blade, so that effect of a centrifugal force that works at the time of rotating travel of the cutter blade may not vary a pushing biasing force of the cutter blade. As a result, a contact pressure of the cutter blade to the outer circumferential edge of the semiconductor wafer is maintained stable.

Abstract: A semiconductor device of the invention includes an integrated circuit formed on a semiconductor substrate having first and second surfaces and a notch region along the edges. The first surface includes electrical contact pads electrically connected with the integrated circuit. The first surface of the semiconductor substrate includes a top protective layer that has a surface portion extending beyond the edges of the semiconductor substrate. The second surface of the semiconductor substrate includes a bottom protective layer with electrical connectors. The surface portion of the top protective layer includes electrical contact pads that are electrically interconnected with electrical contact pad extensions. The electrical contact pad extensions are interconnected with electrical connectors via a backside electrical connector that overlaps the electrical contact pad extensions forming a lap connection. Methods for constructing such devices and connections are also disclosed.

Abstract: A method for manufacturing a SiC semiconductor device includes: forming an impurity layer in a SiC layer; and forming an oxide film on the SiC layer. The forming the impurity layer includes: implanting an impurity ion in the SiC layer; forming a carbon layer on the SiC layer; heating the SiC layer for activating the implanted impurity in the SiC layer covered with the carbon layer; and removing the carbon layer from the SiC layer. The forming the carbon layer includes: coating a resist on the SiC layer; and heating the resist for evaporating organic matter in the resist so that the resist is carbonized. The forming the oxide film is performed after the removing the carbon layer.

Abstract: A laser processing method for a gallium arsenide wafer of radiating a laser beam along streets formed in lattice on a surface of a gallium arsenide substrate, and cutting-off the gallium arsenide wafer along the streets includes a wafer supporting step for sticking a rear surface of the gallium arsenide substrate on a protective member, a debris shielding coating step for coating the surface of the gallium arsenide substrate with a debris shielding film, a laser-processed trench forming step for radiating a laser beam along the streets from the debris shielding film side to the gallium arsenide substrate, thereby forming laser-processed trenches each not reaching the rear surface, and a cutting-off step for radiating the laser beam along the laser-processed trenches to the gallium arsenide substrate, thereby forming cutting-off trenches each reaching the rear surface.

Abstract: A method of manufacturing a compound semiconductor device comprises forming a scribed groove extending from an edge of a major surface of a laminated body to an internal region on the first major surface. The laminated body has the first major surface and a second major surface and is formed by crystal growth of a compound semiconductor multilayer film on a substrate. The scribed groove is shallow at the edge and deep in the internal region. The method may further comprise separating the laminated body into first and second portions separated by a separation plane including the scribed groove by applying load to the second major surface of the laminated body.

Abstract: In a semiconductor wafer including a plurality of element forming regions formed on a front surface of a semiconductor substrate, a scribe line groove is formed along a periphery of the each of the element forming regions, and stoppers are located at an intersection of the scribe line groove, so as to block the scribe line groove.

Abstract: A compound semiconductor device includes a laminated body including a crystal substrate and a compound semiconductor multilayer film. The laminated body has a major surface, a first side face, a second side face, a third side face, and a fourth side face. The first and the second side faces are opposed to each other, substantially perpendicular to the major surface of the laminated body, made of cleaved surfaces. The third and the fourth side faces are perpendicular to the major surface and to the first and the second side faces, opposed to each other, and made of uncleaved surfaces. A groove is provided on the third side face, and the groove has a depth varied with position as viewed from the major surface, and has ends not reaching the first and second side face.

Abstract: A MEMS device (100) is provided that includes a handle layer (108) having a sidewall (138), a cap (132) overlying said handle layer (108), said cap (132) having a sidewall (138), and a conductive material (136) disposed on at least a portion of said sidewall of said cap (138) and said sidewall of said handle layer (138) to thereby electrically couple said handle layer (108) to said cap (132). A wafer-level method for manufacturing the MEMS device from a substrate (300) comprising a handle layer (108) and a cap (132) overlying the handle layer (108) is also provided. The method includes making a first cut through the cap (132) and at least a portion of the substrate (300) to form a first sidewall (138), and depositing a conductive material (136) onto the first sidewall (138) to electrically couple the cap (132) to the substrate (300).

Abstract: A plurality of device patterns constituting part of an electronic circuit are formed over the surface of a substrate. A symbol pattern to be used for an identification sign is formed in the same layer as the device patterns. A width of the device pattern is within a pattern width range on a design rule. The symbol pattern is formed by a plurality of isolated element patterns. The element pattern is either a linear pattern or a dot pattern. A width of the element pattern is equal to or larger than 0.8 time a lower limit value of the pattern width range and equal to or smaller than 1.2 times an upper limit value of the pattern width range.

Abstract: One aspect relates to a method for singulating semiconductor wafers to form semiconductor chips. A semiconductor wafer is provided with semiconductor chip positions arranged in rows and columns, rectilinear separating tracks being arranged between the positions. Crystallographic strains are induced into the region of the separating tracks. This is followed by a laser ablation along the separating tracks, the semiconductor wafer being separated into individual semiconductor chips.

Abstract: A laser processing method is provided, which, when cutting a substrate formed with a laminate part including a plurality of functional devices into a plurality of chips, each chip including at least one of the functional devices, can cut the laminate part with a high precision together with the substrate. In this laser processing method, modified regions differing from each other in terms of easiness to cause the substrate 4 to fracture are formed along respective lines to cut 5a to 5d. Therefore, when an expandable tape is attached to the rear face of a substrate 4 and expanded, an object to be processed 1 is cut stepwise into a plurality of chips. Such stepwise cutting allows uniform tensile stresses to act on respective parts extending along the lines to cut 5a to 5d, whereby interlayer insulating films on the lines to cut 5a to 5d are cut with a high precision together with the substrate 4.

Abstract: Materials, and methods that use such materials, that are useful for forming chip stacks, chip and wafer bonding and wafer thinning are disclosed. Such methods and materials provide strong bonds while also being readily removed with little or no residues.

Abstract: Methods for singulating surface-mountable semiconductor devices and for fitting external contact areas to the devices are described herein. Semiconductor device components are applied to a metallic carrier in rows and columns in corresponding semiconductor device positions of the metallic carrier. Thereafter, a plurality of components, situated in the device positions, is embedded into a plastic housing composition, thereby producing a composite board. The composite board is subsequently separated into individual semiconductor devices by laser ablation, the semiconductor devices being inscribed on their top sides via the laser technique. The top sides with the inscription can then be adhesively bonded to an adhesive film, so that the undersides of the devices can be uncovered while maintaining the semiconductor device positions.

Abstract: A semiconductor wafer that includes a plurality of groups of active devices or circuits on a first side of the wafer and a patterned electrical contact on the backside of the wafer. Each group consisting of an active device or circuit is intended to be diced into a discrete chip. The backside of the wafer includes a metal layer patterned into discrete spaced-apart deposits that form an electrical contact to the semiconductor and the respective group of active devices. The deposits are not contiguously or laterally connected to each other and function to protect the metal layer from peeling or detaching from the wafer during dicing of the semiconductor wafer into chips.

Abstract: A wafer is provided and a front scribe line pattern is defined on a front surface of the wafer. A back scribe line pattern corresponding to the front scribe line pattern is defined on a back surface of the wafer. Then the wafer is attached to an extendable film and a wafer breaking process is performed to form a plurality of dies by virtue by extending the extendable film.

Abstract: A feature in a layer is provided. A photoresist layer is formed over the layer. The photoresist layer is patterned to form photoresist features with photoresist sidewalls, where the photoresist features have a first critical dimension. A conformal layer is deposited over the sidewalls of the photoresist features to reduce the critical dimensions of the photoresist features. Features are etched into the layer, wherein the layer features have a second critical dimension, which is less than the first critical dimension.

Abstract: A semiconductor device according to the present invention includes a semiconductor substrate, which comprises a first surface on which an electrode pad is formed, and a second surface arranged at an opposite side of the first surface; an external terminal formed on the first surface of the semiconductor substrate and is electrically connected to the electrode pad; and a sealing resin which seals the first surface so that a surface of the external terminal is exposed. An outer edge of the second surface has a chamfered portion, a surface of which is inclined by substantially 45 degrees from the second surface.

Abstract: A packaging wafer having a plurality of cavities on an upper surface thereof is provided. A plurality of trenches is formed between the cavities, wherein the packaging wafer has a thickness greater than a depth of the trenches. The packaging wafer is bonded to an element wafer and a hermetical window is formed from each cavity. Then, a cutting process is performed and an unbound part of the packaging wafer is removed. Therefore, a wafer level package is formed. Finally, the wafer level package is divided into a plurality of individual packages.

Abstract: A plurality of MEMS structures is formed on a wafer. The wafer is mounted on a dicing frame assembly having a dicing frame and a dicing tape attached to the dicing frame. A protective layer is applied to cover the entire surface of the wafer or may be limited to the portion of the surface of the wafer that includes the MEMS structures by any suitable means of coating techniques to protect the MEMS structures during dicing operation. The protective layer base material to be provided on the wafer may include linear carbon chain molecules containing 12-18 carbon atoms. The dicing operation is performed to divide the wafer into individual die. The protective layer is removed by any suitable process including decomposition, vaporized, sublimation or the like. For example, the protective layer may be evaporated through the application of heat after the die attachment process is completed. The heat application may be part of the cure cycle required for die bonding or may be a separate operation.

Abstract: A method of singulating a microelectronic wafer. The method comprises: providing a microelectronic wafer; focusing a laser beam in an interior region of the wafer from the backside of the wafer to form a modified region extending along the severance lines of the wafer dividing the wafer IC chips, the modified region further extending from an undersurface of the active surface and ending at a predetermined depth with respect to the backside. The modified region comprises a plurality of modified sites of the wafer molten by the laser and resolidified. The method further includes reducing a thickness of the wafer in a direction from the backside toward the active surface by a reduction amount equal to at least the predetermined depth; and dividing the wafer into individual IC chips along the severance lines at the modified sites.

Abstract: The present invention relates to method for producing a group III nitride based compound semiconductor device, including separating the device into individual chips by means of a dicing blade. A portion of an epitaxial layer where a dicing blade is to be positioned is partially or totally removed through etching, to thereby form a trench. An insulating film is formed on the bottom and on the side surfaces of the trench. A wafer is diced into chips in such a manner that the bottom of the trench is removed by means of the dicing blade without completely removing the side surfaces of the insulating film. The insulting film is formed on the side surfaces of the trench such that the film covers a p-type layer to an n-type layer included in group III nitride based compound semiconductor layers so as to prevent short circuit between the p-type layer and the n-type layer.

Abstract: The present invention provides a separating process of a semiconductor device package of wafer level package. The method comprises a step of etching a substrate to form recesses. Then a buffer layer is formed on the first surface of the substrate, wherein the buffer layer is filled with the corresponding recesses to form infillings on adjacent the semiconductor device package. Dicing the wafer into individual package along substantial center of said infillings, the step may avoid the roughness on the edge of each die and also decrease the cost of the separating process.

Abstract: A method of separating an IC. The method includes dicing a semiconductor wafer. The semiconductor wafer includes multiple ICs. The diced wafer is secured to a stretchable substrate. The stretchable substrate can be stretched so as to form corresponding spaces between each of the ICs. The corresponding spaces are filled with a support material. A system for separating ICs on a semiconductor wafer is also disclosed.

Abstract: The present invention discloses a high-power-laser chip-fabrication apparatus and a method thereof, wherein a substrate is fixed on a working table; a light-guide device is used to direct a high power laser to a scribed line on the substrate; a control device is used to position the working table and the high power laser so that the high power laser can be precisely aimed at the scribed line to be cut; a video device is used to observe whether the high power has been aimed at the scribed line; an object lens is used to adjust the focal length by which the high power laser is to be aimed at one of the scribed lines; the length of the scribed line to be cut and the spacing between two scribed lines are input; and then, the cutting is performed. The present invention can cut the substrate quickly and precisely into multiple discrete chips and accelerate the fabrication process.

Abstract: A method of expanding the contact pitch for un-diced chips in an array by pre-slicing the array in a first direction, attaching a lead frame to the chips' contacts, and then slicing the array and attached lead frame in the second direction. The lead frame has leads mechanically connected one another such that slicing the frame in the second direction along the mechanical connections separates the leads. Each lead has a first terminal which is conductively attached to a chip contact and a second terminal extending beyond the boundaries of the chip to which the first terminal is attached. In this manner, the contact pitch is effectively expanded to the terminal pitch of the leads.

Abstract: A pre-process before cutting a wafer is described. The wafer includes a plurality of scribe lines and a plurality of dies defined by the scribe lines, and a material layer covers the wafer. A pre-processing step is performed to remove the material layer on the scribe lines close to the corner regions of the dies. Removing the material layer at the corner regions before cutting the wafer is able to preserve the integrity of the corner regions of the cut dies.

Abstract: A method for forming a MEMS device is disclosed, where a final release step is performed just prior to a wafer bonding step to protect the MEMS device from contamination, physical contact, or other deleterious external events. Without additional changes to the MEMS structure between release and wafer bonding and singulation, except for an optional stiction treatment, the MEMS device is best protected and overall process flow is improved. The method is applicable to the production of any MEMS device and is particularly beneficial in the making of fragile micromirrors.

Abstract: A method for dicing a semiconductor wafer includes the steps of: forming grooves in an integrated circuit layer of the semiconductor wafer; forming a photoresist layer on the integrated circuit layer; forming V-shaped first notches, each of which is further indented from the integrated circuit layer; thinning the substrate; attaching a blue tape to the integrated circuit layer; forming V-shaped second notches, each of which is indented from the thinned substrate and each of which is registered with a respective one of the first notches such that the first and second notches cooperatively define imaginary breaking lines, respectively; and pressing the blue tape at positions that are aligned with the imaginary breaking lines, respectively.

Abstract: The invention provides methods and systems for sawing and singulating individual semiconductor devices manufactured on a wafer. Pursuant to the systems and methods of the invention, a wafer is secured for sawing and is then presented to a saw blade. At least one parameter associated with sawing the wafer is monitored and the rate of presentation of the wafer to the saw blade is dynamically controlled responsive to the one or more monitored parameters. According to preferred embodiments of the invention, the saw blade voltage or spindle current is a monitored parameter. Additional monitored parameters include horizontal and vertical forces acting upon the wafer and deflection of the saw blade. In preferred embodiments of the invention, monitored sawing process parameters are also used to establish control limits, which are then used to implement real time process controls.

Abstract: A semiconductor chip is formed by dividing a semiconductor wafer by use of the laser dicing technique. The semiconductor chip has a laser dicing region on the side surface thereof. A dummy wiring layer is formed along the laser dicing region on the surface layer of the laser dicing region. A laser beam is applied to the dummy wiring layer to divide the semiconductor wafer.