Abstract: A method is provided for fabricating a semiconductor device that includes providing a semiconductor substrate having a first region and a second region, forming a high-k dielectric layer over the substrate, forming a silicon layer over the high-k dielectric layer, forming a hard mask layer over the silicon layer, patterning the hard mask layer, silicon layer, and high-k dielectric layer to form first and second gate structures over the first and second regions, respectively, forming a contact etch stop layer (CESL) over the first and second gate structures, modifying a profile of the CESL by an etching process, forming an inter-layer dielectric (ILD) over the modified CESL, performing a chemical mechanical polishing (CMP) on the ILD to expose the silicon layer of the first and second gate structures, respectively, and removing the silicon layer from the first and second gate structures, respectively, and replacing it with metal gate structures.

Abstract: In polishing of a to-be-polished surface in the production of a semiconductor integrated circuit device, a flat surface of an insulating layer having an embedded metal interconnect can be obtained. Further, a semiconductor integrated circuit device having a highly planarized multilayer structure can be obtained. Provided is a polishing composition which is a chemical mechanical polishing composition for polishing a to-be-polished surface of a semiconductor integrated circuit device, contains one or more oxidizing agents selected from the group consisting of hydrogen peroxide, ammonium persulfate and potassium persulfate, an abrasive grain, an alicyclic resin acid, a basic compound and inorganic acid, and has a pH ranging from 8 to 12.

Abstract: The present invention provides a final polishing method for a silicon single crystal wafer that performs final polishing with a polishing rate being set to 10 nm/min or below at a final polishing step as a final step among a plurality of polishing steps for polishing the silicon single crystal wafer with a polishing slurry being interposed between the silicon single crystal wafer and a polishing pad, and a silicon single crystal wafer subjected to final polishing by this method. Hereby, there can be provided the final polishing method that can obtain a silicon single crystal wafer with less PIDs (Polishing Induced Defects) and the silicon single crystal wafer subjected to final polishing by this method.

Abstract: Provided is a method of fabricating an integrated circuit semiconductor device. The method may include forming a plurality of gate patterns spaced apart from each other on a semiconductor substrate, the plurality of gate patterns including gate electrodes and gate capping patterns. After an interlayer insulating layer is formed to insulate the gate patterns, the interlayer insulating layer and the gate capping patterns may be planarized by etching until top surfaces of the gate electrodes are exposed. Gate metal silicide layers may be selectively formed on the gate electrodes.

Abstract: A dielectric film, a method of manufacturing a dielectric film and a method of forming an air-gap. A method of manufacturing a low-k dielectric film may include introducing TMS and 3,3-dimethyl-1-butene into a plasma deposition reactor, polymerizing TMS and 3,3-dimethyl-1-butene using plasma generated in a reactor to deposit an insulation film over a substrate disposed in a reactor and/or subjecting a deposited insulation film to heat treatment concurrently with an inductively coupled plasma (ICP) process. A dielectric film may have a dielectric constant up to approximately 3. A method of forming an air-gap may include depositing a first insulation film over a surface of a patterned substrate, depositing a decahydronaphthalene layer over a portion of a first insulation film, subjecting a patterned substrate to a polishing process, forming a second insulation film, and/or subjecting a second insulation film to heat treatment concurrently with an ICP process.

Abstract: A colloidal dispersion for chemical mechanical polishing comprising: (a) an abrasive component; and (b) from about 0.05% to about 10% by weight of the abrasive component, a water-soluble amphoteric polymer comprising at least one macromolecular chain B and a part A bonded to a single end of the at least one macromolecular chain B, wherein the macromolecular chain B is derived from one or more ethylenically unsaturated monomers having quaternary ammonium groups or inium groups, and wherein the part A is a polymeric or nonpolymeric group comprising at least one anionic group; wherein the dispersion has a pH of between about 1.5 and about 6. The colloidal dispersion is capable of polishing a substrate comprising silicon nitride and silicon oxide with a reverse selectivity ratio of at least about 27, typically at least 50 the reverse selectivity ratio being the ratio of the rate of removal of the silicon nitride to the rate of removal of the silicon oxide.

Abstract: The invention concerns a method of producing a mixed substrate, that is to say a substrate comprising at least one block of material different from the material of the substrate, the method comprising the following successive steps: formation of a cavity in a substrate of first material, and from one of its faces, the formation of the cavity being carried out so as to leave at least part of the first material projecting from the bottom of the cavity, formation of the block by means of a reaction, initiated from the walls of the cavity, between the first material and at least one chemical element contributed in order to obtain a second material filling the cavity, the formation of the block being carried out so as to obtain, from the part of the first material projecting, a protrusion of second material projecting on said face of the substrate.

Abstract: The present invention discloses a method for manufacturing thin film structure, which comprises the following steps: providing a substrate having a first recess and a second recess formed therein with the first recess being deeper than the second recess; depositing a first material layer and a second material layer of different thicknesses successively on the substrate; and grinding the substrate so that a flat upper surface is formed and the first material layer and the second material layer are remained in the first recess while only the first material layer is remained in the second recess. The present invention also discloses a method for manufacturing fringe field switching type liquid crystal display array substrate. With the present invention, it is possible to make the upper surface flat while forming patterns on two layers of thin films respectively by using a single mask.

Abstract: The invention provides a chemical-mechanical polishing composition for polishing a substrate. The polishing composition comprises silica, a compound selected from the group consisting of an amine-substituted silane, a tetraalkylammonium salt, a tetraalkylphosphonium salt, and an imidazolium salt, a carboxylic acid having seven or more carbon atoms, an oxidizing agent that oxidizes a metal, and water. The invention further provides a method of chemically-mechanically polishing a substrate with the aforementioned polishing composition.

Abstract: A chemical mechanical polishing aqueous dispersion is used to polish a polishing target that includes an interconnect layer that contains tungsten. The chemical mechanical polishing aqueous dispersion includes: (A) a cationic water-soluble polymer; (B) an iron (III) compound; and (C) colloidal silica particles. The content (MA) (mass %) of the cationic water-soluble polymer (A) and the content (MB) (mass %) of the iron (III) compound (B) satisfy the relationship “MA/MB=0.004 to 0.1”. The chemical mechanical polishing aqueous dispersion has a pH of 1 to 3.

Abstract: In methods of forming a phase-change material layer pattern, an insulation layer having a recessed portion may be formed on a substrate, and a phase-change material layer may be formed on the insulation layer to fill the recessed portion. A first polishing process may be performed on the phase-change material layer using a first slurry composition to partially remove the phase-change material layer, the first slurry composition having a first polishing selectivity between the insulation layer and the phase-change material layer. A second polishing process may be performed on the phase-change material layer using a second slurry composition to form a phase-change material layer pattern in the recessed portion, the second slurry composition having a second polishing selectivity substantially lower than the first polishing selectivity.

Abstract: Disclosed is CMP slurry, which includes a pyridine-based compound including at least two pyridinyl groups, and minimizes the occurrence of dishing and erosion of a wiring line.

Abstract: A composition and associated method for chemical mechanical planarization (or other polishing) are described. The composition contains a boron surface-modified abrasive, a nitro-substituted sulfonic acid compound, a per-compound oxidizing agent, and water. The composition affords high removal rates for barrier layer materials in metal CMP processes. The composition is particularly useful in conjunction with the associated method for metal CMP applications (e.g., step 2 copper CMP processes).

Abstract: The present invention provides a method for polishing an aluminum nitride substrate. The method comprises abrading a surface of the aluminum nitride substrate with a basic, aqueous polishing composition, which comprises an abrasive (e.g., colloidal silica), an oxidizing agent (e.g., hydrogen peroxide), and an aqueous carrier. The methods of the invention provide for substantially improved polishing rates relative to conventional methods that do not utilize an oxidizing agent in the polishing slurry.

Abstract: A biosensor chip (100) for detecting biological particles, the biosensor chip (100) comprising a sensor active region (101) being sensitive for the biological particles and being arranged in a Back End of the Line portion (102) of the biosensor chip (100).

Abstract: A semiconductor polishing compound comprising cerium oxide abrasive grains, water and an additive, wherein the additive is a water-soluble organic polymer such as ammonium polyacrylate or an anionic surfactant, the pH at 25° C. is from 3.5 to 6, and the concentration of the additive is from 0.01 to 0.5% based on the total mass of the polishing compound. This polishing compound simultaneously has dispersion stability, excellent scratch characteristics and excellent polishing planarization characteristics. In particular, this polishing compound provides excellent planarization characteristics having dishing fluctuation reduced, when used for polishing a semiconductor substrate having a silicon nitride film 3 and a silicon oxide film 2 formed on a silicon substrate 1. Further, the time for polishing a pattern wafer can be shortened by using this polishing compound.

Abstract: A method for producing a semiconductor wafer. The method includes placing the semiconductor wafer in a cutout in a carrier. Both sides of the semiconductor wafer are polished between an upper and a lower polishing plate with a polishing agent until the thickness of the center of the semiconductor wafer is less than the thickness of the carrier and from 10 ?m to 30 ?m of semiconductor wafer material is removed. The polishing agent contains 0.1 to 0.4% by weight of SiO2 and 0.1 to 0.9% by weight of an alkaline component.

Abstract: A region corresponding to a convex pattern of a first insulating film deposited above a semiconductor substrate having a plurality of convex patterns is removed by anisotropic etching up to a top surface of the convex patterns, the convex patterns are exposed, and a convex portion of the first insulating film is formed. Subsequently, a second insulating film is deposited above the semiconductor substrate, the convex portion of the first insulating film and the second insulating film that covers the convex portion are removed to a surface height of the second insulating film at least on the convex patterns by a CMP process to perform planarization.

Abstract: A method for performing a chemical-mechanical polishing (CMP) is provided. The method includes processing a semiconductor substrate to form a dummy gate structure on the substrate, to form a hard mask on the dummy gate structure, and to form a contact etch stop layer (CESL) and an interlayer dielectric (ILD) layer on the hard mask, performing a first CMP process with a first slurry to modify a non-planar topography of the ILD layer, performing a second CMP process with a second slurry to remove the hard mask, and performing a third CMP process with a third slurry to remove an interfacial layer that forms between the dummy gate and hard mask during semiconductor processing.

Abstract: Provided is a polishing agent composition for chemical mechanical polishing, which is used for polishing a surface of a semiconductor integrated circuit device to be polished. The polishing agent composition contains silica particles, one or more oxidizing agents selected from the group consisting of hydrogen peroxide, ammonium persulfate and potassium persulfate, a compound represented by formula (1), pullulan, one or more acids selected from the group consisting of nitric acid, sulfuric acid and carboxylic acids, and water, and has a pH within the range of 1-5. According to the present invention, a flat surface of an insulating layer having a buried metal interconnect can be attained in polishing of a surface to be polished during production of a semiconductor integrated circuit device. Further, a semiconductor integrated circuit device having a highly planarized multilayer structure can be obtained.

Abstract: Epitaxially coated silicon wafers, are coated individually in an epitaxy reactor by placing a wafer on a susceptor, pretreating under a hydrogen atmosphere, in and then with addition of an etching medium, and coating epitaxially on a polished front side, wherein an etching treatment of the susceptor is effected after a specific number of epitaxial coatings, and the susceptor is then hydrophilized. Silicon wafer produced thereby have a maximum local flatness value SFQRmax of 0.01 ?m to 0.035 ?m relative to at least 99% of the partial regions of an area grid of measurement windows having a size of 26×8 mm2 on the front side of the silicon wafer with an edge exclusion of 2 mm.

Abstract: A wafer manufacturing method includes after flattening both upper and lower surfaces of a wafer sliced from a single crystal ingot, processing the wafer having damage on both surfaces caused by the flattening, so as to obtain desired damage at least on the lower surface of the wafer, the desired damage having a damage depth ranging from 5 nm-10 ?m; forming a polysilicon layer at least on the lower surface of the wafer while the damage on the lower surface of the wafer remains; single-wafer etching the upper surface of the wafer; and final polishing the upper surface of the wafer to have a mirrored surface, after the single-wafer etching.

Abstract: Exposed copper regions on a semiconductor substrate can be etched by a wet etching solution comprising (i) one or more complexing agents selected from the group consisting of bidentate, tridentate, and quadridentate complexing agents; and (ii) an oxidizer, at a pH of between about 5 and 12. In many embodiments, the etching is substantially isotropic and occurs without visible formation of insoluble species on the surface of copper. The etching is useful in a number of processes in semiconductor fabrication, including for partial or complete removal of copper overburden, for planarization of copper surfaces, and for forming recesses in copper-filled damascene features. Examples of suitable etching solutions include solutions comprising a diamine (e.g., ethylenediamine) and/or a triamine (e.g., diethylenetriamine) as bidentate and tridentate complexing agents respectively and hydrogen peroxide as an oxidizer.

Abstract: The invention relates to a CMP polishing slurry containing cerium oxide particles, a dispersing agent, a water-soluble polymer and water, wherein the water-soluble polymer includes a polymer obtained by polymerizing a monomer including at least one of a carboxylic acid having an unsaturated double bond and a salt thereof, using a reducing inorganic acid salt and oxygen as a redox polymerization initiator; an additive liquid for CMP polishing slurry; and substrate-polishing processes using the same. This makes it possible to polish a silicon oxide film effectively in a CMP technique for planarizing an interlayer dielectric, a BPSG film or a shallow trench isolating insulated film.

Abstract: The present invention relates to a CMP slurry composition for polishing a copper film in a semiconductor device fabricating process. The CMP composition for polishing a substrate comprising copper comprises zeolite, an oxidizer and a complexing agent and a content of the complexing agent is 0.01˜0.8 weight % with respect to an entire weight of the polishing composition.

Abstract: A semiconductor chip having a thickness of 130 micrometers or less includes a mechanically ground bottom surface corresponding to a central circuit area, and a polished bottom surface corresponding to a peripheral scribe area. The mechanically ground bottom surface prevents heavy metals attached onto the bottom surface of the wafer from diffusing toward the source/drain regions of the semiconductor substrate and thereby from degrading the transistor characteristics.

Abstract: A polishing compound for chemical mechanical polishing of a substrate, which comprises (A) abrasive grains, (B) an aqueous medium, (C) tartaric acid, (D) trishydroxymethylaminomethane and (E) at least one member selected from the group consisting of malonic acid and maleic acid, and more preferably, which further contains a compound having a function to form a protective film on the wiring metal surface to prevent dishing at the wiring metal portion, such as benzotriazole. By use of this polishing compound, the copper wirings on the surface of a semiconductor integrated circuit board can be polished at a high removal rate while suppressing formation of scars as defects in a polishing step.

Abstract: A silicon nitride polishing liquid for chemical mechanical polishing of a body to be polished in a planarization process for manufacturing of a semiconductor integrated circuit, the body to be polished including at least a first layer containing silicon nitride and a second layer containing at least one silicon-including material selected from the group consisting of polysilicon, modified polysilicon, silicon oxide, silicon carbide, and silicon oxycarbide, the silicon nitride polishing liquid having a pH of 2.5 to 5.0, and including (a) colloidal silica, (b) an organic acid that has at least one sulfonic acid group or phosphonic acid group in the molecular structure thereof and functions as a polishing accelerator for silicon nitride, and (c) water.

Abstract: The invention relates to a method for producing a MEMS/NEMS structure from a substrate made in a monocrystalline semiconductor material, the structure comprising a flexible mechanical element connected to the substrate by at least one anchoring zone, the method comprising the following steps: the formation of a protection layer on one face of the substrate, the protection layer being made in a monocrystalline material different from the material of the substrate, etching of the protection layer and the substrate in order to produce at least one cavity, the etching being done so as to leave an overhang made in the material of the protection layer on the edges of the cavity, filling in of the cavity with an electrically insulating material in order to obtain an insulating anchoring portion, epitaxy of a semiconductor material from the protection layer and the electrically insulating material in order to obtain a layer designed to produce the flexible mechanical element, liberation of the flexible mechanical

Abstract: To provide a wetting agent for semiconductors and a polishing composition whereby the wettability of a semiconductor substrate surface can be improved, and microdefects such as particle attachments can be remarkably reduced. A wetting agent for semiconductors, comprising a water soluble polymer compound having a low viscosity and water, and a polishing composition. A 0.3 wt % aqueous solution of the water soluble polymer compound has a viscosity of less than 10 mPa·s at 25° C.

Abstract: The wafer bevel etching apparatus of the present invention includes a wafer-protecting mask to cover parts of a wafer. A central region and a wafer bevel region surrounding the central region are defined on the wafer. The wafer-protecting mask includes a center sheltering region and at least one wafer bevel sheltering region. The center sheltering region can completely shelter the central region of the wafer, and the wafer bevel sheltering region extends from the outside edge of the center sheltering region, shelters parts of the wafer bevel region, and exposes the other parts of the wafer bevel region.

Abstract: There is provided an aqueous dispersion for chemical mechanical polishing that comprises abrasives comprising: (A) 100 parts by weight of inorganic particles comprising ceria, (B) 5 to 100 parts by weight of cationic organic polymer particles, and (C) 5 to 120 parts by weight of anionic water-soluble compound. The aqueous dispersion for chemical mechanical polishing is preferably produced by a method comprising a step of adding a second liquid comprising (C) 5 to 30 wt % of anionic water-soluble compound to a first liquid comprising (A) 0.1 to 10 wt % of inorganic particles comprising ceria and (B) 5 to 100 parts by weight of cationic organic polymer particles based on 100 parts by weight of the inorganic particles (A).

Abstract: A method of manufacturing a semiconductor device has forming a first insulating film on a low dielectric constant film; etching the first insulating film and the low dielectric constant film to form a trench in a region in which the wiring layer is to be formed; forming a first barrier metal film in the trench and on the first insulating film; forming a film of a conductive material on the first barrier metal film, thereby burying the conductive material in the trench to form a conductor layer; polishing and planarizing the conductor layer, the first barrier metal film and the first insulating film by CMP using a slurry, wherein the first insulating film is not completely removed; and etching the remained first insulating film after the planarization by the CMP manner.

Abstract: A chemical mechanical polishing aqueous dispersion according to the invention includes (A) 0.1 to 4 mass % of colloidal silica having an average particle diameter of 10 to 100 nm, and (B) 0.1 to 3 mass % of at least one ammonium salt selected from ammonium phosphate, diammonium phosphate, and ammonium hydrogen sulfate, the chemical mechanical polishing aqueous dispersion having a mass ratio (A)/(B) of the component (A) to the component (B) of 1 to 3 and a pH of 4 to 5 and being able to simultaneously polish at least two films that form a polishing target surface and are selected from a polysilicon film, a silicon nitride film, and a silicon oxide film.

Abstract: A semiconductor chip, semiconductor package including the same, and a method of manufacturing the semiconductor chip and semiconductor package to block up electrical contacts between bonding wires and the semiconductor chip by providing insulation over the edge of the semiconductor chip.

Abstract: A silicon oxynitride film is formed on a target substrate by CVD, in a process field configured to be selectively supplied with a first process gas containing a chlorosilane family gas, a second process gas containing an oxidizing gas, and a third process gas containing a nitriding gas. This method alternately includes first to sixth steps. The first, third, and fifth steps perform supply of the first, second, and third process gases, respectively, while stopping supply of the other two process gases. Each of the second, fourth, and sixth steps stops supply of the first to third process gases. The third and fifth steps include an excitation period of supplying the second and third process gases, respectively, to the process field while exciting the respective process gases by an exciting mechanism.

Abstract: A trench isolation method of a semiconductor device includes forming polishing prevention film patterns on a semiconductor substrate, etching the semiconductor device by using the polishing prevention film patterns as masks and forming trenches, and forming conformal insulation films on the semiconductor substrate and the polishing prevention film patterns by burying the trenches. The conformal insulation films are first polished using a first polishing pad by using a slurry including an abrasive having a polishing selection ratio with respect to the polishing prevention film patterns. The first polished conformal insulation films are second polished using a second polishing pad including an abrasive and by using the polishing prevention film patterns as polishing prevention films.

Abstract: A slurry composition for chemical mechanical polishing (CMP) of a phase-change memory device is provided. The slurry composition comprises deionized water and iron or an iron compound. The slurry composition can achieve high polishing rate on a phase-change memory device and improved polishing selectivity between a phase-change memory material and a polish stop layer (e.g., a silicon oxide film), can minimize the occurrence of processing imperfections (e.g., dishing and erosion), and can lower the etch rate on a phase-change memory material to provide a high-quality polished surface. Further provided is a method for polishing a phase-change memory device using the slurry composition.

Abstract: A polishing liquid which is used for chemical mechanical polishing of a body to be polished in a planarization process for manufacturing of a semiconductor integrated circuit, the body to be polished including at least a first layer containing polysilicon or modified polysilicon and a second layer containing at least one selected from the group consisting of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbide, and silicon oxynitride, the polishing liquid having a pH of 1.5 to 7.0, including (1) colloidal silica particles, (2) an organic acid, and (3) an anionic surfactant, and being capable of selectively polishing the second layer with respect to the first layer.

Abstract: The present invention provides system and apparatus for use in processing wafers. The new system and apparatus allows for the production of thinner wafers that at same time remain strong. As a result, the wafers produced by the present process are less susceptible to breaking. The unique system also offers an improved structure for handling thinned wafers and reduces the number of processing steps. This results in improved yields and improved process efficiency.

Abstract: A method for manufacturing CMOS transistors includes an etching back process alternatively performed after the gate structure formation, the lightly doped drain formation, source/drain implantation, or SEG process to etch a hard mask layer covering and protecting a first type gate structure, and to reduce thickness deviation between the hard masks covering the first type gate structure and a second type gate structure. Therefore the damage to spacers, STIs, and the profile of the gate structures due to the thickness deviation is prevented.

Abstract: A method of forming an integrated circuit structure includes providing a semiconductor substrate; forming patterned features over the semiconductor substrate, wherein gaps are formed between the patterned features; filling the gaps with a first filling material, wherein the first filling material has a first top surface higher than top surfaces of the patterned features; and performing a first planarization to lower the top surface of the first filling material, until the top surfaces of the patterned features are exposed. The method further includes depositing a second filling material, wherein the second filling material has a second top surface higher than the top surfaces of the patterned features; and performing a second planarization to lower the top surface of the second filling material, until the top surfaces of the patterned features are exposed.

Abstract: The present invention relates to a process for producing an interpenetrating polymer network structure, which comprises the steps of impregnating a polymer molding with a radical polymerizable composition containing an ethylenically unsaturated compound and a radical polymerization initiator; and polymerizing the ethylenically unsaturated compound in a swollen state of the polymer molding impregnated with the radical polymerizable composition; wherein a chain transfer agent and/or a radical polymerization inhibitor are added to the radical polymerizable composition and/or the polymer molding before impregnating the polymer molding with the radical polymerizable composition. According to the present invention, a highly uniform interpenetrating polymer network structure can be obtained.

Abstract: A method for surface treatment of a group III nitride crystal includes the steps of lapping a surface of a group III nitride crystal using a hard abrasive grain with a Mohs hardness higher than 7, and abrasive-grain-free polishing the lapped surface of the group III nitride crystal using a polishing solution without containing abrasive grain, and the polishing solution without containing abrasive grain has a pH of not less than 1 and not more than 6, or not less than 8.5 and not more than 14. Accordingly, the method for surface treatment of a group III nitride crystal can be provided according to which hard abrasive grains remaining at the lapped crystal can be removed to reduce impurities at the crystal surface.

Abstract: Disclosed is a slurry for polishing a phase change material. The slurry includes an abrasive, an alkaline polishing promoter and deionized water. Due to the use of the abrasive and the alkaline polishing promoter, the pH of the slurry is adjusted, the polishing rate of the phase change material is improved, and the polishing selectivity of the phase change material to an underlying insulating layer is increased. Further disclosed is a method for patterning a phase change material using the slurry.

Abstract: A method for patterning a material is provided. The method includes patterning a second material over a first material over a substrate. A surface portion of the patterned second material is converted to form a third material and a remaining patterned second material, wherein the third material is around the remaining patterned second material. One of the remaining patterned second material and the third material is removed to form a mask. The first material is patterned by using the mask.

Abstract: Methods of avoiding chemical mechanical polish (CMP) edge erosion and a related wafer are disclosed. In one embodiment, the method includes providing a wafer; forming a first material across the wafer; forming a second material at an outer edge region of the wafer, leaving a central region of the wafer devoid of the second material; and performing chemical mechanical polishing (CMP) on the wafer. The second material diminishes CMP edge erosion.

Abstract: A method for planarizing a layer of a semiconductor device includes depositing a high density plasma (HDP) oxide layer over a wafer to have a reflective index distribution that is inversely proportional to a thickness distribution of the HDP oxide layer. A chemical mechanical polishing process is performed on the HDP oxide layer.

Abstract: Provided is a CMP method. According to the CMP method, an interlayer insulating layer having two or more layers is etched to form a trench and/or via hole, and a combined thickness of the two or more layers are measured. A barrier metal layer and a metal layer are sequentially formed in the trench and/or via hole. Portions of the metal layer, the barrier metal layer and the interlayer insulating layer are removed. After that, the combined thickness of the two or more insulating layers is measured again.

Abstract: Multiple pitch-multiplied spacers are used to form mask patterns having features with exceptionally small critical dimensions. One of each pair of spacers formed around a plurality of mandrels is removed and alternating layers, formed of two mutually selectively etchable materials, are deposited around the remaining spacers. Layers formed of one of the materials are then etched, leaving behind vertically-extending layers formed of the other of the materials, which form a mask pattern. Alternatively, instead of depositing alternating layers, amorphous carbon is deposited around the remaining spacers followed by a plurality of cycles of forming pairs of spacers on the amorphous carbon, removing one of the pairs of spacers and depositing an amorphous carbon layer. The cycles can be repeated to form the desired pattern. Because the critical dimensions of some features in the pattern can be set by controlling the width of the spaces between spacers, exceptionally small mask features can be formed.