Abstract: An ink leveling device includes a stage on which a target substrate is disposed, base frames disposed at sides of the stage, moving members coupled to the base frames and movable upward and downward, and at least one plate coupled to the moving members and disposed to press the target substrate. Light-emitting element ink is disposed on the target substrate.

Abstract: A thin film transistor includes an active layer and at least one gate stack. The active layer may be formed using multiple iterations of a unit layer stack deposition process, which includes an acceptor-type oxide deposition process and a post-transition metal oxide deposition process. A surface of each gate dielectric within the at least one gate stack contacts a surface of a respective layer of the oxide of the acceptor-type element so that leakage current of the active layer may be minimized. A source electrode and a drain electrode may contact an oxide layer providing lower contact resistance such as a layer of the post-transition metal oxide or a zinc oxide layer within the active layer.

Abstract: A method of planarizing a substrate comprises dispensing formable material onto a substrate, contacting, at a planarizing station at a first location, a superstrate held by a superstrate chuck with the formable material on the substrate, thereby forming a multilayer structure including the superstrate, a film of the formable material, and the substrate, releasing the superstrate from the superstrate chuck, moving the multilayer structure from the first location to a curing station located at a second location away from the first location, the curing station including an array of light-emitting diodes, and curing the film of the multilayer structure by exposing the film to light emitted from the array of light-emitting diodes.

Abstract: Methods and apparatus for reducing particle generation in a remote plasma source (RPS) include an RPS having a first plasma source with a first electrode and a second electrode, wherein the first electrode and the second electrode are symmetrical with hollow cavities configured to induce a hollow cathode effect within the hollow cavities, and wherein the RPS provides radicals or ions into the processing volume, and a radio frequency (RF) power source configured to provide a symmetrical driving waveform on the first electrode and the second electrode to produce an anodic cycle and a cathodic cycle of the RPS, wherein the anodic cycle and the cathodic cycle operate in a hollow cathode effect mode.

Abstract: A method for producing a PUF-film includes printing a layer of dielectric material on a film substrate, such that a variable thickness of the layer is obtained by the printing. The method includes arranging a structured electrode layer on the dielectric material such that the structured electrode layer is influenced with respect to an electric measurement value due to the variable thickness.

Abstract: A spin dry etching process includes loading an object into a dry etching system. A dry etching process is performed to the object, and the object is spun while the dry etching process is being performed. The spin dry etching process is performed using a semiconductor fabrication system. The semiconductor fabrication system includes a dry etching chamber in which a dry etching process is performed. A holder apparatus has a horizontally-facing slot that is configured for horizontal insertion of an etchable object therein. The etchable object includes either a photomask or a wafer. A controller is communicatively coupled to the holder apparatus and configured to spin the holder apparatus in a clockwise or counterclockwise direction while the dry etching process is being performed. An insertion of the etchable object into the horizontally-facing slot of the holder apparatus restricts a movement of the object as the dry etching process is performed.

Abstract: A method for treating high aspect ratio (HAR) structures arranged on a surface of a substrate includes a) spin rinsing the surface of the substrate using a first rinsing liquid; b) spinning off the first rinsing liquid from the surface of the substrate; and c) directing a gas mixture containing hydrogen fluoride onto the surface of the substrate after the first rinsing liquid is dispensed.

Abstract: The present invention relates to an ALD (Atomic layer deposition) apparatus and an ALD method. The ALD apparatus is provided with a reacting chamber and an annealing chamber, in which the reacting chamber is positioned with several heaters, a substrate to be deposited with an epitaxial layer may be transferred between different heaters, and each heater may independently moderate temperature. Different heaters correspond to different ALDs, and the number of the heaters may be varied to meet required a film to be deposited or composition of a crystal material. Because the heaters may be optimized to adapt to required temperature of different reactant gases, thickness of the epitaxial layer will meet expectation, and quality of the epitaxial layer will be promoted. Meanwhile, moderating the temperature independently may raise yield of production.

Abstract: A method of selectively transferring micro devices from a donor substrate to contact pads on a receiver substrate. Micro devices being attached to a donor substrate with a donor force. The donor substrate and receiver substrate are aligned and brought together so that selected micro devices meet corresponding contact pads. A receiver force is generated to hold selected micro devices to the contact pads on the receiver substrate. The donor force is weakened and the substrates are moved apart leaving selected micro devices on the receiver substrate. Several methods of generating the receiver force are disclosed, including adhesive, mechanical and electrostatic techniques.

Abstract: Disclosed is a method of making an optoelectronic device that incorporates a crosslinked resin-linear polyorganosiloxane.

Abstract: Embodiments of the disclosure provide an integrated circuit (IC) structure. The IC structure may include a first metal layer on a substrate, and a second metal layer on the substrate that is horizontally separated from the first metal layer. A dielectric material may include a first portion on the first metal layer, and having a first upper surface, a second portion on the second metal layer, and having a second upper surface, and a third portion on the substrate between the first metal layer and the second metal layer. The third portion of the dielectric material includes a third upper surface above the first upper surface of the first portion and the second upper surface of the second portion of the dielectric material.

Abstract: Methods and apparatus for selectively depositing a titanium material layer atop a substrate having a silicon surface and a dielectric surface are disclosed. In embodiments an apparatus is configured for forming a remote plasma reaction between titanium tetrachloride (TiCl4), hydrogen (H2) and argon (Ar) in a region between a lid heater and a showerhead of a process chamber at a first temperature of 200 to 800 degrees Celsius; and flowing reaction products into the process chamber to selectively form a titanium material layer upon the silicon surface of the substrate.

Abstract: In accordance with an embodiment of the present invention, a method of forming a densified fill layer is provided. The method includes forming a pair of adjacent vertical fins on a substrate, forming an inner liner on the sidewalls of the adjacent vertical fins, and forming a sacrificial layer on the inner liner. The method further includes forming a fill layer between the pair of adjacent vertical fins, wherein the fill layer is in contact with at least a portion of the sacrificial layer, removing at least a portion of the sacrificial layer in contact with the fill layer to form sidewall channels adjacent to the fill layer, and subjecting the fill layer to a densification process to form the densified fill layer.

Abstract: An apparatus may include a superstrate. The superstrate can include a body having a diameter. The body may fit within a projected square. The projected square may have a length equal to the diameter of the body. The body within the projected square may produce an open area between an exterior edge of the body and the projected square. The superstrate may further include a first projection extending from the exterior edge of the body within the open area.

Abstract: Semiconductor device is provided. The semiconductor device includes a base substrate and a first dielectric layer on the base substrate. The first dielectric layer contains a first trench and a second trench passing therethrough, and a width of the second trench is larger than a width of the first trench. The semiconductor device further includes a first gate dielectric layer and a first gate electrode in the first trench. A first recess is on the first gate dielectric layer between the first gate electrode and the first dielectric layer. The semiconductor device further includes a second gate dielectric layer and a second gate electrode in the second trench. A second recess is on the second gate dielectric layer between the second gate electrode and the first dielectric layer. The semiconductor device further includes a first protection layer in the first recess and a second protection layer in the second recess.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a conductive feature over the semiconductor substrate. The semiconductor device structure also includes a dielectric layer over the conductive feature and the semiconductor substrate. The semiconductor device structure further includes a conductive via surrounded by the dielectric layer and electrically connected to the conductive feature. The conductive via has a lower end and an upper end larger than the lower end, and the conductive via has a side surface curved inward.

Abstract: A method for manufacturing an interconnect structure includes providing a metal interconnect layer, forming a dielectric layer on the metal interconnect layer, forming a fluorocarbon layer on the dielectric layer, forming a patterned hardmask layer on the fluorocarbon layer, etching the fluorocarbon layer and the dielectric layer using the patterned hardmask layer as a mask to form a trench in the dielectric layer and a through-hole through the dielectric layer to the metal interconnect layer, forming a metal layer filling the trench and the through-hole, and planarizing the metal layer until the planarized metal layer has an upper surface that is flush with an upper surface of the fluorocarbon layer. The interconnect structure thus formed has an improved reliability.

Abstract: A planarization device includes a planarization pad and a pad conditioner over the planarization pad. The pad conditioner includes a rotatable plate having a lower surface separated from an upper surface of the planarization pad by a predetermined distance and at least one nozzle opening on the lower surface of the rotatable plate.

Abstract: A method for forming a film on a patterned surface of a substrate by atomic layer deposition (ALD) processing includes: adsorbing onto a patterned surface a first precursor containing silicon or metal in its molecule; adsorbing onto the first-precursor-adsorbed surface a second precursor containing no silicon or metal in its molecule; exposing the second-precursor-adsorbed surface to an excited reactant to oxidize, nitride, or carbonize the precursors adsorbed on the surface of the substrate; and repeating the above cycle to form a film on the patterned surface of the substrate.

Abstract: A semiconductor device includes a substrate, a peripheral structure, a lower insulating layer, and a stack. The substrate includes a peripheral circuit region and a cell array region. The peripheral structure is on the peripheral circuit region. The lower insulating layer covers the peripheral circuit region and the cell array region and has a protruding portion protruding from a flat portion. The stack is on the lower insulating layer and the cell array region, and includes upper conductive patterns and insulating patterns which are alternately and repeatedly stacked.

Abstract: A method of filling a dielectric trench includes forming two adjacent conductors on a substrate, forming a dielectric layer over a surface of the conductors and the substrate, removing a portion of the dielectric layer, treating a top surface of the dielectric layer with phosphorous plasma, and repeating the forming the dielectric layer, the removing the portion of the dielectric layer, and the treating the top surface of the dielectric layer in a multi cycle fashion. A narrowest width of the dielectric trench between the two adjacent conductors is smaller than about 30 nm.

Abstract: A strip of sacrificial semiconductor material is formed on top of a non-sacrificial semiconductor material substrate layer. A conformal layer of the non-sacrificial semiconductor material is epitaxially grown to cover the substrate layer and the strip of sacrificial semiconductor material. An etch is performed to selectively remove the strip of sacrificial semiconductor material and leave a hollow channel surrounded by the conformal layer and the substrate layer. Using an anneal, the conformal layer and the substrate layer are reflowed to produce an optical waveguide structure including the hollow channel.

Abstract: According to one embodiment, a substrate planarizing method includes dropping from above a substrate with topography, resist whose amount is determined in accordance with the volume of a concave portion according to the topography. The distance between a blank template with a flat pressing plane and the substrate is set to a predetermined distance and then the resist is cured. After that, the blank template is released from the resist and the substrate is entirely etched. The amount of resist to be dropped on the substrate is adjusted for units of shot of the substrate.

Abstract: Provided are methods and apparatus for ultraviolet (UV) assisted capillary condensation to form dielectric materials. In some embodiments, a UV driven reaction facilitates photo-polymerization of a liquid phase flowable material. Applications include high quality gap fill in high aspect ratio structures and por sealing of a porous solid dielectric film. According to various embodiments, single station and multi-station chambers configured for capillary condensation and UV exposure are provided.

Abstract: Methods and systems for enhancing electronic designs for improving mask designs and manufacturability of electronic circuit designs for multi-exposure lithography are disclosed. The methods identify gap rectangles in a design and create gap blocks with the some of the identified gap rectangles according to at least their positions in a design and design rules. A relation graph is determined among the gap blocks or gap rectangles. The methods adjust some gap blocks by altering their sizes or dimensions. Some gap blocks may be split into multiple smaller gap blocks. The methods convert some gap rectangles into metal fill(s) and/or metal extensions to generate a structured physical design based at least in part upon the gap blocks and/or the multiple smaller gap blocks.

Abstract: An integrated circuit device includes spaced apart conductive patterns on a substrate surface, and a supporting pattern on the substrate surface between adjacent ones of the conductive patterns and separated therefrom by respective gap regions. The adjacent ones of the conductive patterns extend away from the substrate surface beyond a surface of the supporting pattern therebetween. A capping layer is provided on respective surfaces of the conductive patterns and the surface of the supporting pattern. Related fabrication methods are also discussed.

Abstract: There is provided an etching method, including: disposing a target substrate within a chamber, the target substrate having a first silicon oxide film formed on a surface of the target substrate and a second silicon oxide film formed adjacent to the first silicon oxide film, the first silicon oxide film being formed by an atomic layer deposition method and the second silicon oxide film being formed by a method other than the atomic layer deposition method; and selectively etching the first silicon oxide film with respect to the second silicon oxide film by supplying one selected from the group consisting of HF gas and alcohol gas; HF gas and water vapor; HF gas, F2 gas, and alcohol gas; HF gas, F2 gas, and water vapor, into the chamber.

Abstract: A method, which forms an air-bubble-free thin film with a high-viscosity fluid resin, initially dispenses the fluid resin on an outer region of a semiconductor wafer while the semiconductor wafer is spinning, and then dispenses the fluid resin onto the center of the semiconductor wafer after the semiconductor wafer has stopped spinning.

Abstract: A display, lighting, window, or signage product incorporates a panel including a collection of distinct electro-optical elements formed over a substrate. The substrate is in the form of a matrix with multiple openings that are filled with respective rigid local encapsulation seals. A second set of rigid local encapsulation seals are adhered over the electro-optical elements, so that each electro-optical element has a local seal below it, and another local seal above it. The electro-optical elements may be light-emissive, light-controlling, and/or light-sensing.

Abstract: A method for depositing an insulating layer includes performing a primary deposition over a sidewall of a feature by depositing a layer of silicate glass using a silicon source at a first flow rate and a dopant source at a second flow rate. A ratio of the flow of the dopant source to the flow of the silicon source is a first ratio. The method further includes performing a secondary deposition over the sidewall of a feature by increasing the flow of the silicon source relative to the flow of the dopant source. The ratio of the flow of the dopant source to the flow of the silicon source is a second ratio lower than the first ratio, and stopping the flow of the silicon source after performing the secondary deposition. A reflow process is performed after stopping the flow. A variation in thickness of the layer of silicate glass over the sidewall of a feature after the reflow process is between 1% to 20%.

Abstract: A polishing apparatus which can reduce scratches that are generated on a surface of a substrate during polishing by detecting a foreign matter such as a fragment of the substrate on an inner circumferential surface of a retaining ring for holding an edge portion (peripheral portion) of the substrate is disclosed. The polishing apparatus includes a polishing table having a polishing surface, and a top ring having a substrate holding surface to hold a beck surface of a substrate and a retaining ring to retain the substrate on the substrate holding surface. The top ring holds the substrate and presses the substrate against the polishing surface. The polishing apparatus includes an imaging device configured to image an inner circumferential surface of the retaining ring, and an image processor configured to process an image obtained by the imaging device to judge whether there is a foreign matter on the inner circumferential surface of the retaining ring.

Abstract: A MEMS gyroscope is provided. A substrate can be formed with a substantially planar surface, a substantially hemispherical cavity extending into the surface, an actuation electrode, and a plurality of sensing electrodes. A resonator formed from a substantially hemispherical shell can be suspended within the cavity by a stem coupling the center of the bottom of the cavity to the center of the bottom of the shell. An electronic processor can be configured to cause a voltage to be applied to the actuation electrode, receive signals from the sensing electrodes, and process the received signals to determine rotation of the MEMS gyroscope.

Abstract: A chemical planarization process described herein can be used for planarizing a substrate without using mechanical abrasion. A developable planarization material can be applied to a substrate having a non-planar topography, such that a planar surface results. The resulting planarization layer can cover existing structures on the substrate. A top portion of the planarization layer can be solubilized using a solubility-changing agent, and then the soluble portion can be removed thereby slimming a height of the planarization material to a target value, which can be a top surface of a tallest underlying structure. With the substrate planarized, additional patterning operations can be executed.

Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a plurality of circuit devices over a substrate. The method includes forming an organic layer over the substrate. The organic layer is formed over the plurality of circuit devices. The method includes polishing the organic layer to planarize a surface of the organic layer. The organic layer is free of being thermally treated prior to the polishing. The organic material is un-cross-linked during the polishing. The method includes depositing a LT-film over the planarized surface of the organic layer. The depositing is performed at a temperature less than about 150 degrees Celsius. The depositing is also performed without using a spin coating process. The method includes forming a patterned photoresist layer over the LT-film.

Abstract: Methods for bonding substrate surfaces, bonded substrate assemblies, and design structures for a bonded substrate assembly. Device structures of a product chip are formed using a first surface of a device substrate. A wiring layer of an interconnect structure for the device structures is formed on the product chip. The wiring layer is planarized. A temporary handle wafer is removably bonded to the planarized wiring layer. In response to removably bonding the temporary handle wafer to the planarized first wiring layer, a second surface of the device substrate, which is opposite to the first surface, is bonded to a final handle substrate. The temporary handle wafer is then removed from the assembly.

Abstract: Methods for forming a semiconductor device include forming self-aligned trenches, in which a first set of trenches is used to align a second set of trenches. Methods taught herein can be used as a pitch doubling technique, and may therefore enhance device integration. Further, employing a very thin CMP stop layer, and recessing surrounding materials by about an equal amount to the thickness of the CMP stop layer, provides improved planarity at the surface of the device.

Abstract: A semiconductor process includes the following steps. A first gate structure and a second gate structure are formed on a substrate, wherein the top of the first gate structure includes a cap layer, so that the vertical height of the first gate structure is higher than the vertical height of the second gate structure. An interdielectric layer is formed on the substrate. A first chemical mechanical polishing process is performed to expose the top surface of the cap layer. A second chemical mechanical polishing process is performed to expose the top surface of the second gate structure or an etching process is performed to remove the interdielectric layer located on the second gate structure. A second chemical mechanical polishing process is then performed to remove the cap layer.

Abstract: Disclosed herein is a fabrication method of a semiconductor device to order to increase an operation liability of the semiconductor device. A method for fabricating a semiconductor device comprises forming a recess in a semiconductor substrate, forming a word line in a lower part of the recess, oxidizing a top portion of the word line, and depositing an insulating material in a remained part of the recess.

Abstract: A method for semiconductor processing is provided wherein a workpiece having an underlying body and a plurality of features extending therefrom, is provided. A first set of the plurality of features extend from the underlying body to a first plane, and a second set of the plurality features extend from the underlying body to a second plane. A protection layer overlies each of the plurality of features and an isolation layer overlies the underlying body and protection layer, wherein the isolation has a non-uniform first oxide density associated therewith. The isolation layer anisotropically etched based on a predetermined pattern, and then isotropically etched, wherein a second oxide density of the isolation layer is substantially uniform across the workpiece. The predetermined pattern is based, at least in part, on a desired oxide density, a location and extension of the plurality of features to the first and second planes.

Abstract: A FinFET device and method for fabricating a FinFET device is disclosed. An exemplary FinFET device includes a semiconductor substrate; an insulator layer disposed over the semiconductor substrate; a fin structure disposed over the insulator layer, the fin structure having a source region, a drain region, and a channel region disposed between the source region and the drain region; a gate structure disposed adjacent to the channel region of the fin structure; and a doped region disposed in the semiconductor substrate below the channel region of the fin structure. The gate structure includes a first gate dielectric layer disposed adjacent to the fin structure, a second gate dielectric layer, a charge storing layer disposed between the first gate dielectric layer and the second gate dielectric layer, and a gate electrode layer disposed adjacent to the second gate dielectric layer.

Abstract: A miniaturized semiconductor device is provided by reducing the design thickness of a wiring line protecting film covering the surface of a wiring layer, and reducing the distance between the wiring layer and via plugs formed by a self-aligning process. Dummy mask layers extending in the same layout pattern as the wiring layer is formed above the wiring layer covered with a protecting film composed of a cap layer and side wall layers. In the self-aligning process for forming via plugs in a self-aligned manner with the wiring layer and its protecting film, the thickness of the cap layer is reduced and the design interval between the via plugs is reduced, whereby the miniaturization of the semiconductor device is achieved.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a source region and a drain region provided on a surface area of a semiconductor region, a tunnel insulating film provided on a channel between the source region and the drain region, a charge storage layer provided on the tunnel insulating film, a first dielectric film provided on the charge storage layer and containing lanthanum aluminum silicon oxide or oxynitride, a second dielectric film provided on the first dielectric film and containing oxide or oxynitride containing at least one of hafnium (Hf), zirconium (Zr), titanium (Ti), and a rare earth metal, and a control gate electrode provided on the second dielectric film.

Abstract: Planarization methods and microelectronic structures formed therefrom are disclosed. The methods and structures use planarization materials comprising fluorinated compounds or acetoacetylated compounds. The materials are self-leveling and achieve planarization over topography without the use of etching, contact planarization, chemical mechanical polishing, or other conventional planarization techniques.

Abstract: When forming sophisticated high-k metal gate electrode structures on the basis of a replacement gate approach, pronounced loss of the interlayer dielectric material may be avoided by inserting at least one surface modification process, for instance in the form of a nitridation process. In this manner, leakage paths caused by metal residues formed in the interlayer dielectric material may be significantly reduced.

Abstract: Methods for forming a semiconductor device include forming self-aligned trenches, in which a first set of trenches is used to align a second set of trenches. Methods taught herein can be used as a pitch doubling technique, and may therefore enhance device integration. Further, employing a very thin CMP stop layer, and recessing surrounding materials by about an equal amount to the thickness of the CMP stop layer, provides improved planarity at the surface of the device.

Abstract: A method for planarizing a semiconductor device includes providing a substrate having at least one opening therein, each opening defining a lower portion and an upper portion; coating a light sensitive material layer over the substrate, the light sensitive material layer covering the lower and upper portions of the at least one opening; etching back the light sensitive material layer to expose the upper portion of the at least one opening; repeating the steps of coating and etching to remove a predetermined amount below the upper portion of the at least one opening; depositing an insulating layer over the substrate; and planarizing the insulating layer until the upper portion of the at least one opening is exposed.

Abstract: A flash memory device and methods of forming a flash memory device are provided. The flash memory device includes a doped silicon nitride layer having a dopant comprising carbon, boron or oxygen. The doped silicon nitride layer generates a higher number and higher concentration of nitrogen and silicon dangling bonds in the layer and provides an increase in charge holding capacity and charge retention time of the unit cell of a non-volatile memory device.

Abstract: A DNA amplification device utilizing a polydimethylsiloxane (PDMS) and silicon substrate coated with spin-on glass (SOG) is provided. This PDMS layer is irreversibly bonded to the SOG layer of the silicon substrate using oxygen plasma. The amplification device is an inexpensive, microfluidic device, which can be utilized as a portable thermo-cycler to perform PCR amplification of DNA in the field.

Abstract: Methods for forming a semiconductor device include forming self-aligned trenches, in which a first set of trenches is used to align a second set of trenches. Methods taught herein can be used as a pitch doubling technique, and may therefore enhance device integration. Further, employing a very thin CMP stop layer, and recessing surrounding materials by about an equal amount to the thickness of the CMP stop layer, provides improved planarity at the surface of the device.

Abstract: Planarization methods include depositing a mask material on top of an overburden layer on a semiconductor wafer. The mask material is planarized to remove the mask material from up areas of the overburden layer to expose the overburden layer without removing the mask material from down areas. The exposed overburden layer is wet etched and leaves a thickness remaining over an underlying layer. Remaining portions of the mask layer and the exposed portions of the overburden layer are planarized to expose the underlying layer.