Abstract: A method of straining a transistor channel zone is provided, including a) forming a plurality of stress blocks based on a material having an intrinsic stress, around a zone based on a semiconducting material in which a transistor channel will be made and on which a transistor gate will be formed, the stress blocks inducing a stress in the zone; b) forming a gate block on the zone, the gate block being disposed between the stress blocks; and c) at least partially removing the stress blocks without removing the gate block, wherein the gate block has a Young's modulus and a thickness such that the stress blocks are at least partially removed in step c) and the induced stress is at least partially maintained in the zone after the stress blocks are at least partially removed.

Abstract: A method for manufacturing a semiconductor structure is disclosed. The method includes: providing a substrate; forming an MRAM structure over the substrate; forming a first dielectric layer over the MRAM structure; forming a stop layer over the first dielectric layer; forming a second dielectric layer over the stop layer; and removing the second dielectric layer, the stop layer and at least a portion of the first dielectric layer through a planarization operation without exposing a top electrode of the MRAM structure. Associated methods are also disclosed.

Abstract: Provided herein are approaches for patterning a semiconductor device. In an exemplary approach, a method includes providing a set of contact openings through a photoresist formed atop a substrate, and implanting ions into just a sidewall surface of the set of contact openings. In an exemplary approach, the ions are implanted at an implant angle nonparallel with the sidewall surface to prevent the ions from implanting a surface of the substrate within the set of contact openings, and to form a treated layer along an entire height of the contact opening. The method further includes etching the substrate within the set of contact openings after the ions are implanted into the sidewall surface. As a result, by using an angled ion implantation to the contact opening sidewall surface as a pretreatment prior to etching, local critical dimension uniformity is improved.

Abstract: Provided herein are approaches for patterning a semiconductor device. In an exemplary approach, a method includes providing a set of patterning features atop a layer of a semiconductor device, and implanting ions into a sidewall surface of the set of patterning features. The method includes implanting ions at an angle nonparallel with the sidewall surface, for example, approximately 60° to a plane normal to the sidewall surface. The method further includes etching the semiconductor device after the ions are implanted into the sidewall surface. As a result, by using an angled ion implantation as a pretreatment prior to etching, photoresist roughness is minimized, and sidewall striation and etch-induced line edge roughness is reduced. Approaches herein may also improve etch selectivity with respect to underlying layers disposed under the photoresist, as well as improved photoresist profiles.

Abstract: A method for far back end of the line (FBEOL) protection of a semiconductor device includes forming a patterned layer over a back end of the line (BEOL) stack, depositing a first conformal protection layer on the patterned layer which covers horizontal surfaces of a top surface and sidewalls of openings formed in the patterned layer. A resist layer is patterned over the first conformal protection layer such that openings in the resist layer correspond with the openings in the patterned layer. The first conformal protection layer is etched through the openings in the resist layer to form extended openings that reach a stop position. The resist layer is removed, and a second conformal protection layer is formed on the first conformal protection layer and on sidewalls of the extended openings to form an encapsulation boundary to protect at least the patterned layer and a portion of the BEOL stack.

Abstract: A semiconductor device includes a substrate, a carrier transit layer disposed above the substrate, a compound semiconductor layer disposed on the carrier transit layer, a source electrode disposed on the compound semiconductor layer, a first groove disposed from the back of the substrate up to the inside of the carrier transit layer while penetrating the substrate, a drain electrode disposed in the inside of the first groove, a gate electrode located between the source electrode and the first groove and disposed on the compound semiconductor layer, and a second groove located diagonally under the source electrode and between the source electrode and the first groove and disposed from the back of the substrate up to the inside of the carrier transit layer while penetrating the substrate.

Abstract: Provided are a method of manufacturing a group-III nitride semiconductor light-emitting device in which a light-emitting device excellent in the internal quantum efficiency and the light extraction efficiency can be obtained, a group-III nitride semiconductor light-emitting device and a lamp. Included are an epitaxial step of forming a semiconductor layer (30) so as to a main surface (20) of a substrate (2), a masking step of forming a protective film on the semiconductor layer (30), a semiconductor layer removal step of removing the protective film and the semiconductor layer (30) by laser irradiation to expose the substrate (2), a grinding step of reducing the thickness of the substrate (2), a polishing step of polishing the substrate (2), a laser processing step of providing processing marks to the inside of the substrate (2), a division step of creating a plurality of light-emitting devices (1) while forming a division surface of the substrate (2) to have a rough surface.

Abstract: A method of making multi-level contacts. The method includes providing an in-process multilevel device including at least one device region and at least one contact region. The contact region includes a plurality of electrically conductive layers configured in a step pattern. The method also includes forming a conformal etch stop layer over the plurality of electrically conductive layers, forming a first electrically insulating layer over the etch stop layer, forming a conformal sacrificial layer over the first electrically insulating layer and forming a second electrically insulating layer over the sacrificial layer. The method also includes etching a plurality of contact openings through the etch stop layer, the first electrically insulating layer, the sacrificial layer and the second electrically insulating layer in the contact region to the plurality of electrically conductive layers.

Abstract: In a SOI process, a high lateral voltage isolation structure is formed by providing at least two concentric dielectric filled trenches, removing the semiconductor material between the dielectric filled trenches and filling the resultant gap with dielectric material to define a single wide dielectric filled trench.

Abstract: A High Electron Mobility Transistor (HEMT) includes a first III-V compound layer having a first band gap, and a second III-V compound layer having a second band gap over the first III-V compound layer. The second band gap is greater than the first band gap. A crystalline interfacial layer is overlying and in contact with the second III-V compound layer. A gate dielectric is over the crystalline interfacial layer. A gate electrode is over the gate dielectric. A source region and a drain region are over the second III-V compound layer, and are on opposite sides of the gate electrode.

Abstract: A composite hard mask is disclosed that prevents build up of metal etch residue in a MRAM device during etch processes that define an MTJ shape. As a result, MTJ shape integrity is substantially improved. The hard mask has a lower non-magnetic spacer, a middle conductive layer, and an upper sacrificial dielectric layer. The non-magnetic spacer serves as an etch stop during a pattern transfer with fluorocarbon plasma through the conductive layer. A photoresist pattern is transferred through the dielectric layer with a first fluorocarbon etch. Then the photoresist is removed and a second fluorocarbon etch transfers the pattern through the conductive layer. The dielectric layer protects the top surface of the conductive layer during the second fluorocarbon etch and during a substantial portion of a third RIE step with a gas comprised of C, H, and O that transfers the pattern through the underlying MTJ layers.

Abstract: A method of forming a pattern in a substrate is provided, in which the substrate having a pattern region is provided first. A plurality of stripe-shaped mask layers is formed on the substrate in the pattern region. Each of at least two adjacent stripe-shaped mask layers among the stripe-shaped mask layers has a protrusion portion and the protrusion portions face to each other. A spacer is formed on sidewalls of the stripe-shaped mask layers, wherein a thickness of the spacer is greater than a half of a distance between two of the protrusion portions. Subsequently, the stripe-shaped mask layers are removed. An etching process is performed by using the spacer as a mask to form trenches in the substrate. Thereafter, the trenches are filled with a material.

Abstract: Provided is a method of forming a semiconductor device. The method may include forming a first insulating layer on a semiconductor substrate. A first polycrystalline silicon layer may be formed on the first insulating layer. A second insulating layer may be formed on the first polycrystalline silicon layer. A second polycrystalline silicon layer may be formed on the second insulating layer. A mask pattern may be formed on the second polycrystalline silicon layer. The second polycrystalline silicon layer may be patterned using the mask pattern as an etch mask to form a second polycrystalline silicon pattern exposing a portion of the second insulating layer. A sidewall of the second polycrystalline silicon pattern may include a first amorphous region. The first amorphous region may be crystallized by a first recrystallization process. The exposed portion of the second insulating layer may be removed to form a second insulating pattern exposing a portion of the first polycrystalline silicon layer.

Abstract: A method for designing, fabricating, and predicting a desired structure in and/or on a host material through defining etch masks and etching the host material is provided. The desired structure can be micro- or nanoscale structures, such as suspended nanowires and corresponding supporting pillars, and can be defined one layer at a time. Arbitrary desired structures can also be defined and obtained through etching. Further, given the desired structure, a starting structure can be predicted where etching of the starting structure yields the desired structure.

Abstract: According to example embodiments of inventive concepts, a method of fabricating a semiconductor device includes forming a sacrificial pattern having SiGe on a crystalline silicon substrate. A body having crystalline silicon is formed on the sacrificial pattern. At least one active element is formed on the body. An insulating layer is formed to cover the sacrificial pattern, the body, and the active element. A contact hole is formed to expose the sacrificial pattern through the insulating layer. A void space is formed by removing the sacrificial pattern. An amorphous silicon layer is formed in the contact hole and the void space. The amorphous silicon layer is transformed into a metal silicide layer.

Abstract: A method to determine minimum etch mask dosage or thickness as a function of etch depth or maximum etch depth as a function of etch mask implantation dosage or thickness, for fabricating structures in or on a substrate through etch masking via addition or removal of a masking material and subsequent etching.

Abstract: A method for semiconductor processing is provided wherein a workpiece having an underlying body and a plurality of features extending therefrom, is provided. A first set of the plurality of features extend from the underlying body to a first plane, and a second set of the plurality features extend from the underlying body to a second plane. A protection layer overlies each of the plurality of features and an isolation layer overlies the underlying body and protection layer, wherein the isolation has a non-uniform first oxide density associated therewith. The isolation layer anisotropically etched based on a predetermined pattern, and then isotropically etched, wherein a second oxide density of the isolation layer is substantially uniform across the workpiece. The predetermined pattern is based, at least in part, on a desired oxide density, a location and extension of the plurality of features to the first and second planes.

Abstract: A method for forming fine pattern includes sequentially forming a first thin film and a second thin film over a target layer for patterning, forming a partition over the second thin film, removing the partition after forming spacers on sidewalls of the partition, forming first pattern of the second thin film by etching the second thin film of a first region and the second thin film of a second region while exposing the spacers, forming second pattern of the second thin film by using the spacers as masks and etching the first pattern of the second thin film in the first region, forming first thin film pattern by using the first and second patterns of the second thin film as masks in the first and second regions and etching the first thin film, and etching the pattern target layer.

Abstract: A method for fabricating a semiconductor device includes forming a plurality of active regions, each having a first sidewall and a second sidewall, by etching a semiconductor substrate, forming an insulation layer on the first sidewall and the second sidewall, forming an etch stop layer filling a portion of each gap between the active regions, forming a recess exposing the insulation layer formed on any one sidewall from among the first sidewall and the second sidewall, and forming a side contact exposing a portion of any one sidewall from among the first sidewall and the second sidewall by selectively removing a portion of the insulation layer.

Abstract: In a replacement gate approach, the polysilicon material may be efficiently removed during a wet chemical etch process, while the semiconductor material in the resistive structures may be substantially preserved. For this purpose, a species such as xenon may be incorporated into the semiconductor material of the resistive structure, thereby imparting a significantly increased etch resistivity to the semiconductor material. The xenon may be incorporated at any appropriate manufacturing stage.

Abstract: A device and method for improving performance of a transistor includes gate structures formed on a substrate having a spacing therebetween. The gate structures are formed in an operative relationship with active areas fainted in the substrate. A stress liner is formed on the gate structures. An angled ion implantation is applied to the stress liner such that ions are directed at vertical surfaces of the stress liner wherein portions of the stress liner in contact with the active areas are shielded from the ions due to a shadowing effect provided by a height and spacing between adjacent structures.

Abstract: Provided are methods of manufacturing semiconductor devices by which two different kinds of contact holes with different sizes are formed using one photolithography process. The methods include preparing a semiconductor substrate in which an active region is titled in a diagonal direction. A hard mask is formed on the entire surface of the semiconductor substrate. A mask hole is patterned not to overlap a word line. A first oxide layer is deposited on the hard mask, and the hard mask is removed to form a piston-shaped sacrificial pattern. A first polysilicon (poly-Si) layer is deposited on the sacrificial pattern and patterned to form a cylindrical first sacrificial mask surrounding the piston-shaped sacrificial pattern. A second oxide layer is coated on the first sacrificial mask to such an extent as to form voids. A second poly-Si layer is deposited in the voids and patterned to form a pillar-shaped second sacrificial mask. The second oxide layer is removed to expose the active region.

Abstract: A semiconductor device manufacturing method including: forming a first interlayer insulating film on a semiconductor substrate; forming a first hole in the first interlayer insulating film; forming a barrier film inside the first hole; filling a conductive material in the first hole to form a first plug; forming a second interlayer insulating film on the first interlayer insulating film; forming a second hole reaching the first plug in the second interlayer insulating film; selectively etching an upper end of the barrier film inside the second hole; and forming a second plug for connection to the first plug inside the second hole.

Abstract: A production method for producing a semiconductor device capable of improving surface flatness and suppressing a variation in electrical characteristics of the semiconductor chip, and improving production yield. The production method includes the steps of: forming a first insulating film on a semiconductor substrate and on a conductive pattern film formed on the semiconductor substrate and reducing a thickness of the first insulating film in a region where the conductive pattern film is arranged by patterning; forming a second insulating film and polishing the second insulating film, thereby forming a flattening film; implanting a substance for cleavage into the semiconductor substrate through the flattening film, thereby forming a cleavage layer; transferring the semiconductor chip onto a substrate with an insulating surface so that the chip surface on the side opposite to the semiconductor substrate is attached thereto; and separating the semiconductor substrate from the cleavage layer.

Abstract: Surface processing in which the area to be processed is restricted to a predetermined pattern, can be achieved by: (a) providing a layer of a first reagent over a region of the surface to be processed which at least covers an area of the predetermined pattern; (b) providing one or more further reagents which are further reagents required for the processing of the surface; and (c) applying at least one of the further reagents over the region to be processed according to the predetermined pattern; such that the first reagent acts with the one or more of the further reagents to process the surface only in the area of the predetermined pattern. The process is particularly applicable to etching where an etchant having two or more components is used. In that case at least a first etchant component is applied over the surface and at least one further etchant component is applied in the predetermined pattern.

Abstract: A method for forming features in a polysilicon layer is provided. A hardmask layer is formed over the polysilicon layer. A photoresist mask is formed over the hardmask layer. The hardmask layer is etched through the photoresist mask to form a patterned hardmask. The patterned hardmask is trimmed by providing a non-carbon containing trim gas comprising oxygen and a fluorine containing compound, forming a plasma from the trim gas, and trimming the hardmask. Features are etched into the polysilicon layer through the hardmask.

Abstract: Differently-sized features of an integrated circuit are formed by etching a substrate using a mask which is formed by combining two separately formed patterns. Pitch multiplication is used to form the relatively small features of the first pattern and conventional photolithography used to form the relatively large features of the second pattern. Pitch multiplication is accomplished by patterning a photoresist and then etching that pattern into an amorphous carbon layer. Sidewall spacers are then formed on the sidewalls of the amorphous carbon. The amorphous carbon is removed, leaving behind the sidewall spacers, which define the first mask pattern. A bottom anti-reflective coating (BARC) is then deposited around the spacers to form a planar surface and a photoresist layer is formed over the BARC. The photoresist is next patterned by conventional photolithography to form the second pattern, which is then is transferred to the BARC.

Abstract: Systems and methods for single lithography step interconnection metallization using a stop-etch layer are described. A method that includes depositing a stop-etch layer over a semiconductor device, depositing an interconnect metallization material over the stop-etch layer, performing a single lithography step to pattern a mask over the interconnect metallization material, etching the interconnect metallization material in non-masked areas, and removing the stop-etch layer. A system comprises a stop-etch layer material for deposit into a stop-etch layer over a wafer, an interconnect metallization material for deposit over the chrome layer, a lithography operation for patterning a mask over the interconnect metallization material, a first etching compound for etching the interconnect metallization material, where the etching stops at the stop-etch layer, and a second etching compound for removing the stop-etch layer.

Abstract: Integrated high efficiency lateral field effect rectifier and HEMT devices of GaN or analogous semiconductor material, methods for manufacturing thereof, and systems which include such integrated devices. The lateral field effect rectifier has an anode containing a shorted ohmic contact and a Schottky contact, and a cathode containing an ohmic contact, while the HEMT preferably has a gate containing a Schottky contact. Two fluorine ion containing regions are formed directly underneath both Schottky contacts in the rectifier and in the HEMT, pinching off the (electron gas) channels in both structures at the hetero-interface between the epitaxial layers.

Abstract: A method of removing silicon nitride over a semiconductor surface for forming shallow junctions. Sidewall spacers are formed along sidewalls of a gate stack that together define lightly doped drain (LDD) regions or source/drain (S/D) regions. At least one of the sidewall spacers, LDD regions and S/D regions include an exposed silicon nitride layer. The LDD or S/D regions include a protective dielectric layer formed directly on the semiconductor surface. Ion implanting implants the LDD regions or S/D regions using the sidewall spacers as implant masks. The exposed silicon nitride layer is selectively removed, wherein the protective dielectric layer when the sidewall spacers include the exposed silicon nitride layer, or a replacement protective dielectric layer formed directly on the semiconductor surface after ion implanting when the LDD or S/D regions include the exposed silicon nitride layer, protects the LDD or S/D regions from dopant loss due to etching during selectively removing.

Abstract: An etching method is provided in which selective etching can be carried out for an amorphous oxide semiconductor film including at least one of gallium and zinc, and indium. In the etching method, the selective etching is performed using an alkaline etching solution. The alkaline etching solution contains especially ammonia in a specific concentration range.

Abstract: A method for removing defects from a semiconductor surface is disclosed. The surface of the semiconductor is first coated with a protective layer, which is later thinned to selectively reveal portions of the protruding defects. The defects are then removed by etching. Finally, also the protective layer is removed. According to the method, inadvertent thinning of the surface is prevented and removal of the defects is obtained.

Abstract: A method of fabricating a semiconductor device forms a micro-sized gate, and mitigates short channel effects. The method includes a pull-back process to form the gate on a substrate. The method also includes forming inner and outer spacers on the gate that are asymmetric to one another with respect to the gate, and using the spacers in forming junction regions in the substrate on opposite sides of the gate. In particular, the inner and outer spacers are formed on opposite sides of the gate so as to have different thicknesses at the bottom of the gate. The inner and outer junction regions are formed by doping the substrate before and after the spacers are formed. Thus, the inner and outer junction regions have extension regions under the inner and outer spacers, respectively, and the extension regions have different lengths.

Abstract: Embodiments of the invention contemplate the formation of a high efficiency solar cell using novel methods to form the active region(s) and the metal contact structure of a solar cell device. In one embodiment, the methods include the use of various etching and patterning processes that are used to define point contacts through a blanket dielectric layer covering a surface of a solar cell substrate. The method generally includes depositing an etchant material that enables formation of a desired pattern in a dielectric layer through which electrical contacts to the solar cell device can be formed.

Abstract: A method of manufacturing a memory device includes an nMOS region and a pMOS region in a substrate. A first gate is defined within the nMOS region, and a second gate is defined in the pMOS region. Disposable spacers are simultaneously defined about the first and second gates. The nMOS and pMOS regions are selectively masked, one at a time, and LDD and Halo implants performed using the same masks as the source/drain implants for each region, by etching back spacers between source/drain implant and LDD/Halo implants. All transistor doping steps, including enhancement, gate and well doping, can be performed using a single mask for each of the nMOS and pMOS regions. Channel length can also be tailored by trimming spacers in one of the regions prior to source/drain doping.

Abstract: A method of planarizing a dielectric insulating layer including providing a substrate including forming a first dielectric insulating layer having a concave and convex portion on the substrate; forming an organic resinous layer on the first dielectric insulating layer and exposing the convex portion of the first dielectric insulating layer; isotropically etching the first dielectric insulating layer convex portion; removing the organic resinous layer; and, forming a second dielectric insulating layer on the first dielectric insulating layer.

Abstract: A method for mounting a semiconductor device onto a composite substrate, including a submount and a heat sink, is described. According to one aspect of the invention, the materials for the submount and the heat sink are chosen so that the value of coefficient of thermal expansion of the semiconductor device is in between the values of coefficients of thermal expansion of the materials of the submount and the heat sink, the thickness of the submount being chosen so as to equalize thermal expansion of the semiconductor device to that of the surface of the submount the device is mounted on. According to another aspect of the invention, the semiconductor device, the submount, and the heat sink are soldered into a stack at a single step of heating, which facilitates reduction of residual post-soldering stresses.

Abstract: A light-emitting device with a protection layer for Zn inter-diffusion and a process to form the device are described. The device of the invention provides an active layer containing aluminum (Al) as a group III element, typically AlGaInAs, and protection layers containing silicon (Si) to prevent the inter-diffusion of zing (Zn) atoms contained in p-type layers surrounding the active layer. One of protection layers is put between the active layer and the p-type cladding layer, while, the other of protection layers is disposed between the active layer and the p-type burying layer.

Abstract: One inventive aspect relates to a method of selective epitaxial growth of source/drain (S/D) areas. The method includes providing a substrate having a first and a second substrate area, the first area including at least one gate stack. The method includes applying a poly-Si or poly-SiGe top layer on the substrate, the top layer being etchable with the same etch chemistry as the substrate. The method includes removing the poly-Si or poly-SiGe top layer from the first area selectively towards the poly-Si or poly-SiGe top layer in the second area. The method includes removing simultaneously the poly-Si or poly-SiGe top layer on the second area and at least a part of the substrate in the S/D areas of the first area selectively to the gate stack. The method includes performing a selective epitaxial growth of S/D areas in the first area.

Abstract: An increase of the via resistance resulted due to the presence of the altered layer that has been formed and grown after the formation of the via hole can be effectively prevented, thereby providing an improved reliability of the semiconductor device. A method includes: forming a TiN film on the semiconductor substrate; forming an interlayer insulating film on a surface of the TiN film; forming a resist film on a surface of the interlayer insulating film; etching the semiconductor substrate having the resist film formed thereon to form an opening, thereby partially exposing the TiN film; plasma-processing the exposed portion of the TiN film to remove an altered layer formed in the exposed portion of the TiN film; and stripping the resist film via a high temperature-plasma processing.

Abstract: Solutions for solutions for utilizing Inverse Reactive Ion Etching lag in double patterning contact formation are disclosed. In one embodiment, a method includes providing a CMOS device including: an NMOS device having an NMOS gate and a PMOS device having a PMOS gate; a shallow trench isolation located between the NMOS device and the PMOS device; and an inter-level dielectric located over the NMOS device, the PMOS device and the shallow trench isolation; performing a double-patterning etch process on the CMOS device under conditions causing inverse reactive ion etching lag, the performing including forming a first opening, a second opening and a third opening, the second opening being wider than the first opening, and the third opening being contiguous with the second opening; and forming a first contact in the first opening and forming a second contact in both of the second opening and the third opening.

Abstract: A semiconductor substrate having a through-silicon via with an air gap interposed between the through-silicon via and the semiconductor substrate is provided. An opening is formed partially through the semiconductor substrate. The opening is first lined with a liner and then the opening is filled with a conductive material. A backside of the semiconductor substrate is thinned to expose the liner, which is subsequently removed to form an air gap around the conductive material of the through-silicon via. A dielectric layer is formed of the backside of the semiconductor substrate to seal the air gap.

Abstract: A method of making a device includes forming a first hard mask layer over an underlying layer, forming first features over the first hard mask layer, forming a first spacer layer over the first features, etching the first spacer layer to form a first spacer pattern and to expose top of the first features, removing the first features, patterning the first hard mask using the first spacer pattern as a mask to form first hard mask features, removing the first spacer pattern. The method also includes forming second features over the first hard mask features, forming a second spacer layer over the second features, etching the second spacer layer to form a second spacer pattern and to expose top of the second features, removing the second features, etching the first hard mask features using the second spacer pattern as a mask to form second hard mask features, and etching at least part of the underlying layer using the second hard mask features as a mask.

Abstract: Differently-sized features of an integrated circuit are formed by etching a substrate using a mask which is formed by combining two separately formed patterns. Pitch multiplication is used to form the relatively small features of the first pattern and conventional photolithography used to form the relatively large features of the second pattern. Pitch multiplication is accomplished by patterning a photoresist and then etching that pattern into an amorphous carbon layer. Sidewall spacers are then formed on the sidewalls of the amorphous carbon. The amorphous carbon is removed, leaving behind the sidewall spacers, which define the first mask pattern. A bottom anti-reflective coating (BARC) is then deposited around the spacers to form a planar surface and a photoresist layer is formed over the BARC. The photoresist is next patterned by conventional photolithography to form the second pattern, which is then is transferred to the BARC.

Abstract: In an embodiment, a method of forming a lower electrode of a capacitor in a semiconductor memory device includes etching a mold oxide layer to have at a cylindrical structure, resulting in an electrode with increased surface area. The cylindrical structure may have more than one radius. This increased surface area results in an increased capacitance. An excessive etch phenomenon, which occurs because a sacrificial oxide layer is etched at a higher rate than the mold oxide layer, is avoided.

Abstract: Disclosed is a structure and method for forming a structure including a SiCOH layer having increased mechanical strength. The structure includes a substrate having a layer of dielectric or conductive material, a layer of oxide on the layer of dielectric or conductive material, the oxide layer having essentially no carbon, a graded transition layer on the oxide layer, the graded transition layer having essentially no carbon at the interface with the oxide layer and gradually increasing carbon towards a porous SiCOH layer, and a porous SiCOH (pSiCOH) layer on the graded transition layer, the porous pSiCOH layer having an homogeneous composition throughout the layer. The method includes a process wherein in the graded transition layer, there are no peaks in the carbon concentration and no dips in the oxygen concentration.

Abstract: A semiconductor light emitting device can have stable electric characteristics and can emit light with high intensity from a substrate surface. The device can include a transparent substrate and a semiconductor layer on the substrate. The semiconductor layer can include a first conductive type semiconductor layer, a luminescent layer, a second conductive type semiconductor layer, and first and second electrodes disposed to make contact with the first and second conductive type semiconductor layers, respectively. The first conductive type semiconductor layer, the luminescent layer, and the second conductive type semiconductor layer can be laminated in order from the side adjacent the substrate. An end face of the semiconductor layer can include a first terrace provided in an end face of the first conductive type semiconductor layer in parallel with the substrate surface, and an inclined end face region provided nearer to the substrate than the first terrace.

Abstract: Method for fabricating a semiconductor device, including the steps of providing a first conductive type semiconductor substrate having a cell region and a logic region defined thereon, forming a first insulating film, second conductive type polysilicon, and a second insulating film in succession on the semiconductor substrate, selectively removing the first insulating film, the polysilicon, and the second insulating film, to form a floating gate pattern at the cell region, elevating a temperature initially in a state O2 gas is injected, maintaining a fix temperature, and dropping the temperature in a state N2 gas is injected, to form a gate oxide film on a surface of the semiconductor substrate at the logic region, and forming a gate electrode pattern at each of the cell region and the logic region, whereby preventing a threshold voltage of a semiconductor device from dropping due to infiltration of impurities from doped polysilicon at the cell region to the active channel region.

Abstract: Systems and methods for single lithography step interconnection metallization using a stop-etch layer are described. A method comprises depositing a stop-etch layer over a semiconductor device, depositing an interconnect metallization material over the stop-etch layer, performing a single lithography step to pattern a mask over the interconnect metallization material, etching the interconnect metallization material in non-masked areas, and removing the stop-etch layer. A system comprises means for depositing the stop-etch layer over a wafer, means for depositing an interconnected metallization layer over the chrome layer, means for patterning a mask over the interconnect metallization layer, means for etching the interconnect metallization layer, where the etching stops at the stop-etch layer, and means for removing the stop-etch layer.

Abstract: An etched grooved GaN-based permeable-base transistor structure is disclosed, along with a method for fabrication of same.