Removal By Chemical Etching, E.g., Dry Etching (epo) Patents (Class 257/E21.245)
  • Patent number: 10707330
    Abstract: A method of manufacturing a semiconductor device is provided including providing an SOI substrate comprising a semiconductor bulk substrate, a buried insulation layer and a semiconductor layer, forming a shallow trench isolation in the SOI substrate, forming a FET in and over the SOI substrate, and forming a contact to a source or drain region of the FET that is positioned adjacent to the source or drain region, wherein forming the shallow trench isolation includes forming a trench in the SOI substrate, filling a lower portion of the trench with a first dielectric layer, forming a buffer layer over the first dielectric material layer, the buffer layer having a material different from a material of the first dielectric layer, and forming a second dielectric layer over the buffer layer and of a material different from the material of the buffer layer.
    Type: Grant
    Filed: February 15, 2018
    Date of Patent: July 7, 2020
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Hans-Juergen Thees, Peter Baars, Elliot John Smith
  • Patent number: 10658172
    Abstract: Methods and apparatuses for depositing material into high aspect ratio features, features in a multi-laminate stack, features having positively sloped sidewalls, features having negatively sloped sidewalls, features having a re-entrant profile, and/or features having sidewall topography are described herein. Methods involve depositing a first amount of material, such as a dielectric (e.g., silicon oxide), into a feature and forming a sacrificial helmet on the field surface of the substrate, etching some of the first amount of the material to open the feature opening and/or smoothen sidewalls of the feature, and depositing a second amount of material to fill the feature. The sacrificial helmet may be the same as or different material from the first amount of material deposited into the feature.
    Type: Grant
    Filed: March 6, 2019
    Date of Patent: May 19, 2020
    Assignee: Lam Research Corporation
    Inventors: Joseph R. Abel, Pulkit Agarwal, Richard Phillips, Purushottam Kumar, Adrien LaVoie
  • Patent number: 10537967
    Abstract: A laser processing method includes a supporting step of attaching an adhesive tape to an annular frame having an opening for accommodating the plate-shaped workpiece and attaching the plate-shaped workpiece to the adhesive tape. The adhesive tape is composed of a base film, an adhesive layer formed on one side of the base film, and a functional layer formed on the other side of the base film. The functional layer includes fine particles of metal oxide, emulsion particles of thermoplastic resin as a binder, and a dispersing medium. The laser processing method further includes a laser processed groove forming step of applying a laser beam from a laser beam applying unit to the plate-shaped workpiece held on the chuck table and relatively feeding the chuck table and the laser beam applying unit by operating a feeding unit, thereby forming the laser processed groove on the plate-shaped workpiece.
    Type: Grant
    Filed: December 11, 2015
    Date of Patent: January 21, 2020
    Assignee: DISCO CORPORATION
    Inventors: Hirokazu Matsumoto, Saki Kimura
  • Patent number: 10510615
    Abstract: A method of manufacturing a semiconductor device includes forming a semiconductor strip protruding above a substrate, forming isolation regions on opposing sides of the semiconductor strip, recessing the isolation regions in a first chamber using a first etching process, and increasing a planarity of the isolation regions in the first chamber using a second etching process.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Chan Weng, Wan-Chun Kuan, Yi-Wei Chiu, Meng-Je Chuang
  • Patent number: 10453651
    Abstract: Systems and methods for determining a fault in a gas heater channel are described. One of the methods includes receiving measured parameters associated with a plurality of heater elements of the gas heater channel. The gas heater channel transfers one or more gases from a gas supply to a plasma chamber. The method further includes calculating a measured parallel resistance of the plurality of heater elements from the measured parameters, comparing the measured parallel resistance to an ideal parallel resistance of the heater elements of the gas heater channel, and determining based on the comparison that a portion of the gas heater channel is inoperational. The method includes selecting an identity of one of the heater elements from a correspondence between a plurality of identities of the heater elements and the measured parallel resistance.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: October 22, 2019
    Assignee: Lam Research Corporation
    Inventor: Dirk Rudolph
  • Patent number: 10366900
    Abstract: In a method for manufacturing a semiconductor device, a first dielectric layer is formed over an underlying structure disposed on a substrate. A planarization resistance layer is formed over the first dielectric layer. A second dielectric layer is formed over the first dielectric layer and the planarization resistance layer. A planarization operation is performed on the second dielectric layer, the planarization resistance layer and the first dielectric layer. The planarization resistance film is made of a material different from the first dielectric layer.
    Type: Grant
    Filed: March 25, 2016
    Date of Patent: July 30, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Juing-Yi Wu, Liang-Yao Lee, Tsung-Chieh Tsai
  • Patent number: 10354884
    Abstract: The etching of a sacrificial silicon dioxide (SiO2) portion in a microstructure such as a microelectro-mechanical structures (MEMS) by the use an etchant gas, namely hydrogen fluoride (HF) vapor is performed with greater selectivity to other portions within the MEMS, and in particular portions of silicon nitride (Si3N4). This is achieved by the addition of a secondary non-etchant gas suitable for increase the ratio of difluoride reactive species (HF2? and H2F2) to monofluoride reactive species (F?, and HF) within the HF vapor. The secondary non-etchant gas may comprise a hydrogen compound gas. The ratio of difluoride reactive species (HF2? and H2F2) to the monofluoride reactive species (F?, and HF) within the HF vapor can also be increased by setting an etch operating temperature to 20° C. or below.
    Type: Grant
    Filed: January 24, 2012
    Date of Patent: July 16, 2019
    Assignee: MEMSSTAR LIMITED
    Inventor: Anthony O'Hara
  • Patent number: 10269559
    Abstract: Methods and apparatuses for depositing material into high aspect ratio features, features in a multi-laminate stack, features having positively sloped sidewalls, features having negatively sloped sidewalls, features having a re-entrant profile, and/or features having sidewall topography are described herein. Methods involve depositing a first amount of material, such as a dielectric (e.g., silicon oxide), into a feature and forming a sacrificial helmet on the field surface of the substrate, etching some of the first amount of the material to open the feature opening and/or smoothen sidewalls of the feature, and depositing a second amount of material to fill the feature. The sacrificial helmet may be the same as or different material from the first amount of material deposited into the feature.
    Type: Grant
    Filed: September 13, 2017
    Date of Patent: April 23, 2019
    Assignee: Lam Research Corporation
    Inventors: Joseph Abel, Pulkit Agarwal, Richard Phillips, Purushottam Kumar, Adrien LaVoie
  • Patent number: 10217648
    Abstract: Methods using chemical vapor deposition (CVD) of diamond deposited on a sacrificial material provide CVD diamond microchannel structures and 3-D interconnection structures of CVD diamond microfluidic channels. The sacrificial material is patterned to define locations and dimensions of the microchannels. The patterned sacrificial material is selectively removed from underneath the chemical vapor deposited (CVD) diamond to form the CVD diamond microchannels. The CVD diamond microchannels are integrated with electronic structures to provide an integral microfluidic cooling system to electronic devices.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: February 26, 2019
    Assignee: HRL Laboratories, LLC
    Inventors: David F. Brown, Keisuke Shinohara, Miroslav Micovic, Alexandros Margomenos, Andrea Corrion, Hector L. Bracamontes, Ivan Alvarado-Rodriguez
  • Patent number: 10074721
    Abstract: In an embodiment, a method of planarizing a surface includes applying a first layer to a surface including a protruding region such that the first layer covers the surface and the protruding region, removing a portion of the first layer above the protruding region and forming an indentation in the first layer above the protruding region, the protruding region remaining covered by material of the first layer, and progressively removing an outermost surface of the first layer to produce a planarised surface.
    Type: Grant
    Filed: September 22, 2016
    Date of Patent: September 11, 2018
    Assignee: Infineon Technologies AG
    Inventors: Albert Birner, Helmut Brech, Simone Lavanga
  • Patent number: 10062571
    Abstract: A method of manufacturing a semiconductor device includes forming a feature layer on a substrate, forming a plurality of reference patterns, arranged at a first pitch, on the feature layer, forming an organic liner on a side wall of each of the plurality of reference patterns, forming a plurality of buried patterns on the organic liner, removing the organic liner exposed between the plurality of buried patterns and the plurality of reference patterns, and etching the feature layer by using the plurality of buried patterns and the plurality of reference patterns as etch masks to form a feature pattern. Each of the plurality of buried patterns covers a space between side walls of two adjacent reference patterns among the plurality of reference patterns.
    Type: Grant
    Filed: November 3, 2016
    Date of Patent: August 28, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun-chul Yoon, Kyoung-seon Kim, Hai-sub Na, Jin Park
  • Patent number: 9362357
    Abstract: A method of forming SSRW FETs with controlled step height between a field oxide and epitaxially grown silicon and the resulting devices are provided. Embodiments include providing a SiN layer on a substrate, forming first, second, and third spaced STI regions of field oxide through the SiN layer and into the substrate, removing a top portion of the field oxide for each STI region by a controlled deglaze, removing the SiN layer, forming an n-type region in the substrate between the first and second STI regions and a p-type region in the substrate between the second and third STI regions, and epitaxially growing a Si based layer on the substrate over the n-type and p-type regions.
    Type: Grant
    Filed: May 19, 2015
    Date of Patent: June 7, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Laegu Kang, Vara Govindeswara Reddy Vakada, Michael Ganz, Yi Qi, Puneet Khanna, Sri Charan Vemula, Srikanth Samavedam
  • Patent number: 9305825
    Abstract: A method of manufacturing a semiconductor device includes forming a plurality of fins by forming a plurality of first device isolating trenches repeated at a first pitch in a substrate, forming a plurality of fin-type active areas protruding from a top surface of a first device isolating layer by forming the first device isolating layer in the plurality of first device isolating trenches, forming a plurality of second device isolating trenches at a pitch different from the first pitch by etching a portion of the substrate and the first device isolating layer, and forming a second device isolating layer in the plurality of second device isolating trenches, so as to form a plurality of fin-type active area groups separated from each other with the second device isolating layer therebetween.
    Type: Grant
    Filed: February 7, 2014
    Date of Patent: April 5, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-sang Youn, Myung-geun Song, Ji-hoon Cha, Jae-jik Baek, Bo-un Yoon, Jeong-nam Han
  • Patent number: 9040424
    Abstract: A single crystal silicon etching method includes providing a single crystal silicon substrate having at least one trench therein. The single crystal silicon substrate is exposed to an anisotropic etchant that undercuts the single crystal silicon. By controlling the length of the etch, single crystal silicon islands or smooth vertical walls in the single crystal silicon may be created.
    Type: Grant
    Filed: March 9, 2012
    Date of Patent: May 26, 2015
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Janos Fucsko, David H. Wells, Patrick Flynn, Whonchee Lee
  • Patent number: 8962452
    Abstract: In one embodiment, a method of singulating semiconductor die from a semiconductor wafer includes forming a material on a surface of a semiconductor wafer and reducing a thickness of portions of the material. Preferably, the thickness of the material is reduced near where singulation openings are to be formed in the semiconductor wafer.
    Type: Grant
    Filed: December 2, 2013
    Date of Patent: February 24, 2015
    Assignee: Semiconductor Components Industries, LLC
    Inventor: Gordon M. Grivna
  • Patent number: 8932956
    Abstract: A method for far back end of the line (FBEOL) protection of a semiconductor device includes forming a patterned layer over a back end of the line (BEOL) stack, depositing a first conformal protection layer on the patterned layer which covers horizontal surfaces of a top surface and sidewalls of openings formed in the patterned layer. A resist layer is patterned over the first conformal protection layer such that openings in the resist layer correspond with the openings in the patterned layer. The first conformal protection layer is etched through the openings in the resist layer to form extended openings that reach a stop position. The resist layer is removed, and a second conformal protection layer is formed on the first conformal protection layer and on sidewalls of the extended openings to form an encapsulation boundary to protect at least the patterned layer and a portion of the BEOL stack.
    Type: Grant
    Filed: December 4, 2012
    Date of Patent: January 13, 2015
    Assignee: International Business Machines Corporation
    Inventors: Tymon Barwicz, Robert L. Bruce, Swetha Kamlapurkar
  • Patent number: 8865543
    Abstract: The embodiments of the present invention provide a Ge-based NMOS device structure and a method for fabricating the same. By using the method, double dielectric layers of germanium oxide (GeO2) and metal oxide are deposited between the source/drain region and the substrate. The present invention not only reduces the electron Schottky barrier height of metal/Ge contact, but also improves the current switching ratio of the Ge-based Schottky and therefore, it will improve the performance of the Ge-based Schottky NMOS transistor. In addition, the fabrication process is very easy and completely compatible with the silicon CMOS process. As compared with conventional fabrication method, the Ge-based NMOS device structure and the fabrication method in the present invention can easily and effectively improve the performance of the Ge-based Schottky NMOS transistor.
    Type: Grant
    Filed: February 21, 2012
    Date of Patent: October 21, 2014
    Assignee: Peking University
    Inventors: Ru Huang, Zhiqiang Li, Xia An, Yue Guo, Xing Zhang
  • Patent number: 8859396
    Abstract: In one embodiment, a method of singulating semiconductor die from a semiconductor wafer includes forming a material on a surface of a semiconductor wafer and reducing a thickness of portions of the material. Preferably, the thickness of the material is reduced near where singulation openings are to be formed in the semiconductor wafer.
    Type: Grant
    Filed: June 9, 2011
    Date of Patent: October 14, 2014
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Gordon M. Grivna, John M. Parsey, Jr.
  • Patent number: 8853085
    Abstract: A method for defining a template for directed self-assembly (DSA) materials includes patterning a resist on a stack including an ARC and a mask formed over a hydrophilic layer. A pattern is formed by etching the ARC and the mask to form template lines which are trimmed to less than a minimum feature size (L). Hydrophobic spacers are formed on the template lines and include a fractional width of L. A neutral brush layer is grafted to the hydrophilic layer. A DSA material is deposited between the spacers and annealed to form material domains in a form of alternating lines of a first and a second material wherein the first material in contact with the spacers includes a width less than a width of the lines. A metal is added to the domains forming an etch resistant second material. The first material and the spacers are removed to form a DSA template pattern.
    Type: Grant
    Filed: April 23, 2013
    Date of Patent: October 7, 2014
    Assignee: International Business Machines Corporation
    Inventors: Jassem A. Abdallah, Matthew E. Colburn, Steven J. Holmes, Chi-Chun Liu
  • Patent number: 8841217
    Abstract: In one implementation, a chemical sensor is described. The chemical sensor includes a chemically-sensitive field effect transistor including a floating gate conductor having an upper surface. A dielectric material defines an opening extending to the upper surface of the floating gate conductor. A conductive element on a sidewall of the opening and extending over an upper surface of the dielectric material.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: September 23, 2014
    Assignee: Life Technologies Corporation
    Inventors: Keith Fife, James Bustillo, Jordan Owens
  • Patent number: 8790962
    Abstract: A semiconductor device is made by forming an interconnect structure over a substrate. A semiconductor die is mounted to the interconnect structure. The semiconductor die is electrically connected to the interconnect structure. A ground pad is formed over the interconnect structure. An encapsulant is formed over the semiconductor die and interconnect structure. A shielding cage can be formed over the semiconductor die prior to forming the encapsulant. A shielding layer is formed over the encapsulant after forming the interconnect structure to isolate the semiconductor die with respect to inter-device interference. The shielding layer conforms to a geometry of the encapsulant and electrically connects to the ground pad. The shielding layer can be electrically connected to ground through a conductive pillar. A backside interconnect structure is formed over the interconnect structure, opposite the semiconductor die.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: July 29, 2014
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Reza A. Pagaila, Rui Huang, Yaojian Lin
  • Patent number: 8741702
    Abstract: An object is to manufacture a semiconductor device including an oxide semiconductor at low cost with high productivity in such a manner that a photolithography process is simplified by reducing the number of light-exposure masks. In a method for manufacturing a semiconductor device including a channel-etched inverted-staggered thin film transistor, an oxide semiconductor film and a conductive film are etched using a mask layer formed with the use of a multi-tone mask which is a light-exposure mask through which light is transmitted so as to have a plurality of intensities. In etching steps, a first etching step is performed by dry etching in which an etching gas is used, and a second etching step is performed by wet etching in which an etchant is used.
    Type: Grant
    Filed: October 20, 2009
    Date of Patent: June 3, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunichi Ito, Miyuki Hosoba, Hideomi Suzawa, Shinya Sasagawa, Taiga Muraoka
  • Patent number: 8729707
    Abstract: A method of manufacturing a semiconductor device includes forming an insulating film over a semiconductor substrate, forming a capacitor including a lower electrode, a capacitor dielectric film including a ferroelectric material, and an upper electrode over the insulating film, forming a first protective insulating film over a side surface and upper surface of the capacitor by a sputtering method, and forming a second protective insulating film over the first protective insulating film by an atomic layer deposition method.
    Type: Grant
    Filed: October 4, 2012
    Date of Patent: May 20, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Wensheng Wang
  • Patent number: 8669190
    Abstract: In a method for manufacturing a semiconductor device, a process of providing a semiconductor wafer having a wiring layer having conductive patterns and a plurality of insulation films containing a first insulation film surrounding side surfaces of the conductive patterns are provided. After the process of providing the semiconductor wafer, a process of removing some regions of the plurality of insulation films to form openings is provided. Herein, the first insulation film is disposed to a position closer to the circumference of the semiconductor wafer than a position closest to the outermost circumference of the wafer among the arrangement positions of the conductive patterns.
    Type: Grant
    Filed: February 6, 2012
    Date of Patent: March 11, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventors: Kenji Togo, Hiroaki Sano
  • Patent number: 8669187
    Abstract: A porous lift off layer facilitates removal of films from surfaces, such as semiconductors. A layer, with porosities typically larger than the film thickness is provided where no film is desired. The film is applied over the porous layer and also where it is desired. The porous material and the film are then removed from areas where film is not intended. The porous layer can be provided as a slurry, dried to open porosities, or fugitive particles within a field, which disassociate upon the application of heat or solvent. The film can be removed by etchant that enters through porosities that have arisen due to the film not bridging the spaces between solid portions. Etchant attacks both film surfaces. Particles may have diameters of four to ten times the film thickness. Particles may be silica, alumina and ceramics. Porous layers can be used in depressions or on flat surfaces.
    Type: Grant
    Filed: May 7, 2010
    Date of Patent: March 11, 2014
    Assignee: 1366 Technologies, Inc.
    Inventors: Emanuel M. Sachs, Andrew M. Gabor
  • Publication number: 20140065828
    Abstract: A process is provided for selective removal of one or more unwanted fins during FINFET device fabrication. In one aspect, the process includes: providing a conformal protective layer over multiple fin structures on a substrate; patterning one or more openings over the unwanted fin structure(s); and removing at least a top portion of the unwanted fin structure(s) exposed through the opening(s), the removing including removing at least a portion of the conformal protective layer over the unwanted fin structure(s) exposed through the opening(s). In enhanced aspects, the removing includes removing a hard mask from the at least one unwanted fin structure(s) exposed through the opening(s), and selectively removing semiconductor material of at least one unwanted fin structure(s). The conformal protective layer protects one or more remaining fin structures during the selective removal of the semiconductor material of the unwanted fin structure(s).
    Type: Application
    Filed: September 5, 2012
    Publication date: March 6, 2014
    Applicant: GLOBALFOUNDRIES, INC.
    Inventors: Dae-Han CHOI, Jae Hee HWANG, Wontae HWANG
  • Patent number: 8664040
    Abstract: A method includes performing an etching step on a package. The package includes a package component, a connector on a top surface of the package component, a die bonded to the top surface of the package component, and a molding material molded over the top surface of the package component. The molding material covers the connector, wherein a portion of the molding material covering the connector is removed by the etching step, and the connector is exposed.
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: March 4, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Chung-Shi Liu, Chun-Cheng Lin, Meng-Tse Chen, Ming-Da Cheng
  • Patent number: 8647986
    Abstract: A semiconductor process includes the following steps. A first gate structure and a second gate structure are formed on a substrate, wherein the top of the first gate structure includes a cap layer, so that the vertical height of the first gate structure is higher than the vertical height of the second gate structure. An interdielectric layer is formed on the substrate. A first chemical mechanical polishing process is performed to expose the top surface of the cap layer. A second chemical mechanical polishing process is performed to expose the top surface of the second gate structure or an etching process is performed to remove the interdielectric layer located on the second gate structure. A second chemical mechanical polishing process is then performed to remove the cap layer.
    Type: Grant
    Filed: August 30, 2011
    Date of Patent: February 11, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Po-Cheng Huang, Teng-Chun Tsai, Chia-Lin Hsu, Chun-Wei Hsu, Yen-Ming Chen, Chih-Hsun Lin, Chang-Hung Kung
  • Patent number: 8633116
    Abstract: A dry etching method includes a first step and a second step. The first step includes generating a first plasma from a gas mixture, which includes an oxidation gas and a fluorine containing gas, and performing anisotropic etching with the first plasma on a silicon layer to form a recess in the silicon layer. The second step includes alternately repeating an organic film forming process whereby an organic film is deposited on the inner surface of the recess with a second plasma, and an etching process whereby the recess covered with the organic film is anisotropically etched with the first plasma. When an etching stopper layer is exposed from a part of the bottom surface of the recess formed in the first step, the first step is switched to the second step.
    Type: Grant
    Filed: January 25, 2011
    Date of Patent: January 21, 2014
    Assignee: Ulvac, Inc.
    Inventors: Manabu Yoshii, Kazuhiro Watanabe
  • Patent number: 8551886
    Abstract: A method for semiconductor processing is provided wherein a workpiece having an underlying body and a plurality of features extending therefrom, is provided. A first set of the plurality of features extend from the underlying body to a first plane, and a second set of the plurality features extend from the underlying body to a second plane. A protection layer overlies each of the plurality of features and an isolation layer overlies the underlying body and protection layer, wherein the isolation has a non-uniform first oxide density associated therewith. The isolation layer anisotropically etched based on a predetermined pattern, and then isotropically etched, wherein a second oxide density of the isolation layer is substantially uniform across the workpiece. The predetermined pattern is based, at least in part, on a desired oxide density, a location and extension of the plurality of features to the first and second planes.
    Type: Grant
    Filed: April 9, 2008
    Date of Patent: October 8, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Kyle P. Hunt, Leila Elvira Noriega, Billy Alan Wofford, Asadd M. Hosein, Binghua Hu, Xinfen Chen
  • Patent number: 8551836
    Abstract: A method of manufacturing a semiconductor device includes forming an insulating film over a semiconductor substrate, forming a capacitor including a lower electrode, a capacitor dielectric film including a ferroelectric material, and an upper electrode over the insulating film, forming a first protective insulating film over a side surface and upper surface of the capacitor by a sputtering method, and forming a second protective insulating film over the first protective insulating film by an atomic layer deposition method.
    Type: Grant
    Filed: May 16, 2011
    Date of Patent: October 8, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Wensheng Wang
  • Patent number: 8546265
    Abstract: A method for manufacturing a silicon structure according to the present invention includes, in a so-called dry-etching process wherein gas-switching is employed, the steps of: etching a portion in the silicon region at a highest etching rate under a high-rate etching condition such that the portion does not reach the etch stop layer; subsequently etching under a transition etching condition in which an etching rate is decreased with time from the highest etching rate in the high-rate etching condition; and thereafter, etching the silicon region under a low-rate etching condition of a lowest etching rate in the transition etching condition.
    Type: Grant
    Filed: April 8, 2009
    Date of Patent: October 1, 2013
    Assignee: SPP Technologies Co., Ltd.
    Inventors: Yoshiyuki Nozawa, Takashi Yamamoto
  • Patent number: 8536699
    Abstract: In a manufacturing process of a semiconductor device by forming a structure film on a substrate in a reaction chamber of a manufacturing apparatus, cleaning inside the reaction chamber is performed. That is, a precoat film made of a silicon nitride film containing boron is deposited on an inner wall of the reaction chamber, a silicon nitride film not containing boron is formed as the structure film on the substrate in the reaction chamber, and the inner wall of the reaction chamber is dry etched to be cleaned. At this time, the dry etching is terminated after boron is detected in a gas exhausted from the reaction chamber.
    Type: Grant
    Filed: October 13, 2011
    Date of Patent: September 17, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kenichiro Toratani, Takashi Nakao, Ichiro Mizushima
  • Patent number: 8492196
    Abstract: A semiconductor device has a plurality of semiconductor die mounted to a temporary carrier. A prefabricated shielding frame has a plate and integrated bodies extending from the plate. The bodies define a plurality of cavities in the shielding frame. A penetrable material is deposited in the cavities of the shielding frame. The shielding frame is mounted over the semiconductor die such that the penetrable material encapsulates the die. The carrier is removed. An interconnect structure is formed over the die, shielding frame, and penetrable material. The bodies of the shielding frame are electrically connected through the interconnect structure to a ground point. The shielding frame is singulated through the bodies or through the plate and penetrable material to separate the die. TIM is formed over the die adjacent to the plate of the shielding frame. A heat sink is mounted over the plate of the shielding frame.
    Type: Grant
    Filed: January 13, 2012
    Date of Patent: July 23, 2013
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Reza A. Pagaila, Yaojian Lin
  • Publication number: 20130115774
    Abstract: According to one embodiment, a method for chemical planarization includes: preparing a treatment liquid containing a hydrosilicofluoric acid aqueous solution containing silicon dioxide dissolved therein at a saturated concentration; and decreasing height of irregularity of a silicon dioxide film. In the decreasing, dissolution rate of convex portions is made larger than dissolution rate of concave portion of the irregularity while changing equilibrium state of the treatment liquid at areas being in contact with the convex portions of the irregularity, in a state in which the silicon dioxide film having the irregularity is brought into contact with the treatment liquid.
    Type: Application
    Filed: March 16, 2012
    Publication date: May 9, 2013
    Inventors: Masako Kodera, Yukiteru Matsui
  • Patent number: 8436439
    Abstract: A semiconductor device is made by forming an interconnect structure over a substrate. A semiconductor die is mounted to the interconnect structure. The semiconductor die is electrically connected to the interconnect structure. A ground pad is formed over the interconnect structure. An encapsulant is formed over the semiconductor die and interconnect structure. A shielding cage can be formed over the semiconductor die prior to forming the encapsulant. A shielding layer is formed over the encapsulant after forming the interconnect structure to isolate the semiconductor die with respect to inter-device interference. The shielding layer conforms to a geometry of the encapsulant and electrically connects to the ground pad. The shielding layer can be electrically connected to ground through a conductive pillar. A backside interconnect structure is formed over the interconnect structure, opposite the semiconductor die.
    Type: Grant
    Filed: August 30, 2010
    Date of Patent: May 7, 2013
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Reza A. Pagaila, Rui Huang, Yaojian Lin
  • Patent number: 8420543
    Abstract: A method for treating the threading dislocation within a GaN-containing semiconductor layer is provided. The method includes a substrate is provided. A GaN-containing semiconductor layer with the threading dislocation is formed on the substrate. An etching process with an etching gas is performed to remove the threading dislocation in the GaN-containing semiconductor layer so as to increase the efficiency for the light emitting device.
    Type: Grant
    Filed: January 10, 2012
    Date of Patent: April 16, 2013
    Assignee: National Chiao Tung University
    Inventors: Wei-I Lee, Yen-Hsien Yeh, Yin-Hao Wu, Tzu-Yi Yu
  • Patent number: 8389415
    Abstract: Methods and apparatus may operate to position a sample within a processing chamber and operate on a surface of the sample. Further activities may include creating a layer of reactive material in proximity with the surface, and exciting a portion of the layer of reactive material in proximity with the surface to form chemical radicals. Additional activities may include removing a portion of the material in proximity to the excited portion of the surface to a predetermined level, and continuing the creating, exciting and removing actions until at least one of a plurality of stop criteria occurs.
    Type: Grant
    Filed: August 23, 2010
    Date of Patent: March 5, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Neal R. Rueger, Mark J. Williamson, Gurtej S. Sandhu, Justin R. Arrington
  • Patent number: 8362553
    Abstract: A method includes forming elongate structures on a first substrate, such that the material composition of each elongate structure varies along its length so as to define first and second physically different sections in the elongate structures. First and second physically different devices are then defined in the elongate structures. Alternatively, the first and second physically different sections may be defined in the elongate structures after they have been fabricated. The elongate structures may be encapsulated and transferred to a second substrate. The invention provides an improved method for the formation of a circuit structure that requires first and second physically different devices to be provided on a common substrate. In particular, only one transfer step is necessary.
    Type: Grant
    Filed: April 12, 2011
    Date of Patent: January 29, 2013
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Thomas Heinz-Helmut Altebaeumer, Stephen Day, Jonathan Heffernan
  • Patent number: 8273659
    Abstract: Surface processing in which the area to be processed is restricted to a predetermined pattern, can be achieved by: (a) providing a layer of a first reagent over a region of the surface to be processed which at least covers an area of the predetermined pattern; (b) providing one or more further reagents which are further reagents required for the processing of the surface; and (c) applying at least one of the further reagents over the region to be processed according to the predetermined pattern; such that the first reagent acts with the one or more of the further reagents to process the surface only in the area of the predetermined pattern. The process is particularly applicable to etching where an etchant having two or more components is used. In that case at least a first etchant component is applied over the surface and at least one further etchant component is applied in the predetermined pattern.
    Type: Grant
    Filed: July 30, 2010
    Date of Patent: September 25, 2012
    Assignee: Newsouth Innovations PTY Limited
    Inventors: Alison Joan Lennon, Stuart Ross Wenham, Anita Wing Yi Ho-Baillie
  • Patent number: 8269318
    Abstract: A method for forming an offset spacer of a MOS device is disclosed. The method includes the steps of: providing a substrate having a gate structure thereon; forming a dielectric stack on the substrate and the gate structure, wherein the dielectric stack includes a first dielectric layer, a second dielectric layer, a third dielectric layer, and a fourth dielectric layer; and performing an etching process on the dielectric stack to form an offset spacer around the gate structure.
    Type: Grant
    Filed: May 3, 2010
    Date of Patent: September 18, 2012
    Assignee: United Microelectronics Corp.
    Inventor: Chun Rong
  • Patent number: 8193099
    Abstract: A method of forming a semiconductor device includes forming a transistor gate stack over a substrate having an active area and a shallow trench isolation (STI) region. First sidewall spacers are formed on the transistor gate stack, and an isotropic etch process is applied to isotropically remove an excess portion of a metal layer included within the transistor gate stack, the excess portion left unprotected by the first sidewall spacers. Second sidewall spacers are formed on the transistor gate stack, the second sidewall spacers completely encapsulating the metal layer of the transistor gate stack.
    Type: Grant
    Filed: March 17, 2011
    Date of Patent: June 5, 2012
    Assignee: International Business Machines Corporation
    Inventors: Mukesh V. Khare, Renee T. Mo, Ravikumar Ramachandran, Richard S. Wise, Hongwen Yan
  • Patent number: 8110879
    Abstract: Properties of a hard mask liner are used against the diffusion of a removal agent to prevent air cavity formation in specific areas of an interconnect stack. According to one embodiment, there is provided a method in which there is defined a portion on a surface of an IC interconnect stack as being specific to air cavity introduction, with the defined portion being smaller than the surface of the substrate. At least one metal track is produced within the interconnect stack, and there is deposited at least one interconnect layer having a sacrificial material and a permeable material within the interconnect stack. There is defined at least one trench area surrounding the defined portion and forming at least one trench, and a hard mask layer is deposited to coat the trench. At least one air cavity is formed below the defined portion of the surface by using a removal agent for removing the sacrificial material to which the permanent material is resistant.
    Type: Grant
    Filed: October 19, 2009
    Date of Patent: February 7, 2012
    Assignees: STMicroelectronics (Crolles 2) SAS, Koninklijke Philips Electronics N.V.
    Inventors: Joaquin Torres, Laurent-Georges Gosset
  • Patent number: 8105872
    Abstract: A semiconductor device has a plurality of semiconductor die mounted to a temporary carrier. A prefabricated shielding frame has a plate and integrated bodies extending from the plate. The bodies define a plurality of cavities in the shielding frame. A penetrable material is deposited in the cavities of the shielding frame. The shielding frame is mounted over the semiconductor die such that the penetrable material encapsulates the die. The carrier is removed. An interconnect structure is formed over the die, shielding frame, and penetrable material. The bodies of the shielding frame are electrically connected through the interconnect structure to a ground point. The shielding frame is singulated through the bodies or through the plate and penetrable material to separate the die. TIM is formed over the die adjacent to the plate of the shielding frame. A heat sink is mounted over the plate of the shielding frame.
    Type: Grant
    Filed: June 2, 2010
    Date of Patent: January 31, 2012
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Reza A. Pagaila, Yaojian Lin
  • Patent number: 8097490
    Abstract: A semiconductor die has a first semiconductor die mounted to a carrier. A plurality of conductive pillars is formed over the carrier around the first die. An encapsulant is deposited over the first die and conductive pillars. A first stepped interconnect layer is formed over a first surface of the encapsulant and first die. The first stepped interconnect layer has a first opening. A second stepped interconnect layer is formed over the first stepped interconnect layer. The second stepped interconnect layer has a second opening. The carrier is removed. A build-up interconnect structure is formed over a second surface of the encapsulant and first die. A second semiconductor die over the first semiconductor die and partially within the first opening. A third semiconductor die is mounted over the second die and partially within the second opening. A fourth semiconductor die is mounted over the second stepped interconnect layer.
    Type: Grant
    Filed: August 27, 2010
    Date of Patent: January 17, 2012
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Reza A. Pagaila, Byung Tai Do, Linda Pei Ee Chua
  • Patent number: 8084832
    Abstract: Embodiments relate to a semiconductor device and a method of manufacturing a semiconductor. In embodiments, the method may include a first exposure step of performing an exposure process for forming a first photoresist on a semiconductor substrate at one side of the outside of a trench pattern which will be formed, a first etching step of performing a predetermined dry etching method with respect to the first photoresist, a second exposure step of performing an exposure process for forming a second photoresist at the other side of the outside of the trench pattern, which is a side opposite to the first photoresist, and a second etching step of performing the predetermined dry etching method with respect to the second photoresist.
    Type: Grant
    Filed: September 15, 2009
    Date of Patent: December 27, 2011
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Young-Je Yun
  • Patent number: 8080475
    Abstract: Embodiments of the present invention describe a removal chemistry for removing hard mask. The removal chemistry is a wet-etch solution that removes a metal hard mask formed on a dielectric layer, and is highly selective to a metal conductor layer underneath the dielectric layer. The removal chemistry comprises an aqueous solution of hydrogen peroxide (H2O2), a hydroxide source, and a corrosion inhibitor. The hydrogen peroxide and hydroxide source have the capability to remove the hard mask while the corrosion inhibitor prevents the metal conductor layer from chemically reacting with the hydrogen peroxide and hydroxide source during the hard mask removal.
    Type: Grant
    Filed: January 23, 2009
    Date of Patent: December 20, 2011
    Assignee: Intel Corporation
    Inventors: Vijayakumar SubramanyaRao RamachandraRao, Kanwal Jit Singh
  • Patent number: 8071483
    Abstract: In a manufacturing process of a semiconductor device by forming a structure film on a substrate in a reaction chamber of a manufacturing apparatus, cleaning inside the reaction chamber is performed. That is, a precoat film made of a silicon nitride film containing boron is deposited on an inner wall of the reaction chamber, a silicon nitride film not containing boron is formed as the structure film on the substrate in the reaction chamber, and the inner wall of the reaction chamber is dry etched to be cleaned. At this time, the dry etching is terminated after boron is detected in a gas exhausted from the reaction chamber.
    Type: Grant
    Filed: September 22, 2009
    Date of Patent: December 6, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kenichiro Toratani, Takashi Nakao, Ichiro Mizushima
  • Patent number: 8003531
    Abstract: A method for manufacturing a flash memory device is capable of controlling a phenomenon in which a length of the channel between a source and a drain is decreased due to undercut. The method includes forming a gate electrode comprising a floating gate, an ONO film and a control gate using a hard mask pattern over a semiconductor substrate, forming a spacer over the sidewall of the gate electrode, forming an low temperature oxide (LTO) film over the entire surface of the semiconductor substrate including the gate electrode and the spacer, etching the LTO film such that a top portion of the source/drain region and a top portion of the gate electrode are exposed, and removing the LTO film present over the sidewall of the gate electrode by wet-etching.
    Type: Grant
    Filed: September 29, 2009
    Date of Patent: August 23, 2011
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Chung-Kyung Jung
  • Patent number: 7994066
    Abstract: A method is disclosed for the cleaning of a Si surface at low temperatures. Oxide on the Si surface is brought into contact with Ge, which then sublimates off the surface. The Ge contamination remaining after the oxide removal is cleared away by an exposure to an alkali halide. The disclosed cleaning method may by used in semiconductor circuit fabrication for preparing surfaces ahead of epitaxial growth.
    Type: Grant
    Filed: October 13, 2007
    Date of Patent: August 9, 2011
    Assignee: Luxtera, Inc.
    Inventors: Giovanni Capellini, Gianlorenzo Masini, Lawrence C. Gunn, III, Jeremy Witzens, Joseph W. White