Involving Dielectric Removal Step (epo) Patents (Class 257/E21.244)
  • Patent number: 10386714
    Abstract: Embodiments of the present disclosure include methods, program products, and systems for creating a knowledge base for optical proximity correction (OPC). Methods according to the disclosure can include: fabricating a circuit using a proposed IC layout; identifying a plurality of features in an image of the fabricated circuit; predicting, based on the identifying and a predictive algorithm, whether the fabricated circuit includes a printed sub-resolution assist feature (SRAF) from the proposed IC layout; determining the predicting as being correct when the fabricated circuit includes the printed SRAF, or as being incorrect when the fabricated circuit does not include the printed SRAF; in response to the predicting being incorrect: adjusting the predictive algorithm, and flagging the fabricated circuit as incorrectly predicted; in response to the predicting being correct, flagging the fabricated circuit as correctly predicted; and storing the image of the fabricated circuit in a repository of training data.
    Type: Grant
    Filed: January 9, 2017
    Date of Patent: August 20, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Kriteshwar K. Kohli, Mark N. Jobes, Ioana C. Graur
  • Patent number: 10343253
    Abstract: Methods, non-transitory computer readable media, and systems are provided for detecting an endpoint of a chemical mechanical planarization (CMP) process on a semiconductor substrate. The method comprises generating a reference signal, generating a first signal with which to control a CMP system, generating a second signal using a combination of the first signal and the reference signal, commanding the CMP system with the second signal, generating a response signal that indicates an operational characteristic of the CMP system that is responsive to the second signal and a friction property of the semiconductor substrate, and filtering the response signal using the reference signal to determine the endpoint of the CMP process.
    Type: Grant
    Filed: June 23, 2014
    Date of Patent: July 9, 2019
    Assignee: GLOBALFOUNDRIES, INC.
    Inventors: Abner Bello, Michael Wedlake
  • Patent number: 10347528
    Abstract: Methods of forming an interconnect of an IC are disclosed. The methods etch a wire trench opening partially into an ILD layer using a hard mask, and form a metal liner sidewall spacer on sidewalls of the wire trench opening, prior to etching via openings that create a via-wire opening with the wire trench opening. The metal liner sidewall spacer protects against chamfering during the via etch and/or removal of an etch stop layer over conductive structures in an underlying ILD layer. In one embodiment, a barrier liner is deposited over the metal liner sidewall spacer, creating a double layered sidewall spacer on the sidewalls of the wire trench opening portion of the via-wire opening. A conductor is deposited to form a unitary via-wire conductive structure. An interconnect includes the double layered sidewall spacer on the sidewalls of a wire trench opening portion of the via-wire conductive structure.
    Type: Grant
    Filed: March 6, 2018
    Date of Patent: July 9, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Sunil K. Singh, Ravi P. Srivastava, Sipeng Gu, Akshey Sehgal
  • Patent number: 10304694
    Abstract: A semiconductor treatment composition includes potassium, sodium, and a compound A represented by the formula (1), and has a potassium content MK (ppm) and a sodium content MNa (ppm) that satisfy MK/MNa=1×10?1 to 1×104.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: May 28, 2019
    Assignee: JSR Corporation
    Inventors: Takahiro Hayama, Yasutaka Kamei, Naoki Nishiguchi, Satoshi Kamo, Tomotaka Shinoda
  • Patent number: 10304679
    Abstract: A method of fabricating a mask includes providing a substrate. A first material layer is disposed on the substrate. Then, the first material layer is partly removed. A second trench is formed between the remaining first material layer. The second trench includes a height. Later, a second material layer is formed to conformally fill in the second trench. The second material layer includes a thickness. The thickness of the second material layer equals the height of the second trench. Finally, part of the second material layer is removed, and the remaining second material layer and the remaining first material layer comprise a second mask.
    Type: Grant
    Filed: January 22, 2018
    Date of Patent: May 28, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Chieh-Te Chen, Hsien-Shih Chu, Cheng-Yu Wang
  • Patent number: 10211281
    Abstract: In one embodiment, an isolation device has a substrate, a metal plate, a conductive layer, first and second isolation layers are disclosed. The conductive layer may be formed within the substrate. The conductive layer may be arranged coupled to the metal plate, so as to receive a capacitively coupled signal from the metal plate. The first and second isolation layers may be sandwiched between the metal plate and the conductive layer. In another embodiment, an isolation device comprising a semiconductor substrate, a topmost metal layer and a plurality of additional metal layers is disclosed. The isolation device further comprises an isolation capacitor formed using the topmost metal layer and a conductive layer coupled to at least one of the plurality of additional metal layers.
    Type: Grant
    Filed: April 8, 2015
    Date of Patent: February 19, 2019
    Assignee: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
    Inventors: Qian Tao, Fun Kok Chow
  • Patent number: 10205049
    Abstract: The present invention provides a manufacturing method for a light barrier substrate which comprising steps of: forming a metal electrode pattern on a substrate through a first patterning process; forming an insulating layer above the substrate and the metal electrode pattern; forming a metal electrode via hole on the insulating layer and forming a channel pattern for a connecting line between a metal electrode and an exterior integrated circuit (IC) on the insulating layer, with a half tone make process, through a second patterning process; forming a transparent electrode layer pattern on the substrate on which the metal electrode via hole and the channel pattern are formed.
    Type: Grant
    Filed: July 29, 2014
    Date of Patent: February 12, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE DISPLAY TECHNOLOGY CO., LTD.
    Inventors: Xiaoxiang Zhang, Zheng Liu, Zongjie Guo
  • Patent number: 10134589
    Abstract: A method of fabricating a ceramic substrate structure includes providing a ceramic substrate, encapsulating the ceramic substrate in a barrier layer, and forming a bonding layer coupled to the barrier layer. The method further includes removing a portion of the bonding layer to expose at least a portion of the barrier layer and define fill regions, and depositing a second bonding layer on the at least a portion of the exposed barrier layer and the fill regions.
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: November 20, 2018
    Assignee: Qromis, Inc.
    Inventors: Vladimir Odnoblyudov, Cem Basceri, Shari Farrens
  • Patent number: 10103034
    Abstract: A method of planarizing a substrate surface is disclosed. A substrate having a major surface of a material layer is provided. The major surface of the material layer comprises a first region with relatively low removal rate and a second region of relatively high removal rate. A photoresist pattern is formed on the material layer. The photoresist pattern masks the second region, while exposes at least a portion of the first region. At least a portion of the material layer not covered by the photoresist pattern is etched away. A polish stop layer is deposited on the material layer. A cap layer is deposited on the polish stop layer. A chemical mechanical polishing (CMP) process is performed to polish the cap layer.
    Type: Grant
    Filed: August 16, 2017
    Date of Patent: October 16, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Li-Chieh Hsu, Fu-Shou Tsai, Yu-Ting Li, Yi-Liang Liu, Kun-Ju Li
  • Patent number: 10096482
    Abstract: An apparatus and method for providing target thickness and surface profile uniformity control of a multi-head chemical mechanical polishing (CMP) process is disclosed. An exemplary method includes providing at least two wafers; determining a surface profile of each of the at least two wafers; determining an operation mode for a chemical mechanical polishing (CMP) process based on the surface profiles of the at least two wafers; determining a CMP polishing recipe for each of the at least two wafers based on the operation mode; and performing the CMP process on the at least two wafers based on the determined CMP polishing recipes.
    Type: Grant
    Filed: August 10, 2015
    Date of Patent: October 9, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Keung Hui, Jin-Ning Sung, Jong-I Mou, Soon-Kang Huang, Yen-Di Tsen
  • Patent number: 10061884
    Abstract: A dummy pattern filling method, including: Step I, determining the rule of filling dummy patterns, in accordance with required DR values and isolation rules of patterns; Step II, finding out blank Fields within said layout that need to be filled with dummy patterns; Step III, by following said rule of filling dummy patterns, filling dummy patterns within blank Fields on layouts. Implementing a Smart Dummy Pattern Filling, which enables the Data Ratio (DR) of dummy patterns to come infinitely close the required DR value after completing the filling of dummy patterns.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: August 28, 2018
    Assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corporation
    Inventors: Hualun Chen, Weiran Kong
  • Patent number: 10062581
    Abstract: A method of forming an isolation structure, wherein a hard mask is formed on a first region and a second region of a substrate; the substrate is etched using the hard mask as an etching mask to form a plurality of first active patterns in the first region and a plurality of second active patterns in the second region, a first trench between the first active patterns having a first trench width, and a second trench between the second active patterns having a second trench width smaller than the first trench width; a first oxide layer is formed on the hard mask and the first and second trenches; the first oxide layer is conformally formed on an inner wall of the first trench and filling the second trench; a polysilicon layer is conformally formed on the first oxide layer and a spin-on-dielectric (SOD) layer is formed on the polysilicon layer to fill the first trench; and the SOD layer and the polysilicon layer are annealed using an oxygen-containing gas so that the SOD layer and the polysilicon layer are transf
    Type: Grant
    Filed: April 6, 2016
    Date of Patent: August 28, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Seok-Han Park
  • Patent number: 10049938
    Abstract: Semiconductor devices, fin field effect transistor (FinFET) devices, and methods of manufacturing semiconductor devices are disclosed. In some embodiments, a semiconductor device includes a substrate comprising a first fin and a second fin. A first epitaxial fin is disposed over the first fin, and a second epitaxial fin is disposed over the second fin. The second fin is proximate the first fin. The first epitaxial fin and the second epitaxial fin have an upper portion with a substantially pillar shape.
    Type: Grant
    Filed: January 16, 2015
    Date of Patent: August 14, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Sung-Li Wang, Chih-Sheng Chang, Sey-Ping Sun
  • Patent number: 10026695
    Abstract: A semiconductor device includes a semiconductor substrate, an insulating film formed above the semiconductor substrate, a wiring having copper as a main component and formed above the insulating film, and a barrier metal film having a higher modulus of rigidity than copper and interposed between the insulating film and the wiring. The barrier metal film may have a lower thermal expansion coefficient than copper.
    Type: Grant
    Filed: May 12, 2016
    Date of Patent: July 17, 2018
    Assignee: ROHM CO., LTD.
    Inventors: Satoshi Kageyama, Bungo Tanaka
  • Patent number: 10008387
    Abstract: A low-k dielectric layer, such as SiCOH, with high and stable chemical mechanical polishing (CMP) removal rate (RR) is disclosed. The polishing rate enhancer (PRE) is disposed on the low-k dielectric layer. The PRE increases the CMP RR during CMP. Furthermore, the PRE stabilizes the increases CMP RR. This is particularly useful, for example, for memory applications in which the storage unit is formed in a low-k back-end-of-line (BEOL) dielectric layer. For example, the topography created can be quickly planarized by CMP while producing a uniform polished surface of the low-k dielectric layer due to the shortened processing time.
    Type: Grant
    Filed: February 15, 2017
    Date of Patent: June 26, 2018
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Lei Wang, Chim Seng Seet, Kai Hung Alex See
  • Patent number: 9997420
    Abstract: One or more methods or systems for performing chemical mechanical planarization (CMP) are provided. The system includes at least one of an emitter, a detector, a spectroscopic signal generator, a comparator, a spectral library, a controller or a CMP device. A spectroscopic signal is generated and is used to determine the thickness of a first material formed on or from a wafer by comparing the spectroscopic signal to a spectral library. Responsive to the thickness not being equal to the desired thickness, the controller instructs the CMP device to perform a rotation to reduce the thickness of the first material. The system and method herein increase the sensitivity of the CMP, such that the thickness of the first material is reduced with greater accuracy and precision, as compared to where the thickness is not measured between consecutive rotations of a wafer.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: June 12, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Yen-Di Tsen, Cheng Yen-Wei, Jong-I Mou
  • Patent number: 9997562
    Abstract: A method of forming a semiconductor device is disclosed. The method includes providing a substrate comprising a circuit component formed on a substrate surface. Back-end-of-line (BEOL) processing is performed to form a plurality of inter-level dielectric (ILD) layers over the substrate. A storage unit in the memory region of the via level of an ILD level. A cell dielectric layer is formed over the storage unit. The cell dielectric layer comprises a step structure created by an elevated topography of the memory region relative to the non-memory region of the via level. The elevated topography is defined by the storage unit. Chemical mechanical polishing (CMP) process is performed on the cell dielectric layer to remove the step structure of the cell dielectric layer and form a planar cell dielectric top surface extending uniformly across the memory region and the non-memory region of the via level.
    Type: Grant
    Filed: March 14, 2017
    Date of Patent: June 12, 2018
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Lei Wang, Benfu Lin, Chim Seng Seet, Kai Hung Alex See
  • Patent number: 9997348
    Abstract: A method of forming a semiconductor wafer includes generating a stress topography model of a semiconductor wafer with a plurality of desired structures in a desired layout. The method also includes determining a topography and calculating a compensation pattern based upon the topography, wherein the compensation pattern balances wafer topography. The method also includes patterning a semiconductor front side with the plurality of desired microstructures in the desired layout. The method also includes patterning the semiconductor back side with a compensation block mask corresponding to the compensation pattern.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: June 12, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Timothy A. Brunner, Oleg Gluschenkov, Donghun Kang, Byeong Y. Kim
  • Patent number: 9983257
    Abstract: The present disclosure relates to a substrate having test line letters that are used to identify a test line on an integrated chip, while avoiding contamination of high-k metal gate processes, and a method of formation. In some embodiments, an integrated chip is disclosed. The integrated chip has a semiconductor substrate. A test line letter is arranged over the semiconductor substrate. The test line letter comprises a positive relief that protrudes outward from the semiconductor substrate in the shape of an alpha-numeric character. One or more dummy structures are arranged over the semiconductor substrate. The one or more dummy structures are proximate to a boundary of the test line letter.
    Type: Grant
    Filed: October 15, 2015
    Date of Patent: May 29, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei Cheng Wu, Jui-Tsung Lien, Fang-Lan Chu, Hong-Da Lin, Ku-Ning Chang, Yu-Chen Wang
  • Patent number: 9947546
    Abstract: A semiconductor integrated circuit device and a method of manufacturing the same are disclosed. A semiconductor wafer having a surface step is prepared. A first material layer is formed on an upper surface of the semiconductor wafer so that a protrusion is formed in a portion thereof corresponding to an edge region of the semiconductor wafer. A second material layer is formed on the first material layer.
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: April 17, 2018
    Assignee: SK hynix Inc
    Inventors: Jae Hee Sim, Min Seok Son, Keun Kyu Kong, Jeong Hoon An
  • Patent number: 9934995
    Abstract: This process includes steps: a) providing a carrier substrate including a receiving face; b) depositing a nonstick coating on the receiving face, the nonstick coating including a central region and a peripheral region; and c) trimming the carrier substrate so as to remove the peripheral region of the nonstick coating and to form a recess on the periphery of the carrier substrate, in order to obtain the handle wafer. Also relates to a process for temporarily bonding a substrate to a handle wafer fabricated using the process described above. Furthermore relates to a handle wafer fabricated using the process described above.
    Type: Grant
    Filed: December 15, 2014
    Date of Patent: April 3, 2018
    Assignee: COMMISSARIAT À L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Pierre Montmeat, Laurent Bally, Frank Fournel, Michel Pellat
  • Patent number: 9919402
    Abstract: A practical method of polishing a wafer that can reduce wafer loss due to dummy polishing, and stabilize the LPD count in production wafers at a low level, is provided. In the method of polishing a wafer according to the present disclosure, a wafer 104 is brought into contact with a polishing cloth 112 provided on the surface of a polishing plate 110, and the wafer 104 and the polishing plate 110 are rotated, thereby performing several rounds of a polishing process on the surface of the wafer 104 using the same polishing cloth 112. At this time, the contact angle of the polishing cloth is measured, and based on the measured value thereof, the timing for a switchover from an initial polishing (or a dummy polishing) mode to a production polishing mode is determined.
    Type: Grant
    Filed: June 24, 2014
    Date of Patent: March 20, 2018
    Assignee: SUMCO CORPORATION
    Inventor: Tomonori Kawasaki
  • Patent number: 9917057
    Abstract: In one aspect, a method of forming a wiring layer on a wafer is provided which includes: depositing a HSQ layer onto the wafer; cross-linking a first portion(s) of the HSQ layer using e-beam lithography; depositing a hardmask material onto the HSQ layer; patterning the hardmask using optical lithography, wherein the patterned hardmask covers a second portion(s) of the HSQ layer; patterning the HSQ layer using the patterned hardmask in a manner such that i) the first portion(s) of the HSQ layer remain and ii) the second portion(s) of the HSQ layer covered by the patterned hardmask remain, wherein by way of the patterning step trenches are formed in the HSQ layer; and filling the trenches with a conductive material to form the wiring layer on the wafer.
    Type: Grant
    Filed: November 28, 2016
    Date of Patent: March 13, 2018
    Assignee: International Business Machines Corporation
    Inventors: Josephine B. Chang, Szu-Lin Cheng, Isaac Lauer, Jeffrey W. Sleight
  • Patent number: 9908718
    Abstract: Device and process for picking up a formable and/or collapsible part (30) that employs the forces of a vacuum (44) and generally distributes the vacuum force uniformly over a large portion of the surface of the part (30). The device preferably provides support for the part (30) at regular intervals, for example using a distributor plate (14) having many small openings (26). The device preferably employs a porous layer (12) such as an open cell foam between the distributor plate (14) and the part (30). The porous layer (12) may perform for one or any combination of the following: further distribute the vacuum forces, cushion the part (30) against the distributor plate (14), or further distribute the support for the part (30).
    Type: Grant
    Filed: March 6, 2013
    Date of Patent: March 6, 2018
    Assignee: DOW GLOBAL TECHNOLOGIES LLC
    Inventors: Mark J. Majestic, James R. Ogle
  • Patent number: 9905457
    Abstract: A method for forming an interconnect structure includes forming a patterned layer over a substrate, the patterned layer having an opening therein. A dielectric material is filled in the opening. The dielectric material has a precursor and a solvent, the solvent having a boiling point temperature greater than a precursor cross-linking temperature. A thermal treatment is performed on the dielectric material to form a dielectric layer.
    Type: Grant
    Filed: December 26, 2014
    Date of Patent: February 27, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bo-Jiun Lin, Ching-Yu Chang, Hai-Ching Chen, Tien-I Bao
  • Patent number: 9852980
    Abstract: Methods of forming an interconnect structure include depositing a first conductive material on a substrate. Aspects include subtractively etching the conductive material to form a patterned first conductive layer, and depositing a dielectric layer on interconnect structure. Aspects also include depositing a second conductive material on the dielectric layer and removing the second conductive material through the top of the second metal liner.
    Type: Grant
    Filed: January 13, 2017
    Date of Patent: December 26, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Griselda Bonilla, Samuel S. Choi, Ronald G. Filippi, Elbert E. Huang, Naftali E. Lustig, Andrew H. Simon
  • Patent number: 9773682
    Abstract: A method of planarizing a substrate surface is disclosed. A substrate having a major surface of a material layer is provided. The major surface of the material layer comprises a first region with relatively low removal rate and a second region of relatively high removal rate. A photoresist pattern is formed on the material layer. The photoresist pattern masks the second region, while exposes at least a portion of the first region. At least a portion of the material layer not covered by the photoresist pattern is etched away. A polish stop layer is deposited on the material layer. A cap layer is deposited on the polish stop layer. A chemical mechanical polishing (CMP) process is performed to polish the cap layer.
    Type: Grant
    Filed: July 5, 2016
    Date of Patent: September 26, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Li-Chieh Hsu, Fu-Shou Tsai, Yu-Ting Li, Yi-Liang Liu, Kun-Ju Li
  • Patent number: 9728415
    Abstract: A semiconductor device has a substrate including a plurality of conductive vias formed vertically and partially through the substrate. An encapsulant is deposited over a first surface of the substrate and around a peripheral region of the substrate. A portion of the encapsulant around the peripheral region is removed by a cutting or laser operation to form a notch extending laterally through the encapsulant to a second surface of the substrate opposite the first surface of the substrate. A first portion of the substrate outside the notch is removed by chemical mechanical polishing to expose the conductive vias. A second portion of the substrate is removed by backgrinding prior to or after forming the notch. The encapsulant is coplanar with the substrate after revealing the conductive vias. The absence of an encapsulant/base material interface and coplanarity of the molded substrate results in less over-etching or under-etching and fewer defects.
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: August 8, 2017
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Vinoth Kanna Chockanathan, Xing Zhao, Duk Ju Na, Chang Bum Yong
  • Patent number: 9728543
    Abstract: A method of fabricating a semiconductor structure includes the following steps. A first dummy gate structure and a second dummy gate structure are formed on a semiconductor substrate. A recess is formed next to the first and the second dummy gate structure and in the semiconductor substrate. A pair of first spacers is formed adjacent to the first dummy gate structure. A pair of second spacers is formed adjacent to the second dummy gate structure. One of the first spacers extends from a first sidewall of the first dummy gate structure to a first inner sidewall of the recess. One of the second spacers extends from a second sidewall of the second dummy gate structure to a second inner sidewall of the recess. A first isolation layer is formed on a bottom surface of the recess. A first conducting layer is formed on the first isolation layer.
    Type: Grant
    Filed: August 15, 2016
    Date of Patent: August 8, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Ming Pan, Chiang-Ming Chuang, Kun-Tsang Chuang, Po-Wei Liu, Yong-Shiuan Tsair
  • Patent number: 9679782
    Abstract: A planarization method includes at least two steps. One of the steps is to implant at least one impurity into a wafer to form a polish stop layer in the wafer. The other one of the steps is to polish a top surface of the wafer until reaching the polish stop layer.
    Type: Grant
    Filed: January 7, 2016
    Date of Patent: June 13, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Ting Yen, Ying-Ho Chen
  • Patent number: 9653343
    Abstract: A method for fabricating semiconductor device is disclosed. First, a substrate having a first region and a second region is provided, a shallow trench isolation (STI) is formed in the substrate to separate the first region and the second region, and a patterned hard mask is formed on the first region and part of the STI, in which the patterned hard mask exposes includes an opening to expose part of the STI. Next, a gas is driven-in through the exposed STI to alter an edge of the substrate on the first region.
    Type: Grant
    Filed: June 2, 2016
    Date of Patent: May 16, 2017
    Assignee: UNITED MOCIROELECTRONICS CORP.
    Inventors: Kai-Kuen Chang, Shih-Yin Hsiao, Chang-Po Hsiung
  • Patent number: 9652574
    Abstract: Techniques are disclosed for optimizing the pattern density in the circuit layout design of a circuit layer. A layer in circuit design is analyzed to define empty regions that can be filled with fill polygons (referred to hereafter as “fill” regions). Next, a pattern of fill polygons is generated. After the fill polygons have been defined, the layout design for the layer is divided into separate areas or “windows,” and a target density for each window is determined. Once this target density for the window has been determined, the fill polygons required to most closely approach this target density are generated and added to the circuit layout design. This process may be repeated with progressively different (e.g., smaller) fill polygons, until each window meets or exceeds both the specified minimum density and complies with the specified maximum density gradient.
    Type: Grant
    Filed: April 25, 2011
    Date of Patent: May 16, 2017
    Assignee: Mentor Graphics Corporation
    Inventors: Eugene Anikin, Fedor G. Pikus, Laurence W. Grodd, David A. Abercrombie, John W. Stedman
  • Patent number: 9607946
    Abstract: The present disclosure relates to a method of forming a back-end-of-the-line metallization layer. The method is performed by forming a plurality of freestanding metal layer structures (i.e., metal layer structures not surrounded by a dielectric material) on a semiconductor substrate within an area defined by a patterned photoresist layer. A diffusion barrier layer is deposited onto the metal layer structure in a manner such that the diffusion barrier layer conforms to the top and sides of the metal layer structure. A dielectric material is formed on the surface of the substrate to fill areas between metal layer structures. The substrate is planarized to remove excess metal and dielectric material and to expose the top of the metal layer structure.
    Type: Grant
    Filed: August 15, 2013
    Date of Patent: March 28, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: You-Hua Chou, Min Hao Hong, Jian-Shin Tsai, Miao-Cheng Liao, Hsiang Hsiang Ko
  • Patent number: 9589786
    Abstract: A method for polishing a polymer surface is provided by an embodiment of the present invention. The method includes: curing the polymer surface; polishing the polymer surface cured through a CMP process. By using the method for polishing a polymer surface provided by embodiments of the present invention, the mentioned problems in the prior art are solved. The uniformity of the polymer surface can be improved to <1% through a CMP process, which can meet the requirements of high density and small linewidth integration.
    Type: Grant
    Filed: April 17, 2015
    Date of Patent: March 7, 2017
    Assignee: National Center for Advanced Packaging Co., Ltd
    Inventors: Ting Li, Haiyang Gu
  • Patent number: 9558959
    Abstract: Stable aqueous polishing compositions that can selectively polish silicon nitride (SiN) films and nearly stop (or polish at very low rates) on silicon oxide films are provided herein. The compositions comprise an anionic abrasive, a nitride removal rate enhancer containing a carboxyl or carboxylate group, water, and optionally, an anionic polymer. The synergistic combination of anionic (negatively charged) abrasives and the nitride removal rate enhancer provide beneficial charge interactions with the dielectric films during CMP, a high SiN rate and selectivity enhancement (over oxide), and stable colloidal dispersed slurries.
    Type: Grant
    Filed: September 17, 2015
    Date of Patent: January 31, 2017
    Assignee: FUJIFILM PLANAR SOLUTIONS, LLC
    Inventors: Abhudaya Mishra, Luling Wang
  • Patent number: 9558960
    Abstract: A substrate processing method includes a coating step that applies a coating liquid to a substrate having a front surface on which a pattern is formed, thereby forming a coating film on the substrate, a film removing step that heats the substrate to gasify components of the coating film thereby to reduce a thickness of the film, and a film curing step that is performed after or simultaneously with the film removing step and that heats the substrate to cure the coating film through crosslinking reaction. The film removing step is performed under conditions ensuring that an average thickness of the cured coating film is not greater than 80% of an average thickness of the coating film before being subjected to the film removing step.
    Type: Grant
    Filed: December 24, 2015
    Date of Patent: January 31, 2017
    Assignee: Tokyo Electron Limited
    Inventors: Takahiro Shiozawa, Kenichi Ueda
  • Patent number: 9466565
    Abstract: A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.
    Type: Grant
    Filed: June 4, 2015
    Date of Patent: October 11, 2016
    Assignee: Intel Corporation
    Inventors: Mark T Bohr, Tahir Ghani, Nadia M. Rahhai-Orabi, Subhash M. Joshi, Joseph M. Steigerwald, Jason W. Klaus, Jack Hwang, Ryan Mackiewicz
  • Patent number: 9391200
    Abstract: Techniques and structures for controlling etch-back of a finFET fin are described. One or more layers may be deposited over the fin and etched. Etch-back of a planarization layer may be used to determine a self-limited etch height of one or more layers adjacent the fin and a self-limited etch height of the fin. Strain-inducing material may be formed at regions of the etched fin to induce strain in the channel of a finFET.
    Type: Grant
    Filed: June 18, 2014
    Date of Patent: July 12, 2016
    Assignees: STMicroelectronics, Inc., International Business Machines Corporation, GLOBALFOUNDRIES Inc.
    Inventors: Qing Liu, Xiuyu Cai, Ruilong Xie, Chun-chen Yeh
  • Patent number: 9340706
    Abstract: The invention provides chemical-mechanical polishing compositions and methods of chemically-mechanically polishing a substrate with the chemical-mechanical polishing compositions. The polishing compositions comprise first abrasive particles, wherein the first abrasive particles are ceria particles, second abrasive particles, wherein the second abrasive particles are ceria particles, surface-modified silica particles, or organic particles, a pH-adjusting agent, and an aqueous carrier. The polishing compositions also exhibit multimodal particle size distributions.
    Type: Grant
    Filed: October 10, 2013
    Date of Patent: May 17, 2016
    Assignee: Cabot Microelectronics Corporation
    Inventors: Brian Reiss, Jakub Nalaskowski, Viet Lam, Renhe Jia, Jeffrey Dysard
  • Patent number: 9330224
    Abstract: A method for manipulating a circuit design includes receiving multiple dummy cell modification parameters, selecting, by a computer processor and based on the dummy cell modification parameters, a dummy cell insertion region on a circuit design, and generating, in the dummy cell insertion region, multiple dummy cells. The method further includes selecting a first dummy cell from the dummy cells, determining, by the computer processor and based on a location of the first dummy cell, an illegal overlap with the first dummy cell, and removing, by the computer processor and from the dummy cells, the first dummy cell. The method further includes inserting, by the computer processor, on the circuit design, and after removing the first dummy cell, the dummy cells to obtain a modified circuit design, and presenting the modified circuit design.
    Type: Grant
    Filed: April 30, 2014
    Date of Patent: May 3, 2016
    Assignee: Oracle International Corporation
    Inventors: Duo Ding, Srinivas Sanivarapu, Lai-ching Lydia So, Joseph Curt Peters, Carl Alfred Shisler, Gary Lynn Fowler, Thuvan Le, Kaiwha Peng, Tao Hou, Wilson Fai Chin
  • Patent number: 9281253
    Abstract: A method of controlling polishing includes polishing a substrate at a first polishing station, monitoring the substrate with a first eddy current monitoring system to generate a first signal, determining an ending value of the first signal for an end of polishing of the substrate at the first polishing station, determining a first temperature at the first polishing station, polishing the substrate at a second polishing station, monitoring the substrate with a second eddy current monitoring system to generate a second signal, determining a starting value of the second signal for a start of polishing of the substrate at the second polishing station, determining a gain for the second polishing station based on the ending value, the starting value and the first temperature, and calculating a third signal based on the second signal and the gain.
    Type: Grant
    Filed: October 29, 2013
    Date of Patent: March 8, 2016
    Assignee: Applied Materials, Inc.
    Inventors: Kun Xu, Shih-Haur Shen, Boguslaw A. Swedek, Ingemar Carlsson, Doyle E. Bennett, Wen-Chiang Tu, Hassan G. Iravani, Tzu-Yu Liu
  • Patent number: 9003651
    Abstract: Various pattern transfer and etching steps can be used to create features. Conventional photolithography steps can be used in combination with pitch-reduction techniques to form superimposed, pitch-reduced patterns of crossing elongate features that can be consolidated into a single layer. Planarizing techniques using a filler layer and a protective layer are disclosed. Portions of an integrated circuit having different heights can be etched to a common plane.
    Type: Grant
    Filed: July 5, 2013
    Date of Patent: April 14, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Mirzafer Abatchev, David Wells, Baosuo Zhou, Krupakar Murali Subramanian
  • Patent number: 8980748
    Abstract: A substrate polishing method, a semiconductor device and a fabrication method for a semiconductor device are disclosed by which high planarization polishing can be achieved. In the substrate polishing method, two or more different slurries formed from ceria abrasive grains having different BET values from each other are used to carry out two or more stages of chemical-mechanical polishing processing of a polishing object oxide film on a substrate to flatten the polishing object film.
    Type: Grant
    Filed: January 3, 2008
    Date of Patent: March 17, 2015
    Assignee: Sony Corporation
    Inventors: Hiroko Nakamura, Takaaki Kozuki, Takayuki Enomoto, Yuichi Yamamoto
  • Patent number: 8912092
    Abstract: A method of forming a semiconductor device may include, but is not limited to, the following processes. A multi-layered structure is prepared over a semiconductor substrate. The multi-layered structure may include, but is not limited to, first and second patterns of a first insulating film, a second insulating film covering the first pattern of the first insulating film, and a first conductive film covering the second pattern of the first insulating film. The second insulating film and the first conductive film are polished under conditions that the first and second insulating films are greater in polishing rate than the first conductive film, to expose the first and second patterns of the first insulating film.
    Type: Grant
    Filed: October 19, 2011
    Date of Patent: December 16, 2014
    Assignee: PS4 Luxco S.A.R.L.
    Inventor: Kyoko Miyata
  • Patent number: 8895446
    Abstract: A method includes forming a plurality of trenches extending from a top surface of a semiconductor substrate into the semiconductor substrate, with semiconductor strips formed between the plurality of trenches. The plurality of trenches includes a first trench and second trench wider than the first trench. A first dielectric material is filled in the plurality of trenches, wherein the first trench is substantially fully filled, and the second trench is filled partially. A second dielectric material is formed over the first dielectric material. The second dielectric material fills an upper portion of the second trench, and has a shrinkage rate different from the first shrinkage rate of the first dielectric material. A planarization is performed to remove excess second dielectric material. The remaining portions of the first dielectric material and the second dielectric material form a first and a second STI region in the first and the second trenches, respectively.
    Type: Grant
    Filed: February 18, 2013
    Date of Patent: November 25, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Tang Peng, Tai-Chun Huang, Hao-Ming Lien
  • Patent number: 8828841
    Abstract: A system and method for forming an isolation trench is provided. An embodiment comprises forming a trench and then lining the trench with a dielectric liner. Prior to etching the dielectric liner, an outgassing process is utilized to remove any residual precursor material that may be left over from the deposition of the dielectric liner. After the outgassing process, the dielectric liner may be etched, and the trench may be filled with a dielectric material.
    Type: Grant
    Filed: January 13, 2014
    Date of Patent: September 9, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Tang Peng, Bing-Hung Chen, Tze-Liang Lee, Hao-Ming Lien
  • Patent number: 8722545
    Abstract: A method of forming a transistor is disclosed, in which gate-to-substrate leakage is addressed by forming and maintaining a conformal oxide layer overlying the transistor gate. Using the method disclosed for an n-type device, the conformal oxide layer can be formed as part of the source-drain doping process. Subsequent removal of residual phosphorous dopants from the surface of the oxide layer is accomplished without significant erosion of the oxide layer. The removal step uses a selective deglazing process that employs a hydrolytic reaction, and an acid-base neutralization reaction that includes an ammonium hydroxide component.
    Type: Grant
    Filed: August 27, 2012
    Date of Patent: May 13, 2014
    Assignee: STMicroelectronics Pte Ltd.
    Inventors: Hong-Gap Chua, Yee-Chung Chan, Mei-Yu Muk
  • Patent number: 8647986
    Abstract: A semiconductor process includes the following steps. A first gate structure and a second gate structure are formed on a substrate, wherein the top of the first gate structure includes a cap layer, so that the vertical height of the first gate structure is higher than the vertical height of the second gate structure. An interdielectric layer is formed on the substrate. A first chemical mechanical polishing process is performed to expose the top surface of the cap layer. A second chemical mechanical polishing process is performed to expose the top surface of the second gate structure or an etching process is performed to remove the interdielectric layer located on the second gate structure. A second chemical mechanical polishing process is then performed to remove the cap layer.
    Type: Grant
    Filed: August 30, 2011
    Date of Patent: February 11, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Po-Cheng Huang, Teng-Chun Tsai, Chia-Lin Hsu, Chun-Wei Hsu, Yen-Ming Chen, Chih-Hsun Lin, Chang-Hung Kung
  • Patent number: 8637403
    Abstract: A method of manufacturing a semiconductor structure includes varying local chemical mechanical polishing (CMP) abrading rates of an insulator film by selectively varying a carbon content of the insulator film.
    Type: Grant
    Filed: December 12, 2011
    Date of Patent: January 28, 2014
    Assignee: International Business Machines Corporation
    Inventors: Yoba Amoah, Graham M. Bates, Joseph P. Hasselbach, Thomas L. McDevitt, Eva A. Shah
  • Patent number: 8551886
    Abstract: A method for semiconductor processing is provided wherein a workpiece having an underlying body and a plurality of features extending therefrom, is provided. A first set of the plurality of features extend from the underlying body to a first plane, and a second set of the plurality features extend from the underlying body to a second plane. A protection layer overlies each of the plurality of features and an isolation layer overlies the underlying body and protection layer, wherein the isolation has a non-uniform first oxide density associated therewith. The isolation layer anisotropically etched based on a predetermined pattern, and then isotropically etched, wherein a second oxide density of the isolation layer is substantially uniform across the workpiece. The predetermined pattern is based, at least in part, on a desired oxide density, a location and extension of the plurality of features to the first and second planes.
    Type: Grant
    Filed: April 9, 2008
    Date of Patent: October 8, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Kyle P. Hunt, Leila Elvira Noriega, Billy Alan Wofford, Asadd M. Hosein, Binghua Hu, Xinfen Chen