Abstract: A dresser is enabled to adjust a swing speed in scanning areas set on a polishing member along a swing direction. A surface height of the polishing member in monitoring areas set in advance on the polishing member along the swing direction of the dresser is measured. A dress model matrix defined from the monitoring areas, the scanning areas and a dress model is created. Height profile predicted value is calculated using the dress model and the swing speed in each scanning area or a staying time. Evaluation index is set based on a difference from a target value of a height profile of the polishing member and a step of setting the swing speed in each scanning area of the dresser based on the evaluation index. At least one of parameters to determine the target value or the evaluation index of the height profile is made to change automatically.

Abstract: A polishing liquid containing: abrasive grains; a first nitrogen-containing compound; a second nitrogen-containing compound; and water, in which the first nitrogen-containing compound contains at least one selected from the group consisting of (I) a compound having an aromatic ring containing one nitrogen atom in the ring and a hydroxyl group, (II) a compound having an aromatic ring containing one nitrogen atom in the ring and a functional group containing a nitrogen atom, (III) a compound having a 6-membered ring containing two nitrogen atoms in the ring, (IV) a compound having a benzene ring and a ring containing a nitrogen atom in the ring, and (V) a compound having a benzene ring to which two or more functional groups containing a nitrogen atom are bonded, and an HLB value of the second nitrogen-containing compound is 7 or more.

Abstract: One variation of a method for autonomously scanning and processing a part includes: accessing a part model representing a part positioned in a work zone adjacent a robotic system; retrieving a sanding head translation speed; retrieving a toolpath for execution on the part defining positions, orientations, and target forces applied by the sanding head to the part. The method includes traversing the sanding head along the toolpath, at the sanding head translation speed; reading a sequence of applied forces from a force sensor coupled to the sanding head at positions along the toolpath; and deviating from the toolpath to maintain the set of applied forces within a threshold difference of a sequence of target forces along the toolpath. In one variation of the method, the robotic system executes a toolpath at a duration less than target duration by selectively varying target force and sanding head translation speed across the part.

Abstract: A composition suitable for chemical mechanical polishing a substrate can comprise abrasive particles, a multi-valent metal borate, at least one oxidizer and a solvent. The composition can polish a substrate with a high material removal rate and a very smooth surface finish.

Abstract: Methods and systems for IC photomask patterning are described. In some embodiments, a method includes inserting a dummy region in an IC design layout, the IC design layout includes an active region, and the active region and the dummy region is separated by a first distance. The method further includes performing one or more operations on the IC design layout, and the active region and the dummy region is separated by a second distance substantially less than the first distance. The method further includes performing a dummy region size reduction on the IC design layout to increase the second distance to a third distance substantially greater than the second distance, and the third distance is substantially greater than a minimum feature size to be patterned by a photolithography tool. The method further includes forming a photomask using the IC design layout.

Abstract: A method includes planarizing a protective layer over gate materials overlying a recessed region in a substrate. The planarizing includes forming a first planarized surface by planarizing a sacrificial layer over the protective layer, and forming a second planarized surface of the protective layer by etching the first planarized surface of the sacrificial layer at an even rate across the recessed region. An etch mask layer is formed over the second planarized surface, and control gate stacks are formed in the recessed region by etching the gate materials.

Abstract: There is provided a semiconductor device comprising a semiconductor substrate having an active area in which a plurality of active elements are formed, and a non-active area excepting the active area; at least one electrode pad electrically connected to any of the active elements. At least one Through Silicon VIA electrode is formed, being electrically connected to the electrode pad by way of the non-active area. The non-active area has an insulating region obtained by forming an insulating film on the semiconductor substrate, and a dummy section obtained by leaving a base material of the semiconductor substrate in the insulating region. The dummy section is provided in a position where an outer edge of the Through Silicon VIA electrode does not intersect with the boundary between the insulating region and the dummy section.

Abstract: A semiconductor device including a substrate including a chip region and an edge region; integrated circuit elements on the chip region; an interlayer insulating layer covering the integrated circuit elements; an interconnection structure on the interlayer insulating layer and having a side surface on the edge region; a first and second conductive pattern on the interconnection structure, the first and second conductive patterns being electrically connected to the interconnection structure; a first passivation layer covering the first and second conductive patterns and the side surface of the interconnection structure; and a second passivation layer on the first passivation layer, wherein the second passivation layer includes an insulating material different from the first passivation layer, and, between the first and second conductive patterns, the second passivation layer has a bottom surface that is located at a vertical level lower than a top surface of the first conductive pattern.

Abstract: A layout file for an integrated circuit has drawn geometries. Variable fill geometries are added to local areas based on densities of the drawn geometries in windows associated with the local areas and on the global density of all the drawn geometries in the layout file. Each window has a separate local area associated with it. The densities of the variable fill geometries in the local areas are not all equal. Densities of the fill geometries are higher in local areas associated with windows having lower densities of the drawn geometries, and for lower values of the global density. The layout file is stored in a computer-readable medium which may be used to produce a photomask for manufacturing an integrated circuit.

Abstract: A method of automatically determining optimum recipe parameters constituting an operation recipe of an optical film-thickness measuring device within a short period of time is disclosed. The method includes storing in a memory a plurality of parameter sets each including a plurality of recipe parameters constituting an operation recipe; performing simulation of change in film thickness with polishing time with use of the plurality of parameter sets and data of reference spectra of reflected light from a polished substrate, the reference spectra being stored in a data server; inputting at least one index value for evaluating a manner of the change in film thickness into an evaluation calculation formula to calculate a plurality of comprehensive evaluation values for the plurality of parameter sets; and selecting an optimum one of the plurality of parameter sets based on the plurality of comprehensive evaluation values.

Abstract: A planarization method includes forming a dielectric layer over a polish stop layer. The dielectric layer is polished until reaching the polish stop layer, and the polished dielectric layer has a concave top surface. A compensation layer is formed over the concave top surface. The compensation layer is polished.

Abstract: Provided is a polishing apparatus and polishing method which can preferably adjust a temperature of a surface of a polishing pad. A polishing apparatus includes: a polishing table configured to be rotatable, and to support the polishing pad; a substrate configured to hold an object to be polished, and to press the object to be polished against the polishing pad; a polishing liquid supplying portion configured to supply a polishing liquid to a polishing surface; a polishing liquid removing portion configured to remove the polishing liquid from the polishing surface; and a temperature adjuster configured to adjust a temperature of the polishing surface. In a rotating direction of the polishing table, the polishing liquid supplying portion, a polishing region where the object to be polished is pressed against the polishing surface by the substrate, the polishing liquid removing portion, and the temperature adjuster are disposed in this order.

Abstract: A method of fabricating an object using an additive manufacturing system includes receiving data indicative of a desired shape of the object to be fabricated by droplet ejection. The desired shape defines a profile including a top surface and one or more recesses. Data indicative of a pattern of dispensing feed material is generated to at least partially compensate for distortions of the profile caused by the additive manufacturing system, and a plurality of layers of the feed material are dispensed by droplet ejection in accordance to the pattern.

Abstract: A semiconductor device includes a substrate having a circuit region and a peripheral region disposed around and enclosing the circuit region in a plan view, a first interconnect layer formed on the substrate, a second interconnect layer formed on the first interconnect layer, a third interconnect layer formed on the second interconnect layer, and a guard ring formed in the peripheral region, wherein the guard ring includes a first interconnect formed in the first interconnect layer, and disposed around and enclosing the circuit region in a plan view, a second interconnect formed in the third interconnect layer, and disposed around and enclosing the circuit region in a plan view, and a first via connected to the first interconnect and to the second interconnect, and disposed in a groove shape along a perimeter edge of the substrate in a plan view.

Abstract: A display device with a narrow bezel is provided. The display device includes a pixel circuit and a driver circuit which are provided on the same plane. The driver circuit includes a selection circuit and a buffer circuit. The selection circuit includes a first transistor. The buffer circuit includes a second transistor. The first transistor has a region overlapping with the second transistor. One of a source and a drain of the first transistor is electrically connected to a gate of the second transistor. One of a source and a drain of the second transistor is electrically connected to the pixel circuit.

Abstract: A method for disassembling a stack of at least three substrates. The invention relates to the techniques for transferring thin films in the microelectronics field. It proposes a method for disassembling a stack of at least three substrates having between them two interfaces, one interface of which has an adhesion energy and an interface of which has an adhesion energy, with less than, the method comprising: 1) implementing a removal of material on the first substrate, in order to expose a surface of the second substrate, 2) transferring the stack onto a flexible adhesive film so that the surface has, with an adhesive layer of the film, an adhesion energy greater than, and 3) disassembling the third substrate at the interface between the second substrate and the third substrate. The method makes it possible to open the stack via the interface thereof with the highest adhesion energy.

Abstract: A probe includes a first rod having a first axis and a second rod having a second axis. A first end of the first rod is connected to a first end of the second rod to form an angle that maintains a “total internal reflection” effect for waves propagating through the probe. A second end of the second rod includes a prong facilitating attachment of the probe to a housing block. The first axis and the second axis define a plane. A second end of the first rod includes a tapered face formed perpendicular to the plane. The tapered face is sufficiently flat to make planar contact with a portion of a component under study. A support is formed in the plane and connected to the second rod. A second end of the support includes a connector to facilitate attachment of the probe to the housing block.

Abstract: In a method for manufacturing a semiconductor device, a dielectric layer is formed over a substrate. A first pattern and a second pattern are formed in the first interlayer dielectric layer. The first pattern has a width greater than a width of the second pattern. A first metal layer is formed in the first pattern and the second pattern. A second metal layer is formed in the first pattern. A planarization operation is performed on the first and second metal layers so that a first metal wiring by the first pattern and a second metal wiring by the second pattern are formed. A metal material of the first metal layer is different from a metal material of the second metal layer. The first metal wiring includes the first and second metal layers and the second metal wiring includes the first metal layer but does not include the second metal layer.

Abstract: Provided is a polishing apparatus and polishing method which can preferably adjust a temperature of a surface of a polishing pad. A polishing apparatus includes: a polishing table configured to be rotatable, and to support the polishing pad; a substrate configured to hold an object to be polished, and to press the object to be polished against the polishing pad; a polishing liquid supplying portion configured to supply a polishing liquid to a polishing surface; a polishing liquid removing portion configured to remove the polishing liquid from the polishing surface; and a temperature adjuster configured to adjust a temperature of the polishing surface. In a rotating direction of the polishing table, the polishing liquid supplying portion, a polishing region where the object to be polished is pressed against the polishing surface by the substrate, the polishing liquid removing portion, and the temperature adjuster are disposed in this order.

Abstract: An ultrasonic inspection system includes an ultrasonic sensor and a control device. The ultrasonic sensor has a piezoelectric element that transmits and receives ultrasonic waves and plate portions and that are arranged so as to contact an upper surface of the piezoelectric element and have different thicknesses. The control device acquires a propagation time of a reflected wave reflected on an upper surface of the plate portion, calculates a sound velocity of the plate portion using the propagation time of the reflected wave and a thickness of the plate portion, and corrects a sound velocity of a pipe and acquires a sound velocity of the plate portion based on the calculated sound velocity. In addition, the control device acquires a propagation time of a reflected wave reflected on an upper surface of the plate portion, and calibrates a time axis based on the propagation time of the reflected wave, a thickness of the plate portion, and the sound velocity of the plate portion.

Abstract: In one embodiment, a semiconductor manufacturing apparatus includes a polishing table configured to hold a polishing pad, a polishing head configured to hold a substrate to be polished by the polishing pad, and a polishing liquid feeder configured to feed a polishing liquid to the polishing pad. The apparatus further includes a heat exchanger configured to be placed on the polishing pad and control temperatures of the polishing pad and the polishing liquid, and one or more protruding portions provided on a side face or a bottom face of the heat exchanger.

Abstract: A substrate for microelectronic radiofrequency devices includes a carrier substrate made of a first semiconductor material having a resistivity higher than 500 ohms-cm; a plurality of trenches in the carrier substrate, which trenches are filled with a second material, and defining on a first side of the carrier substrate a plurality of first zones made of a first material and at least one second zone made of a second material. The second material has a resistivity higher than 10 kohms-cm, and the first zones have a maximum dimension smaller than 10 microns and are insulated from one another by the second zone.

Abstract: Disclosed is a semiconductor device comprising a substrate including a first region and a second region, a first gate pattern on the substrate of the first region, and a second gate pattern on the substrate of the second region. The first gate pattern comprises a first high-k dielectric pattern, a first N-type metal-containing pattern, and a first P-type metal-containing pattern that are sequentially stacked. The second gate pattern comprises a second high-k dielectric pattern and a second P-type metal-containing pattern that are sequentially stacked.

Abstract: Disclosed are an apparatus and a method for treating a substrate. The method includes repeatedly rotating the substrate alternately at a first speed and at a second speed while the treatment liquid is supplied, and the second speed is higher than the first speed.

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a first gate, a gate dielectric layer, a pair of second gates, a first spacer, and a second spacer. The first gate is disposed on a substrate. The gate dielectric layer is disposed between the first gate and the substrate. The pair of second gates are disposed on the substrate and respectively located at two sides of the first gate, wherein top surfaces of the pair of second gates are higher than a top surface of the first gate. The first spacer is disposed on sidewalls of the pair of second gates protruding from the top surface of the first gate and covers the top surface of the first gate. The second spacer is disposed between the gate dielectric layer and the pair of second gates, between the first gate and the pair of second gates, and between the first spacer and the pair of second gates.

Abstract: An exemplary semiconductor device includes first spacers disposed along sidewalls of a first gate structure and second spacers disposed along sidewalls of a second gate structure. A source/drain region is disposed between the first gate structure and the second gate structure. A first ILD layer is disposed between the first spacers and the second spacers. A portion of the first ILD layer has a first recessed upper surface. A dielectric layer is disposed over the first spacers, the second spacers, and the first recessed upper surface of the first ILD layer. A portion of the dielectric layer has a second recessed upper surface that is disposed over the portion of the first ILD layer having the first recessed upper surface. A second ILD layer is disposed over the dielectric layer. A contact extends through the second ILD layer, the dielectric layer, and the first ILD layer to the source/drain region.

Abstract: A method of manufacturing a semiconductor package structure includes the following steps. A die is bonded to a wafer. A dielectric material layer is formed on the wafer and the die. The dielectric material layer covers a top surface and sidewalls of the die. At least one planarization process is performed to remove a portion of the dielectric material layer and a portion of the die, such that the top surface of the die is exposed and a dielectric layer aside the die is formed. The dielectric layer surrounds and covers the sidewalls of the die.

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to overlay mark structures and methods of manufacture. The method includes: forming an overlay mark within a layer of a stack of layers; increasing a density of an upper layer of the stack of layers, above the layer, the increased density protecting the overlay mark; and polishing the upper layer or one or more layers above the upper layer of the stack of layers.

Abstract: Techniques disclosed herein provide a method for continued patterning of substrates having sub-resolution features. Techniques include using novel deposition and removal techniques. This results in a substrate with inter-digitated photoresist in which photoresist is positioned between structures on a given substrate. Combined with using extreme ultraviolet lithographic exposure, patterning techniques herein can make desired cuts and blocks at specified locations on the substrate.

Abstract: A method for filling patterns includes the steps of: providing a substrate having a cell region defined thereon; forming main patterns on the substrate and within the cell region; and filling first dummy patterns adjacent to the main patterns. Preferably, each of the first dummy patterns comprises a first length along X-direction between 2 ?m to 5 ?m and a second length along Y-direction between 3 ?m to 5 ?m.

Abstract: Conformal hermetic dielectric films suitable as dielectric diffusion barriers over 3D topography. In embodiments, the dielectric diffusion barrier includes a dielectric layer, such as a metal oxide, which can be deposited by atomic layer deposition (ALD) techniques with a conformality and density greater than can be achieved in a conventional silicon dioxide-based film deposited by a PECVD process for a thinner contiguous hermetic diffusion barrier. In further embodiments, the diffusion barrier is a multi-layered film including a high-k dielectric layer and a low-k or intermediate-k dielectric layer (e.g., a bi-layer) to reduce the dielectric constant of the diffusion barrier. In other embodiments a silicate of a high-k dielectric layer (e.g., a metal silicate) is formed to lower the k-value of the diffusion barrier by adjusting the silicon content of the silicate while maintaining high film conformality and density.

Abstract: A substrate processing system comprising a polishing part, a pre-cleaning region, and a cleaning part. The polishing part performs a Chemical Mechanical Polishing (CMP) process on a substrate. The pre-cleaning region is prepared in the polishing part and allows pre-cleaning performed on the substrate having undergone the polishing process. The cleaning part cleans the substrate pre-cleaned in the pre-cleaning region.

Abstract: A method of producing a substrate having an alignment mark includes a process of forming a lower layer side metal film on a substrate and forming a lower layer side alignment mark base having a lower layer side alignment mark that is a hole, a process of forming an upper layer side metal film on the substrate and the lower layer side metal film, a process of forming a photoresist film on the upper layer side metal film and forming a lower layer side alignment mark overlapping portion overlapping a part of the lower layer side alignment mark with patterning, an etching process of removing with etching selectively portions of the lower and upper layer side metal films not overlapping the lower layer side alignment mark overlapping portion and forming an upper layer side alignment mark that is the upper layer side metal film, and a photoresist removing process.

Abstract: A method for patterning a semiconductor structure is provided, including forming an additional third material layer on a thinner portion of a second material layer to be an etching buffer layer. The removed thickness of the thinner portion of the second material layer covered by the third material layer during an etching back process is therefore reduced.

Abstract: Embodiments of the present disclosure include methods, program products, and systems for creating a knowledge base for optical proximity correction (OPC). Methods according to the disclosure can include: fabricating a circuit using a proposed IC layout; identifying a plurality of features in an image of the fabricated circuit; predicting, based on the identifying and a predictive algorithm, whether the fabricated circuit includes a printed sub-resolution assist feature (SRAF) from the proposed IC layout; determining the predicting as being correct when the fabricated circuit includes the printed SRAF, or as being incorrect when the fabricated circuit does not include the printed SRAF; in response to the predicting being incorrect: adjusting the predictive algorithm, and flagging the fabricated circuit as incorrectly predicted; in response to the predicting being correct, flagging the fabricated circuit as correctly predicted; and storing the image of the fabricated circuit in a repository of training data.

Abstract: Methods, non-transitory computer readable media, and systems are provided for detecting an endpoint of a chemical mechanical planarization (CMP) process on a semiconductor substrate. The method comprises generating a reference signal, generating a first signal with which to control a CMP system, generating a second signal using a combination of the first signal and the reference signal, commanding the CMP system with the second signal, generating a response signal that indicates an operational characteristic of the CMP system that is responsive to the second signal and a friction property of the semiconductor substrate, and filtering the response signal using the reference signal to determine the endpoint of the CMP process.

Abstract: Methods of forming an interconnect of an IC are disclosed. The methods etch a wire trench opening partially into an ILD layer using a hard mask, and form a metal liner sidewall spacer on sidewalls of the wire trench opening, prior to etching via openings that create a via-wire opening with the wire trench opening. The metal liner sidewall spacer protects against chamfering during the via etch and/or removal of an etch stop layer over conductive structures in an underlying ILD layer. In one embodiment, a barrier liner is deposited over the metal liner sidewall spacer, creating a double layered sidewall spacer on the sidewalls of the wire trench opening portion of the via-wire opening. A conductor is deposited to form a unitary via-wire conductive structure. An interconnect includes the double layered sidewall spacer on the sidewalls of a wire trench opening portion of the via-wire conductive structure.

Abstract: A semiconductor treatment composition includes potassium, sodium, and a compound A represented by the formula (1), and has a potassium content MK (ppm) and a sodium content MNa (ppm) that satisfy MK/MNa=1×10?1 to 1×104.

Abstract: A method of fabricating a mask includes providing a substrate. A first material layer is disposed on the substrate. Then, the first material layer is partly removed. A second trench is formed between the remaining first material layer. The second trench includes a height. Later, a second material layer is formed to conformally fill in the second trench. The second material layer includes a thickness. The thickness of the second material layer equals the height of the second trench. Finally, part of the second material layer is removed, and the remaining second material layer and the remaining first material layer comprise a second mask.

Abstract: In one embodiment, an isolation device has a substrate, a metal plate, a conductive layer, first and second isolation layers are disclosed. The conductive layer may be formed within the substrate. The conductive layer may be arranged coupled to the metal plate, so as to receive a capacitively coupled signal from the metal plate. The first and second isolation layers may be sandwiched between the metal plate and the conductive layer. In another embodiment, an isolation device comprising a semiconductor substrate, a topmost metal layer and a plurality of additional metal layers is disclosed. The isolation device further comprises an isolation capacitor formed using the topmost metal layer and a conductive layer coupled to at least one of the plurality of additional metal layers.

Abstract: The present invention provides a manufacturing method for a light barrier substrate which comprising steps of: forming a metal electrode pattern on a substrate through a first patterning process; forming an insulating layer above the substrate and the metal electrode pattern; forming a metal electrode via hole on the insulating layer and forming a channel pattern for a connecting line between a metal electrode and an exterior integrated circuit (IC) on the insulating layer, with a half tone make process, through a second patterning process; forming a transparent electrode layer pattern on the substrate on which the metal electrode via hole and the channel pattern are formed.

Abstract: A method of fabricating a ceramic substrate structure includes providing a ceramic substrate, encapsulating the ceramic substrate in a barrier layer, and forming a bonding layer coupled to the barrier layer. The method further includes removing a portion of the bonding layer to expose at least a portion of the barrier layer and define fill regions, and depositing a second bonding layer on the at least a portion of the exposed barrier layer and the fill regions.

Abstract: A method of planarizing a substrate surface is disclosed. A substrate having a major surface of a material layer is provided. The major surface of the material layer comprises a first region with relatively low removal rate and a second region of relatively high removal rate. A photoresist pattern is formed on the material layer. The photoresist pattern masks the second region, while exposes at least a portion of the first region. At least a portion of the material layer not covered by the photoresist pattern is etched away. A polish stop layer is deposited on the material layer. A cap layer is deposited on the polish stop layer. A chemical mechanical polishing (CMP) process is performed to polish the cap layer.

Abstract: An apparatus and method for providing target thickness and surface profile uniformity control of a multi-head chemical mechanical polishing (CMP) process is disclosed. An exemplary method includes providing at least two wafers; determining a surface profile of each of the at least two wafers; determining an operation mode for a chemical mechanical polishing (CMP) process based on the surface profiles of the at least two wafers; determining a CMP polishing recipe for each of the at least two wafers based on the operation mode; and performing the CMP process on the at least two wafers based on the determined CMP polishing recipes.

Abstract: A dummy pattern filling method, including: Step I, determining the rule of filling dummy patterns, in accordance with required DR values and isolation rules of patterns; Step II, finding out blank Fields within said layout that need to be filled with dummy patterns; Step III, by following said rule of filling dummy patterns, filling dummy patterns within blank Fields on layouts. Implementing a Smart Dummy Pattern Filling, which enables the Data Ratio (DR) of dummy patterns to come infinitely close the required DR value after completing the filling of dummy patterns.

Abstract: A method of forming an isolation structure, wherein a hard mask is formed on a first region and a second region of a substrate; the substrate is etched using the hard mask as an etching mask to form a plurality of first active patterns in the first region and a plurality of second active patterns in the second region, a first trench between the first active patterns having a first trench width, and a second trench between the second active patterns having a second trench width smaller than the first trench width; a first oxide layer is formed on the hard mask and the first and second trenches; the first oxide layer is conformally formed on an inner wall of the first trench and filling the second trench; a polysilicon layer is conformally formed on the first oxide layer and a spin-on-dielectric (SOD) layer is formed on the polysilicon layer to fill the first trench; and the SOD layer and the polysilicon layer are annealed using an oxygen-containing gas so that the SOD layer and the polysilicon layer are transf

Abstract: Semiconductor devices, fin field effect transistor (FinFET) devices, and methods of manufacturing semiconductor devices are disclosed. In some embodiments, a semiconductor device includes a substrate comprising a first fin and a second fin. A first epitaxial fin is disposed over the first fin, and a second epitaxial fin is disposed over the second fin. The second fin is proximate the first fin. The first epitaxial fin and the second epitaxial fin have an upper portion with a substantially pillar shape.

Abstract: A semiconductor device includes a semiconductor substrate, an insulating film formed above the semiconductor substrate, a wiring having copper as a main component and formed above the insulating film, and a barrier metal film having a higher modulus of rigidity than copper and interposed between the insulating film and the wiring. The barrier metal film may have a lower thermal expansion coefficient than copper.

Abstract: A low-k dielectric layer, such as SiCOH, with high and stable chemical mechanical polishing (CMP) removal rate (RR) is disclosed. The polishing rate enhancer (PRE) is disposed on the low-k dielectric layer. The PRE increases the CMP RR during CMP. Furthermore, the PRE stabilizes the increases CMP RR. This is particularly useful, for example, for memory applications in which the storage unit is formed in a low-k back-end-of-line (BEOL) dielectric layer. For example, the topography created can be quickly planarized by CMP while producing a uniform polished surface of the low-k dielectric layer due to the shortened processing time.

Abstract: A method of forming a semiconductor device is disclosed. The method includes providing a substrate comprising a circuit component formed on a substrate surface. Back-end-of-line (BEOL) processing is performed to form a plurality of inter-level dielectric (ILD) layers over the substrate. A storage unit in the memory region of the via level of an ILD level. A cell dielectric layer is formed over the storage unit. The cell dielectric layer comprises a step structure created by an elevated topography of the memory region relative to the non-memory region of the via level. The elevated topography is defined by the storage unit. Chemical mechanical polishing (CMP) process is performed on the cell dielectric layer to remove the step structure of the cell dielectric layer and form a planar cell dielectric top surface extending uniformly across the memory region and the non-memory region of the via level.