Using Mask (epo) Patents (Class 257/E21.257)
  • Patent number: 11264328
    Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method may be performed by forming a first capping layer on a dielectric structure over a substrate, and patterning the dielectric structure and the first capping layer to define cavities within the dielectric structure. A conductive material is formed within the cavities and a second capping layer is formed on the conductive material. An etch stop layer is formed along sidewalls and over an upper surface of the second capping layer. The etch stop layer has a first thickness over the first capping layer and a second thickness over the second capping layer. The first thickness is greater than the second thickness.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: March 1, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chao-Chun Wang, Su-Jen Sung
  • Patent number: 11205574
    Abstract: A method for forming a semiconductor memory structure includes forming a hard mask layer over a semiconductor substrate, etching the hard mask layer to form first mask patterns and second mask patterns, transferring the first and second mask patterns to the substrate to form semiconductor blocks, and thinning down the second mask element. After thinning down the second mask element, the thickness of the second mask elements is less than the thickness of the first mask elements. The method also includes forming a first capping layer to laterally extend over the first mask patterns and the second mask patterns, and etching the first capping layer and the second mask pattern to form contact openings.
    Type: Grant
    Filed: March 5, 2020
    Date of Patent: December 21, 2021
    Assignee: WINBOND ELECTRONICS CORP.
    Inventors: Shuen-Hsiang Ke, Shih-Chieh Lin
  • Patent number: 11189491
    Abstract: A method of forming a mask pattern and a method of fabricating a semiconductor device, the method of forming a mask pattern including providing a substrate including a plurality of patterns thereon; forming a mask material solution layer such that the mask material solution layer covers the patterns on the substrate; and applying a liquid material to remove an upper portion of the mask material solution layer, wherein the mask material solution layer includes a fluorine additive concentrated at the upper portion of the mask material solution layer.
    Type: Grant
    Filed: January 3, 2020
    Date of Patent: November 30, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chul-Ho Kim, Yool Kang, Jaesung Kang, Jinphil Choi
  • Patent number: 11107726
    Abstract: A method for manufacturing a semiconductor device is provided. A substrate is provided, where a cover layer is formed on the substrate, a wiring layer is formed in the cover layer, a layer to be etched is formed on the cover layer, and the layer to be etched includes an adhesive layer. An exposure patterned film layer is formed on the layer to be etched. A first etching hole pattern is formed in the exposure patterned film layer. The layer to be etched is etched to form a blind hole by using the exposure patterned film layer as a mask. The exposure patterned film layer is trimmed to form a second etching hole pattern. The layer to be etched is further etched to form a bonding hole by using the trimmed exposure patterned film layer as a mask. A bonding pad is formed in the bonding hole.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: August 31, 2021
    Assignee: Wuhan Xinxin Semiconductor Manufacturing Co., Ltd.
    Inventors: Yan Xie, Xuanjun Liu
  • Patent number: 11069566
    Abstract: Devices and methods that can facilitate hybrid sidewall barrier and low resistance interconnect components are provided. According to an embodiment, a device can comprise a first interconnect material layer that can have a first opening that can comprise a first discontinuous barrier liner coupled to first sidewalls of the first opening and a first continuous barrier layer coupled to the first discontinuous barrier liner and the first sidewalls. The device can further comprise a second interconnect material layer coupled to the first interconnect material layer, the second interconnect material layer can have a second opening that can comprise a second discontinuous barrier liner coupled to second sidewalls of the second opening, a second continuous barrier layer coupled to the second discontinuous barrier liner and the second sidewalls.
    Type: Grant
    Filed: October 11, 2018
    Date of Patent: July 20, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Oscar van der Straten, Koichi Motoyama, Joseph F. Maniscalco, Scott DeVries
  • Patent number: 10957668
    Abstract: The present disclosure relates to an anisotropic conductive film (ACF) with controllable distribution state of conductive substance and a manufacturing method thereof. The ACF includes: a porous template, a plurality of conductive tubes, and an insulation glue layer. A plurality of through holes are configured on the porous template and to penetrate the porous template along a thickness direction of the porous template. Each of the conductive tubes is respectively inserted into one through hole and protrudes from the through hole at both ends, and the insulation glue layer is configured to wrap at least one protruding portion of the conductive tube protruding from the porous template. As such, the distribution state of the conductive tube may be controlled by controlling the density of the through holes within the porous template during the preparation process, and the distribution state of the conductive substances in the ACF may be precisely controlled.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: March 23, 2021
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventors: Hui Li, Zhenyu Zhao, Mang Huang, Yu Sun
  • Patent number: 10923416
    Abstract: A semiconductor device includes: a first conductive structure having sidewalls and a bottom surface, the first conductive structure extending through one or more isolation layers formed on a substrate; and an insulation layer disposed between at least one of the sidewalls of the first conductive structure and respective sidewalls of the one or more isolation layers, wherein the first conductive structure is electrically coupled to a second conductive structure through at least the bottom surface.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: February 16, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chung-Liang Cheng, Shih Wei Bih, Yen-Yu Chen
  • Patent number: 10832947
    Abstract: A method is presented for forming fully aligned vias without recessing a plurality of conductive lines. The method includes forming the plurality of conductive lines within an interlayer dielectric (ILD), growing first dielectric regions in direct contact with the plurality of conductive lines, forming a capping layer over the first dielectric regions, depositing an ultra-low-k (ULK) layer over and in direct contact with the capping layer, forming a via over a conductive line of the plurality of conductive lines, and removing an exposed portion of the capping layer and an exposed first dielectric region in direct contact with the conductive line to reveal the conductive line.
    Type: Grant
    Filed: February 28, 2019
    Date of Patent: November 10, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chanro Park, Ruilong Xie, Kangguo Cheng, Juntao Li
  • Patent number: 10727056
    Abstract: A method for forming a semiconductor structure including forming a plurality of mandrel lines on a first dielectric layer and forming one or more groups of discontinuous mandrel line pairs with a first mask. The method further includes disposing a second dielectric layer, and forming dielectric spacers on sidewalls of the mandrel lines and the discontinuous mandrel line pairs. The method further includes removing the mandrel lines and the discontinuous mandrel line pairs to form spacer masks, forming one or more groups of blocked regions using a second mask, and forming openings extended through the first dielectric layer with a conjunction of the spacer masks and the second mask. The method also includes removing the spacer masks and the second mask, disposing an objective material in the openings, and forming objective lines with top surfaces coplanar with the top surfaces of the first dielectric layer.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: July 28, 2020
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Lu Ming Fan, Zi Qun Hua, Bi Feng Li, Qingchen Cao, Yaobin Feng, Zhiliang Xia, Zongliang Huo
  • Patent number: 10720491
    Abstract: Provided is a method of fabricating a semiconductor device. The method includes forming an oxide film on a target layer, forming a first mask film on the oxide film, wherein the first mask film contains a semiconductor material and has a first thickness and a first etch selectivity with respect to the oxide film, forming a second mask film on the first mask film, wherein the second mask film contains a metal and has a second thickness smaller than the first thickness and a second etch selectivity larger than the first etch selectivity with respect to the oxide film, forming a second mask film pattern by patterning the second mask film, forming a first mask film pattern by patterning the first mask film, etching some portions of the oxide film by using the second mask film pattern as an etch mask film, and etching the rest of the oxide film by using the first mask film pattern as an etch mask film to form a hole, wherein the target layer is exposed via the hole.
    Type: Grant
    Filed: May 22, 2019
    Date of Patent: July 21, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jun Ho Yoon, Won Chul Lee, Sung Yeon Kim, Jae Hong Park, Chan Hoon Park, Yong Moon Jang, Je Woo Han
  • Patent number: 10672701
    Abstract: Discussed generally herein are methods and devices for flexible fabrics or that otherwise include thin traces. A device can include a flexible polyimide material, and a first plurality of traces on the flexible polyimide material, wherein the first plurality of traces are patterned on the flexible polyimide material using laser spallation.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: June 2, 2020
    Assignee: Intel Corporation
    Inventors: Vivek Raghunathan, Yonggang Li, Aleksandar Aleksov, Adel A. Elsherbini, Johanna M. Swan
  • Patent number: 10636901
    Abstract: A method for producing a substrate for a metal-oxide-semiconductor field-effect transistor or a micro-electromechanical system includes dry etching a preliminary trench into the substrate by using a structured first masking layer. The substrate includes a silicon carbide layer, and the dry etching is carried out in such a way that a remnant of the first structured masking layer remains. The method further includes applying a second masking layer at least to walls of the preliminary trench and dry etching by using the remnant of the first masking layer and the second masking layer so as to produce a trench with a step in the trench.
    Type: Grant
    Filed: August 7, 2014
    Date of Patent: April 28, 2020
    Assignee: Robert Bosch GmbH
    Inventors: Achim Trautmann, Christian Tobias Banzhaf
  • Patent number: 10593872
    Abstract: According to one embodiment, an insulating layer is formed on a substrate. A hole is formed in the insulating layer. A metal layer is formed in the hole to fill the hole. A surface of the insulating layer and a surface of the metal layer is removed by etching with ion beams having a first angle, which etches both the insulating layer and the metal layer at a first etching rate. A resistance change element is formed on the metal layer.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: March 17, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yasuyuki Sonoda, Bo Kyoung Jung
  • Patent number: 10541143
    Abstract: Methods and architectures for self-aligned build-up of patterned features. An initial patterned feature aspect ratio may be maintained or increased, for example to mitigate erosion of the feature during one or more subtractive device fabrication processes. A patterned feature height may be increased without altering an effective spacing between adjacent features that may be further relied upon, for example to further pattern an underlying material. A patterned feature may be conformally capped with a material, such as a metal or dielectric, in a self-aligned manner, for example to form a functional device layer on an initial pattern having a suitable space width-to-line height aspect ratio without the use of a masked etch to define the cap.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: January 21, 2020
    Assignee: Intel Corporation
    Inventors: Leonard P. Guler, Nick Lindert
  • Patent number: 10410920
    Abstract: A semiconductor structure includes a semiconductor substrate having fins and gate structures on the fins. A protective layer is formed on top surfaces of the gate structures. Sidewall spacers are formed on side surfaces of the gate structures and the protective layer. A first dielectric layer is formed on the surface of the semiconductor substrate and covering the fins and the side surfaces of the sidewall spacers. A mask layer is formed on a portion of the first dielectric layer between adjacent gate structures. The mask layer and the protective layer are formed by etching a mask material layer. A second dielectric layer is formed on the first dielectric layer, the protective layer and the sidewall spacers and covering the side surfaces of the mask layer. Conductive vias are formed in the first dielectric layer between the adjacent gate structures and at both sides of the mask layer.
    Type: Grant
    Filed: April 20, 2018
    Date of Patent: September 10, 2019
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Chenglong Zhang, Haiyang Zhang
  • Patent number: 10355030
    Abstract: A display panel and a display apparatus are provided. The display panel includes: a substrate; multiple first-layer wires disposed on the substrate; and an insulating dielectric layer disposed on the first-layer wires. A dielectric constant of the insulating dielectric layer is higher than dielectric constants of silicon oxide layer and silicon nitride layer. The insulating dielectric layer includes a composition. The composition includes a first component and a second component. A dielectric constant of the first component is lower than the dielectric constants of silicon oxide layer and silicon nitride layer. A dielectric constant of the second component is higher than the dielectric constants of silicon oxide layer and silicon nitride layer.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: July 16, 2019
    Assignees: HKC CORPORATION LIMITED, CHONGQING HKC OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: En-Tsung Cho, Kun Fan, Yiqun Tian
  • Patent number: 10319805
    Abstract: Provided is a method of fabricating a semiconductor device. The method includes forming an oxide film on a target layer, forming a first mask film on the oxide film, wherein the first mask film contains a semiconductor material and has a first thickness and a first etch selectivity with respect to the oxide film, forming a second mask film on the first mask film, wherein the second mask film contains a metal and has a second thickness smaller than the first thickness and a second etch selectivity larger than the first etch selectivity with respect to the oxide film, forming a second mask film pattern by patterning the second mask film, forming a first mask film pattern by patterning the first mask film, etching some portions of the oxide film by using the second mask film pattern as an etch mask film, and etching the rest of the oxide film by using the first mask film pattern as an etch mask film to form a hole, wherein the target layer is exposed via the hole.
    Type: Grant
    Filed: June 19, 2017
    Date of Patent: June 11, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jun Ho Yoon, Won Chul Lee, Sung Yeon Kim, Jae Hong Park, Chan Hoon Park, Yong Moon Jang, Je Woo Han
  • Patent number: 10304871
    Abstract: A display panel and a manufacturing method are provided. The display panel includes a substrate, multiple active switches disposed on the substrate and a low dielectric constant protective layer. The low dielectric constant protective layer is formed on the numerous active switches. A relative dielectric constant of the low dielectric constant protective layer is smaller than a relative dielectric constant of silicon nitride.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: May 28, 2019
    Assignees: HKC CORPORATION LIMITED, CHONGQING HKC OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: En-Tsung Cho, Kun Fan, Yiqun Tian
  • Patent number: 10210971
    Abstract: A chip component includes a chip component main body, an electrode pad formed on a top surface of the main body, a protective film covering the top surface of the main body and having a contact hole exposing the pad, and an external connection electrode electrically connected to the pad via the hole and having a protruding portion, which, in a plan view looking from a direction perpendicular to a top surface of the pad, extends to a top surface of the film and protrudes further outward than a region of contact with the pad over the full periphery of an edge portion of the hole. A method for manufacturing the component includes forming the pad on the main body's top surface, forming the protective film, forming the hole in the film so as to expose the pad, and forming the electrode electrically connected to the pad via the hole.
    Type: Grant
    Filed: April 18, 2017
    Date of Patent: February 19, 2019
    Assignee: ROHM CO., LTD.
    Inventors: Hiroshi Tamagawa, Hiroki Yamamoto, Katsuya Matsuura, Yasuhiro Kondo
  • Patent number: 10163652
    Abstract: The present disclosure provides a method for forming patterns in a semiconductor device. In accordance with some embodiments, the method includes providing a substrate and a patterning-target layer formed over the substrate; forming a first cut pattern in a first hard mask layer formed over the patterning-target layer; forming a second cut pattern in a second hard mask layer formed over the patterning layer, the first hard mask layer having a different etching selectivity from the second hard mask layer; selectively removing a portion of the second cut pattern in the second hard mask layer and a portion of the patterning-target layer within a first trench; and selectively removing a portion of the first cut pattern in the first hard mask layer and a portion of the patterning-target layer within a second trench.
    Type: Grant
    Filed: July 18, 2014
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Shih-Ming Chang
  • Patent number: 10103113
    Abstract: A step of forming bump pads on the surface of the substrate corresponding to the cavity region, and covering the whole surface with a second insulating layer, forming a copper barrier on the surface of a second insulating layer corresponding to the cavity region for protection of the second insulating layer, forming a third insulating layer, and forming a copper layer for electrical circuit. A mask is formed on the copper later of the external circuit so that only the cavity region is exposed. The cavity is formed by laser-drilling only the surface-exposed area of the third insulating layer. The bottom copper layer protects the second insulating layer and bump pads underneath from laser damages. The copper barrier is removed by chemical etch after the laser drill. The second insulating layer with the bottom surface exposed will be removed via sand blast process, exposing the bump pads fabricated.
    Type: Grant
    Filed: June 3, 2016
    Date of Patent: October 16, 2018
    Assignee: DAEDUCK ELECTRONICS CO., LTD.
    Inventors: Young-Joo Ko, Tae-Hyuk Ko, Hyeung-Do Lee
  • Patent number: 9899259
    Abstract: A method for forming a gate tie-down includes opening up a cap layer and recessing gate spacers on a gate structure to expose a gate conductor; forming inner spacers on the gate spacers; etching contact openings adjacent to sides of the gate structure down to a substrate below the gate structures; and forming trench contacts on sides of the gate structure. An interlevel dielectric (ILD) is deposited on the gate conductor and the trench contacts and over the gate structure. The ILD is opened up to expose the trench contact on one side of the gate structure and the gate conductor. A second conductive material provides a self-aligned contact down to the trench contact on the one side and to form a gate contact down to the gate conductor and a horizontal connection within the ILD over an active area between the gate conductor and the self-aligned contact.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: February 20, 2018
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES INC.
    Inventors: Su Chen Fan, Andre P. Labonte, Lars W. Liebmann, Sanjay C. Mehta
  • Patent number: 9799651
    Abstract: A semiconductor structure includes a substrate, a first gate structure, a first spacer, a source/drain structure, a conductor, and a contact etch stop layer. The first gate structure is present on the substrate. The first spacer is present on at least one sidewall of the first gate structure, in which the first spacer has a top portion and a bottom portion between the top portion and the substrate. The source/drain structure is present adjacent to the bottom portion of the first spacer. The conductor is electrically connected to the source/drain structure. The protection layer is present at least between the conductor and the top portion of the first spacer. The contact etch stop layer is present at least partially between the conductor and the bottom portion of the first spacer while absent between the protection layer and the top portion of the first spacer.
    Type: Grant
    Filed: March 18, 2016
    Date of Patent: October 24, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng
  • Patent number: 9779943
    Abstract: A hard mask is formed into lines and bridges two adjacent lines using mandrels, spacers for the mandrels and a lithographic process for each bridge to create a metal line pattern in a layer of an interconnect structure with a line pitch below lithographic resolution.
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: October 3, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Guillaume Bouche, Jason Eugene Stephens
  • Patent number: 9773671
    Abstract: Provided is a material composition and method for inhibiting the printing of SRAFs onto a substrate including coating a substrate with a resist layer. After coating the substrate, the resist layer is patterned to form a main feature pattern and at least one sub-resolution assist feature (SRAF) pattern within the resist layer. The main feature pattern may include resist sidewalls and a portion of a layer underlying the patterned resist layer. In various examples, a material composition is deposited over the patterned resist layer and into each of the main feature pattern and the at least one SRAF pattern. Thereafter, a material composition development process is performed to dissolve a portion of the material composition within the main feature pattern and to expose the portion of the layer underlying the patterned resist layer.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: September 26, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Meng-Tze Chen, Chen-Hau Wu, Meng-Wei Chen, Kuei-Shun Chen, Yu-Chin Huang, Li-Hsiang Lai, Shih-Ming Chang, Ken-Hsien Hsieh
  • Patent number: 9704647
    Abstract: A transformer comprising primary and secondary windings is disclosed. Each winding has first and second metal capping layers coupled together electrically in parallel by a metal connector passing through a substrate lying between the first and second metal capping layers.
    Type: Grant
    Filed: April 7, 2015
    Date of Patent: July 11, 2017
    Assignee: NXP B.V.
    Inventors: Magali Duplessis, Olivier Tesson
  • Patent number: 9691590
    Abstract: Systems and methods for processing a substrate include arranging a substrate including a film layer on a substrate support in a processing chamber. The film layer includes a boron doped carbon hard mask. A plasma gas mixture is supplied and includes molecular hydrogen, nitrogen trifluoride, and a gas selected from a group consisting of carbon dioxide and nitrous oxide. Plasma is struck in the processing chamber or supplied to the processing chamber for a predetermined stripping period. The plasma strips the film layer during the predetermined stripping period and the plasma is extinguished.
    Type: Grant
    Filed: June 9, 2016
    Date of Patent: June 27, 2017
    Assignee: LAM RESEARCH CORPORATION
    Inventor: David T. Mattson
  • Patent number: 9685404
    Abstract: A BEOL e-fuse is disclosed which reliably blows in the via and can be formed even in the tightest pitch BEOL layers. The BEOL e-fuse can be formed utilizing a line first dual damascene process to create a sub-lithographic via to be the programmable link of the e-fuse. The sub-lithographic via can be patterned using standard lithography and the cross section of the via can be tuned to match the target programming current.
    Type: Grant
    Filed: January 11, 2012
    Date of Patent: June 20, 2017
    Assignee: International Business Machines Corporation
    Inventors: Junjing Bao, Griselda Bonilla, Kaushik Chanda, Samuel S. Choi, Ronald Filippi, Stephan Grunow, Naftali E. Lustig, Dan Moy, Andrew H. Simon
  • Patent number: 9634029
    Abstract: A thin film transistor (TFT) substrate includes a substrate which is a flexible substrate, and a TFT structure disposed on the substrate and including a gate layer, a gate insulator layer, a first channel island and a second channel island. The gate layer is disposed on the substrate and including a first gate electrode and a second gate electrode electrically connected to each other. The first and second gate electrodes are parts of the same TFT structure. The gate insulator layer covers the first and second gate electrodes. The first and second channel islands are disposed on the gate insulator layer and respectively correspond to the first and second gate electrodes. The source and drain layer is disposed on the gate insulator layer and next to the first and second channel islands, wherein the source and drain layer partially covers top surfaces of the first and second channel islands.
    Type: Grant
    Filed: June 16, 2015
    Date of Patent: April 25, 2017
    Assignee: E INK HOLDINGS INC.
    Inventors: Kai-Cheng Chuang, Chao-Jung Chen, I-Hsuan Chiang
  • Patent number: 9567483
    Abstract: A method of manufacturing a display apparatus and a display apparatus manufactured by using (utilizing) the method.
    Type: Grant
    Filed: October 13, 2014
    Date of Patent: February 14, 2017
    Assignee: Samsung Display Co., Ltd.
    Inventors: Koichi Sugitani, Hoon Kang, Jae-Sung Kim, Jin-Ho Ju, Jin-Young Choi
  • Patent number: 9570355
    Abstract: A method of making a semiconductor device includes depositing a hard mask on a dielectric layer on a substrate, the dielectric layer being disposed around first, second, and third gates; removing a portion of the hard mask to form an opening that exposes the first, second, and third gates; forming a patterned soft mask on the first, second, and third gates within the opening, a first portion of the patterned soft mask being disposed on the first and second gates, and a second portion of the patterned soft mask being disposed on the second and third gates; removing portions of the dielectric layer to transfer the pattern of the patterned soft mask into the dielectric layer and form first and second contact openings between the first and second gates, and third and fourth contact openings between the second and third gates; and disposing a conductive material in the contact openings.
    Type: Grant
    Filed: August 23, 2016
    Date of Patent: February 14, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Veeraraghavan S. Basker
  • Patent number: 9558934
    Abstract: Embodiments of the present invention provide hydrogen-free dielectric films and methods of fabrication. A hydrogen-free precursor, such as tetraisocyanatosilane, and hydrogen-free reactants, such as nitrogen, oxygen (O2/O3) and nitrous oxide are used with chemical vapor deposition processes (PECVD, thermal CVD, SACVD, HDP CVD, and PE and Thermal ALD) to create hydrogen-free dielectric films. In some embodiments, there are multilayer dielectric films with sublayers of various materials such as silicon oxide, silicon nitride, and silicon oxynitride. In embodiments, the hydrogen-free reactants may include Tetra Isocyanato Silane, along with a hydrogen-free gas including, but not limited to, N2, O2, O3, N2O, CO2, CO and a combination thereof of these H-Free gases. Plasma may be used to enhance the reaction between the TICS and the other H-free gasses. The plasma may be controlled during film deposition to achieve variable density within each sublayer of the films.
    Type: Grant
    Filed: October 28, 2015
    Date of Patent: January 31, 2017
    Assignee: International Business Machines Corporation
    Inventors: Donald Francis Canaperi, Alfred Grill, Sanjay C. Mehta, Son Van Nguyen, Deepika Priyadarshini, Hosadurga Shobha, Matthew T. Shoudy
  • Patent number: 9491866
    Abstract: Provided is a method for manufacturing a printed circuit board. The method for manufacturing a printed circuit board includes preparing an insulation board, irradiating a laser onto a graytone mask to each a surface of the insulation board, thereby forming a circuit pattern groove and a via hole at the same time, and filling the circuit pattern groove and the via hole to form a buried circuit pattern and the via. Thus, the circuit pattern groove and the via hole may be formed using the graytone mask at the same time without perfolining a separate process for forming the via hole. Therefore, the manufacturing process may be simplified to reduce the manufacturing costs.
    Type: Grant
    Filed: July 7, 2011
    Date of Patent: November 8, 2016
    Assignee: LG INNOTEK CO., LTD.
    Inventors: Sang Myung Lee, Byeong Ho Kim, Jin Su Kim, Myoung Hwa Nam, Yeong Uk Seo, Sung Woon Yoon
  • Patent number: 9490210
    Abstract: An interconnection structure fabrication method is provided. The method includes providing a substrate; forming a conductive film with a first thickness and having a first lattice structure and a first grain size, wherein the first thickness is greater than the first grain size; and performing an annealing process to change the first lattice structure of the conductive film to a second lattice structure and to change the first grain size to a second grain size. The second grain size is greater than the first grain size, and the first thickness is greater than or equal to the second grain size. The method also includes etching portion of the conductive film to form at least one conductive layer; etching portion of the conductive layer to form at least one trench having a depth smaller than the first thickness in the conductive layer to form an electrical interconnection wire and conductive vias; and forming a dielectric layer covering the substrate, sidewalls of the conductive layer, and the trench.
    Type: Grant
    Filed: March 13, 2015
    Date of Patent: November 8, 2016
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventor: Zhongshan Hong
  • Patent number: 9449812
    Abstract: Embodiments of the present invention provide hydrogen-free dielectric films and methods of fabrication. A hydrogen-free precursor, such as tetraisocyanatosilane, and hydrogen-free reactants, such as nitrogen, oxygen (O2/O3) and nitrous oxide are used with chemical vapor deposition processes (PECVD, thermal CVD, SACVD, HDP CVD, and PE and Thermal ALD) to create hydrogen-free dielectric films. In some embodiments, there are multilayer dielectric films with sublayers of various materials such as silicon oxide, silicon nitride, and silicon oxynitride. In embodiments, the hydrogen-free reactants may include Tetra Isocyanato Silane, along with a hydrogen-free gas including, but not limited to, N2, O2, O3, N2O, CO2, CO and a combination thereof of these H-Free gases. Plasma may be used to enhance the reaction between the TICS and the other H-free gasses. The plasma may be controlled during film deposition to achieve variable density within each sublayer of the films.
    Type: Grant
    Filed: November 2, 2015
    Date of Patent: September 20, 2016
    Assignee: International Business Machines Corporation
    Inventors: Donald Francis Canaperi, Alfred Grill, Sanjay C. Mehta, Son Van Nguyen, Deepika Priyadarshini, Hosadurga Shobha, Matthew T. Shoudy
  • Patent number: 9368444
    Abstract: A method for creating structures in a semiconductor assembly is provided. The method includes etching apertures into a dielectric layer and applying a polymer layer over the dielectric layer. The polymer layer is applied uniformly and fills the apertures at different rates depending on the geometry of the apertures, or on the presence or absence of growth accelerating material. The polymer creates spacers for the etching of additional structure in between the spacers. The method is capable of achieving structures smaller than current lithography techniques.
    Type: Grant
    Filed: December 30, 2014
    Date of Patent: June 14, 2016
    Assignee: Micron Technology, Inc.
    Inventor: Gurtej Sandhu
  • Patent number: 9330964
    Abstract: A method is provided for fabricating a semiconductor structure. The method includes providing a substrate; and forming a to-be-etched layer made of porous low dielectric constant material on one surface of the semiconductor substrate. The method also includes forming a first hard mask layer made of nitrogen-doped silicon oxycarbide (SiOC(N)) on the to-be-etched layer; and etching the first hard mask layer to have patterns corresponding to positions of subsequently formed openings. Further, the method includes forming the plurality of openings without substantial undercut between the to-be-etched layer and the first hard mask layer in the to-be-etched layer using the first hard mask layer as an etching mask; and forming a conductive structure in each of the openings.
    Type: Grant
    Filed: December 26, 2013
    Date of Patent: May 3, 2016
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventor: Ming Zhou
  • Patent number: 9184059
    Abstract: A method of fabricating a semiconductor device includes the steps of providing a hard mask cover using a patterned photoresist layer, wherein the patterned photoresist layer comprises at least four first holes arranged in two rows and two columns. Part of the hard mask is removed to form at least four second holes by taking the pattered photoresist layer as a mask. Next, each of the first holes is widened, and the widened first holes and the second holes are filled up by a filler. Later, the patterned photoresist layer is removed entirely. Part of the hard mask is removed to form at least a fourth hole by taking the filler as a mask. Finally, the filler is removed entirely.
    Type: Grant
    Filed: March 21, 2014
    Date of Patent: November 10, 2015
    Assignee: INOTERA MEMORIES, INC.
    Inventor: Kuo-Yao Chou
  • Patent number: 8975189
    Abstract: A method of forming a fine pattern comprises depositing a modifying layer on a substrate. A photoresist layer is deposited on the modifying layer, the photoresist layer having a first pattern. The modifying layer is etched according to the first pattern of the photoresist layer. A treatment is performed to the etched modifying layer to form a second pattern, the second pattern having a smaller line width roughness (LWR) and/or line edge roughness (LER) than the first pattern. The second pattern is then etched into the substrate.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: March 10, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih Wei Lu, Chung-Ju Lee, Tien-I Bao
  • Patent number: 8969207
    Abstract: One illustrative method disclosed herein includes forming a patterned hard mask layer comprised of a plurality of discrete openings above a structure, wherein the patterned hard mask layer is comprised of a plurality of intersecting line-type features, forming a patterned etch mask above the patterned hard mask layer that exposes at least one, but not all, of the plurality of discrete openings, and performing at least one etching process through the patterned etch mask and the at least one exposed opening in the patterned hard mask layer to define an opening in the structure.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: March 3, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Gerard M. Schmid, Jeremy A. Wahl, Richard A. Farrell, Chanro Park
  • Patent number: 8940643
    Abstract: A method of lithography patterning includes forming a first etch stop layer, a second etch stop layer, and a hard mask layer on a material layer. The materials of the first etch stop layer and the second etch stop layer are selected by the way that there is a material gradient composition between the second etch stop layer, the first etch stop layer, and the material layer. Hence, gradient etching rates between the second etch stop layer, the first etch stop layer, and the material layer are achieved in an etching process to form etched patterns with smooth and/or vertical sidewalls within the second and the first etch stop layers and the material layer.
    Type: Grant
    Filed: August 20, 2013
    Date of Patent: January 27, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Chi Ko, Chih-Hao Chen, Keng-Chu Lin
  • Patent number: 8932961
    Abstract: An illustrative test structure is disclosed herein that includes a plurality of first line features and a plurality of second line features. In this embodiment, each of the second line features have first and second opposing ends and the first and second line features are arranged in a grating pattern such that the first ends of the first line features are aligned to define a first side of the grating structure and the second ends of the first features are aligned to define a second side of the grating structure that is opposite the first side of the grating structure. The first end of the second line features has a first end that extends beyond the first side of the grating structure while the second end of the second line features has a first end that extends beyond the second side of the grating structure.
    Type: Grant
    Filed: February 13, 2012
    Date of Patent: January 13, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Sohan Mehta, Tong Qing Chen, Vikrant Chauhan, Ravi Srivastava, Catherine Labelle, Mark Kelling
  • Patent number: 8906810
    Abstract: An all-in-one trench-over-via etch wherein etching of a low-k material beneath a metal hard mask of titanium nitride containing material is carried out in alternating steps of (a) etching the low-k material while maintaining chuck temperature at about 45 to 80° C. and (b) metal hard mask rounding and Ti-based residues removal while maintaining chuck temperature at about 90 to 130° C.
    Type: Grant
    Filed: May 7, 2013
    Date of Patent: December 9, 2014
    Assignee: Lam Research Corporation
    Inventors: Ananth Indrakanti, Bhaskar Nagabhirava, Alan Jensen, Tom Choi
  • Patent number: 8896002
    Abstract: A method for producing a semiconductor laser having an edge window structure includes the steps of forming masks of insulating films on a nitride-based III-V compound semiconductor substrate including first regions and second regions periodically arranged in parallel therebetween; and growing a nitride-based III-V compound semiconductor layer in a region not covered by the masks. The first region between each two adjacent second regions has two or more positions, symmetrical with respect to a center line thereof, where laser stripes are to be formed. The masks are formed on one or both sides of each of the positions where the laser stripes are to be formed at least near a position where edge window structures are to be formed such that the masks are symmetrical with respect to the center line. The nitride-based III-V compound semiconductor layer includes an active layer containing at least indium and gallium.
    Type: Grant
    Filed: September 29, 2009
    Date of Patent: November 25, 2014
    Assignee: Sony Corporation
    Inventors: Rintaro Koda, Masaru Kuramoto, Eiji Nakayama, Tsuyoshi Fujimoto
  • Patent number: 8883646
    Abstract: The present disclosure is directed to a process for the fabrication of a semiconductor device. In some embodiments the semiconductor device comprises a patterned surface. The pattern can be formed from a self-assembled monolayer. The disclosed process provides self-assembled monolayers which can be deposited quickly, thereby increasing production throughput and decreasing cost, as well as providing a pattern having substantially uniform shape.
    Type: Grant
    Filed: August 6, 2012
    Date of Patent: November 11, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Min Huang, Chung-Ju Lee, Chien-Hua Huang
  • Patent number: 8871645
    Abstract: Semiconductor devices suitable for narrow pitch applications and methods of fabrication thereof are described herein. In some embodiments, a semiconductor device may include a floating gate having a first width proximate a base of the floating gate that is greater than a second width proximate a top of the floating gate. In some embodiments, a method of shaping a material layer may include (a) oxidizing a surface of a material layer to form an oxide layer at an initial rate; (b) terminating formation of the oxide layer when the oxidation rate is about 90% or below of the initial rate; (c) removing at least some of the oxide layer by an etching process; and (d) repeating (a) through (c) until the material layer is formed to a desired shape. In some embodiments, the material layer may be a floating gate of a semiconductor device.
    Type: Grant
    Filed: September 11, 2009
    Date of Patent: October 28, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Udayan Ganguly, Yoshita Yokota, Jing Tang, Sunderraj Thirupapuliyur, Christopher Sean Olsen, Shiyu Sun, Tze Wing Poon, Wei Liu, Johanes Swenberg, Vicky U. Nguyen, Swaminathan Srinivasan, Jacob Newman
  • Patent number: 8853087
    Abstract: A target space ratio of a monitor pattern on a substrate for inspection is determined to be different from a ratio of 1:1. A range of space ratios in a library is determined to include the target space ratio and not include a space ratio of 1:1. The monitor pattern is formed on a film to be processed by performing predetermined processes on the substrate for inspection. Sizes of the monitor pattern are measured. The sizes of the monitor pattern are converted into sizes of a pattern of the film to be processed having a space ratio of 1:1, and processing conditions of the predetermined processes are compensated for based on the sizes of the converted pattern of the film to be processed. After that, the predetermined processes are performed on a wafer under the compensated conditions to form a pattern having a space ratio of 1:1 on the film to be processed.
    Type: Grant
    Filed: December 17, 2010
    Date of Patent: October 7, 2014
    Assignee: Tokyo Electron Limited
    Inventors: Keisuke Tanaka, Machi Moriya
  • Patent number: 8853085
    Abstract: A method for defining a template for directed self-assembly (DSA) materials includes patterning a resist on a stack including an ARC and a mask formed over a hydrophilic layer. A pattern is formed by etching the ARC and the mask to form template lines which are trimmed to less than a minimum feature size (L). Hydrophobic spacers are formed on the template lines and include a fractional width of L. A neutral brush layer is grafted to the hydrophilic layer. A DSA material is deposited between the spacers and annealed to form material domains in a form of alternating lines of a first and a second material wherein the first material in contact with the spacers includes a width less than a width of the lines. A metal is added to the domains forming an etch resistant second material. The first material and the spacers are removed to form a DSA template pattern.
    Type: Grant
    Filed: April 23, 2013
    Date of Patent: October 7, 2014
    Assignee: International Business Machines Corporation
    Inventors: Jassem A. Abdallah, Matthew E. Colburn, Steven J. Holmes, Chi-Chun Liu
  • Patent number: 8835324
    Abstract: In an exemplary method for forming contact holes, a substrate overlaid with an etching stop layer and an interlayer dielectric layer in that order is firstly provided. A first etching process then is performed to form at least a first contact opening in the interlayer dielectric layer. A first carbon-containing dielectric layer subsequently is formed overlying the interlayer dielectric layer and filling into the first contact opening. After that, a first anti-reflective layer and a first patterned photo resist layer are sequentially formed in that order overlying the carbon-containing dielectric layer. Next, a second etching process is performed by using the first patterned photo resist layer as an etching mask to form at least a second contact opening in the interlayer dielectric layer.
    Type: Grant
    Filed: July 1, 2011
    Date of Patent: September 16, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Chieh-Te Chen, Yi-Po Lin, Feng-Yih Chang, Chih-Wen Feng, Shang-Yuan Tsai
  • Patent number: 8785325
    Abstract: According to one embodiment, a method of manufacturing a semiconductor device, the method includes forming first and second cores on a processed material, forming a covering material having a stacked layer includes first and second layers, the covering material covering an upper surface and a side surface of the first and second cores, removing the second layer covering the first core, forming a first sidewall mask having the first layer on the side surface of the first core and a second sidewall mask having the first and second layers on the side surface of the second core by etching the covering material, removing the first and second cores, and forming first and second patterns having different width in parallel by etching the processed material in condition of using the first and second sidewall masks.
    Type: Grant
    Filed: September 15, 2011
    Date of Patent: July 22, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Gaku Sudo