Abstract: A method of making a semiconductor device includes forming a first photoresist layer over an underlying layer, patterning the first photoresist layer into a first photoresist pattern, wherein the first photoresist pattern comprises a plurality of spaced apart first photoresist features located over the underlying layer, and etching the underlying layer using the first photoresist pattern as a mask to form a plurality of first spaced apart features. The method further includes removing the first photoresist pattern, forming a second photoresist layer over the plurality of first spaced apart features, and patterning the second photoresist layer into a second photoresist pattern, wherein the second photoresist pattern comprises a plurality of second photoresist features covering edge portions of the plurality of first spaced apart features.

Abstract: A method of self-aligned dual patterning is described. The method includes first providing a substrate having a stack of films thereon. A template mask is then formed above the stack of films. A liner layer is formed above the stack of films and conformal with the template mask. A spacer-forming material layer is formed over and conformal with the liner layer. The spacer-forming material layer is then etched to form a spacer mask and to exose a portion of the liner layer. The exposed portion of the liner layer and the template mask are then removed. Finally, an image of the spacer mask is transferred to the stack of films.

Abstract: A method of forming a thin film pattern includes: forming a thin film on a substrate; forming an amorphous carbon layer including first and second carbon layers on the thin film, wherein the first carbon layer is formed by one of a spin-on method and a plasma enhanced chemical vapor deposition (PECVD) method and the second carbon layer is formed by a physical vapor deposition (PVD) method; forming a hard mask layer on the amorphous carbon layer; forming a PR pattern on the hard mask layer; forming a hard mask pattern by etching the hard mask layer using the PR pattern as an etch mask; forming an amorphous carbon pattern including first and second carbon patterns by etching the amorphous carbon layer using the hard mask pattern as an etch mask; and forming a thin film pattern by etching the thin film using the amorphous carbon pattern.

Abstract: A photoresist resin composition, a method for forming a pattern and a method for manufacturing a display panel using the photoresist resin composition are disclosed. The photoresist resin composition includes an alkali soluble resin, a photoresist compound, and a solvent, wherein the alkali soluble resin includes a first polymer resin represented by the following Chemical Formula 1, wherein, of R1, R2, R3, R4, R5 and R6, at least one is a hydroxyl group, at least two are methyl groups and any remaining groups are hydrogen, and of R7, R8, R9, R10 and R11, at least one is a hydroxyl group, at least two are methyl groups and any remaining groups are hydrogen.

Abstract: A method of improving high aspect ratio etching by reverse masking to provide a more uniform mask height between the array and periphery is presented. A layer of amorphous carbon is deposited over a substrate. An inorganic hard mask is deposited on the amorphous carbon followed by a layer of photodefinable material which is deposited over the array portion of the substrate. The photodefinable material is removed along with the inorganic hard mask overlaying the periphery. A portion of the amorphous carbon layer is etched in the exposed periphery. The inorganic hard mask is removed and normal high aspect ratio etching continues. The amount of amorphous carbon layer remaining in the periphery results in a more uniform mask height between the array and periphery at the end of high aspect ratio etching. The more uniform mask height mitigates twisting at the edge of the array.

Abstract: By forming a hardmask layer in combination with one or more cap layers, undue exposure of a sensitive dielectric material to resist stripping etch ambients may be reduced and integrity of the hardmask may also be maintained so that the trench etch process may be performed with a high degree of etch selectivity during the patterning of openings in a metallization layer of a semiconductor device.

Abstract: A method of forming a semiconductor device includes forming a first chip region, a second chip region, and a scribe lane region between the first and second chip regions in a wafer, the wafer having a first surface and a second surface facing the first surface, and forming a penetrating extension hole and a scribe connector in the scribe lane region, the penetrating extension hole penetrating the wafer from the first surface to the second surface and extending along the scribe lane region, wherein the scribe connector connects the first and second chip regions spaced apart from each other by the penetrating extension hole.

Abstract: Techniques are disclosed for fabricating a device using a photolithographic process. The method includes providing a first anti-reflective coating over a surface of a substrate. A layer which is transparent to a wavelength of light used during the photolithographic process is provided over the first anti-reflective coating, and a photosensitive material is provided above the transparent layer. The photosensitive material is exposed to a source of radiation including the wavelength of light. Preferably, the first anti-reflective coating extends beneath substantially the entire transparent layer. The complex refractive index of the first anti-reflective coating can be selected to maximize the absorption at the first anti-reflective coating to reduce notching of the photosensitive material.

Abstract: The present invention provides a method for fabricating an embedded static random access memory, including providing a semiconductor substrate; defining a logic area and a memory cell area on the semiconductor substrate and defining at least a first conductive device area and at least a second conductive device area in the logic area and the memory cell area respectively; forming a patterned mask on the memory cell area and on the second conductive device area in the logic area and exposing the first conductive device area in the logic area; performing a first conductive ion implantation process on the exposed first conductive device area in the logic area; and removing the patterned mask.

Abstract: The present invention provides a fabrication method of an opening. The method includes providing a substrate having a conductive region therein. Thereafter, a dielectric layer is formed over the substrate and then a stacked layer is formed on the dielectric layer. The stacked layer includes a patterned metal hard mask layer, a patterned silicon oxynitride layer and a patterned silicon oxide layer on the dielectric layer in sequence. Afterward, a first portion of the dielectric layer is removed using the stacked layer as a first mask to form a first opening that exposes a surface of the conductive region.

Abstract: A method for fabricating a fine pattern in a semiconductor device includes forming a first photoresist pattern over an etch target layer, forming a first hard mask layer over a substrate structure, planarizing the first hard mask layer to form a first hard mask pattern and expose the first photoresist pattern, removing the first photoresist pattern, forming a second photoresist pattern enclosing the first hard mask pattern, forming a second hard mask layer over the substrate structure, planarizing the second hard mask layer to form a second hard mask pattern and expose the first hard mask pattern, removing the second photoresist pattern, and etching the etch target layer using the first hard mask pattern and the second hard mask pattern.

Abstract: A semiconductor device includes an interlayer insulating layer including a plurality of trenches connecting to a number of via holes formed on a semiconductor substrate including lower interconnections, wherein widths of the trenches are greater than widths of the via holes, and metal interconnections formed by burying metal thin films in the via holes and the trenches. Depths of the trenches are adjusted differently from each other depending on required resistances of the metal interconnections.

Abstract: A method of performing a double-sided process is provided. First, a wafer having a structural pattern disposed on the front surface is provided. Following that, a plurality of front scribe lines are defined on the structural pattern, and a filling layer is filled into the front scribe lines. Subsequently, the structural pattern is bonded to a carrier wafer with a bonding layer, and a plurality of back scribe lines are defined on the back surface of the wafer. Finally, the filling layer filled in the front scribe lines is removed.

Abstract: Manufacturing a semiconductor device includes defining bulb-type trenches having spherical portions in a silicon substrate. Oxide layers are formed in surfaces of spherical portions of the bulb-type trenches by conducting an oxidation process for the silicon substrate having the bulb-type trenches defined therein. An insulation layer is formed on the entire surface of the silicon substrate including the surfaces of the bulb-type trenches, which have the oxide layers formed in the surfaces of the spherical portions thereof. Isolation trenches are defined by etching the insulation layer, whereby SOI structures having the oxide layers interposed between portions of the silicon substrate are formed.

Abstract: A method of forming damascene patterns of semiconductor devices comprise forming a first insulating layer and contact plugs, formed in the first insulating layer, over a semiconductor substrate, forming an etch barrier layer and a second insulating layer over the first insulating layer, forming damascene patterns in the second insulating layer, forming a mask layer over the second insulating layer of other region except a region in which the contact plugs are formed so that the damascene patterns are exposed through the region in which the contact plugs are formed, removing the etch barrier layer under the exposed damascene patterns using an etching process employing the mask layer, and removing the mask layer.

Abstract: A method for manufacturing a semiconductor device includes forming a hard mask pattern and a spacer at both sides of the hard mask pattern. The method also includes forming a spacer pattern, so that the spacer remains in one direction to form a spacer pattern, forming a photoresist pattern having a pad type overlapping a side of the spacer pattern, and etching an underlying layer, with the photoresist pattern and the spacer pattern as a mask, to form an isolated pattern. The method improves resolution and process margins to obtain a highly-integrated transistor.

Abstract: A gate hard mask is deposited on a gate structure using low pressure chemical vapor deposition (LPCVD). By doing so, the wet etch removal ratio (WERR) of the gate hard mask relative to the underlying polysilicon gate layer is increased when compared to prior art hard masks. The LPCVD gate hard mask will not only etch faster than prior art hard masks, but it will also reduce undercutting of the gate oxide. To provide additional control of the wet etch rate, the LPCVD hard mask can be annealed. The annealing can be tailored to achieve the desired etching rate.

Abstract: Solder ball assembly for a semiconductor device and method of fabricating the same is described. In one example, a solder mask is formed on a substrate having an aperture exposing at least a portion of a conductive pad of the substrate. A solder pillar is formed in the aperture and in electrical communication with the conductive pad. An insulating layer is formed on the solder mask exposing at least a portion of the solder pillar. The exposed portion of the solder pillar is removed to define a mounting surface. A solder ball is formed on the mounting surface in electrical communication with the solder pillar. The solder pillar may include high-temperature solder having a melting point higher than that of the solder ball.

Abstract: A semiconductor device is composed of: an interconnect made of a first conductive film and a second conductive film that are stacked in sequence from the interconnect underside on an insulating film formed on a substrate; and a capacitor composed of a lower capacitor electrode made of the first conductive film, a dielectric film formed on the lower capacitor electrode, and an upper capacitor electrode made of the second conductive film and formed on the dielectric film.

Abstract: A method for manufacturing a semiconductor device, comprises forming a first film above a pattern forming material, patterning the first film to form a core material pattern, forming a second film above the pattern forming material so as to cover a side surface and an upper surface of the core material pattern, forming a third film above the second film as a protective material for the second film, etching the second and third films so that side wall sections including the second film and the third film are formed on both sides of the core material pattern and the second film and the third film of an area other than the side wall sections are removed, removing the core material pattern between the side wall sections, and transferring patterns corresponding to the side wall sections on the pattern forming material by using the side wall sections as a mask.

Abstract: System and method for direct etching. According to an embodiment, the present invention provides a method for manufacturing an integrated circuit device. The method includes a step for providing a substrate having a contact region, which is provided between a first word line and a second word line. The contact region has an overlying plug structure, which is provided within a thickness of a first dielectric layer. The first dielectric layer includes a portion overlying the plug structure. The first dielectric layer has a planarized surface region. The method also includes a step for forming a first line and a second line and a space provided between the first word line and the second world line. The space is provided within a region overlying the plug structure.

Abstract: The present invention is a method of etching a lower layer film (64) of an organic material formed on a surface layer (61) of a substrate, using an upper layer film (63) of an Si-containing organic material as a mask. A mixed gas containing an NH3 gas and an O2 gas is supplied into the processing vessel as an etching gas, so as to perform etching by a plasma of the etching gas. When the etching gas is supplied into the processing vessel, a CD shift value of etching can be controlled by adjusting a flow ratio of O2 gas to the NH3 gas. Specifically, a satisfactory CD shift value can be obtained when the flow ratio is from 0.5 to 20%, and preferably, 5 to 10%.

Abstract: Methods of forming integrated circuit devices include forming an integrated circuit substrate having an electrically insulating layer thereon and forming a mask layer pattern having at least first and second openings of different size therein, on the electrically insulating layer. First and second portions of the electrically insulating layer extending opposite the first and second openings, respectively, are simultaneously etched at first and second different etch rates. This etching yields a first trench extending adjacent the first opening that is deeper than a second trench extending adjacent the second opening. Then, the bottoms of the first and second trenches are simultaneously etched to substantially the same depths using an etching process that compensates for the first and second different etch rates.

Abstract: A method of patterning a film stack is described. The method comprises preparing a film stack on a substrate, wherein the film stack comprises a SiCOH-containing layer formed on the substrate, a silicon oxide (SiOx) layer formed on the SiCOH-containing layer, and a mask layer formed on the silicon oxide layer. A pattern is created in the mask layer. Thereafter, the pattern in the mask layer is transferred to the silicon oxide layer using a first etching process, and then the mask layer is removed. The pattern in the silicon oxide layer is transferred to the SiCOH-containing layer using a second etching process formed from a process composition comprising NF3. Thereafter, the silicon oxide layer is removed using a third etching process.

Abstract: A method for forming micro-patterns is disclosed. The method forms a sacrificial layer and a mask layer. A plurality of first taper trenches is formed in the sacrificial layer. A photoresist layer is filled in the plurality of first taper trenches. The photoresist layer is used as a mask and a plurality of second taper trenches is formed in the sacrificial layer. Then, the photoresist layer is stripped to be capable of patterning a layer by the first taper trenches and the second taper trenches in the sacrificial layer. Therefore, a patterned sacrificial layer duplicating the line density by double etching is formed.

Abstract: A method for fabricating a semiconductor device includes forming a plurality of first hard mask patterns at certain intervals over a substrate where an etch target layer is formed, forming a sacrificial layer along a step of the substrate where the first hard mask patterns are formed, forming a second hard mask layer over the sacrificial layer, etching a portion of the second hard mask layer to expose the sacrificial layer and form second hard mask patterns remaining between the first hard mask patterns, removing the sacrificial layer between the first hard mask patterns and the second hard mask patterns, and etching the etch target layer using the first hard mask patterns and the second hard mask patterns as an etch mask.

Abstract: A method of fabricating a semiconductor device is provided. The method can include forming a hard mask film including lower and upper hard mask films on a substrate in which an active region and an isolation region are defined and patterning the hard mask film to provide a hard mask pattern partially exposing the active region and the isolation region. An etchant can be applied to the active and isolation regions using the hard mask pattern as an etching mask to form a trench in the active region of the substrate while avoiding substantially etching the isolation region exposed to the etchant and a gate can be formed on the trench.

Abstract: Disclosed are embodiments relating to a method of manufacturing a semiconductor device that may improve the yield rate of the semiconductor device. In embodiments, the method may include preparing a substrate including a plurality of conductive patterns, forming first and second insulating layers on the substrate, forming a plurality of via holes by selectively etching the first and second insulating layers, forming a plurality of trenches by selectively etching the second insulating layer in such a manner that the trenches are communicated with the trenches, and forming metal interconnections in the via holes and the trenches. The width ratio of the trench to the insulating layer positioned between adjacent trenches may be in a range of 0.45 to 0.55.

Abstract: A method of manufacturing a semiconductor device includes depositing a mask material to be patterned into a desired target pattern on an underlying material; patterning the mask material into a preparatory pattern including the target pattern and being larger than the target pattern; patterning the mask material into the target pattern; and processing the underlying material by using the mask material, which has been patterned, as a mask.

Abstract: Semiconductor fabrication processes are provided for removing sidewall spacers from gate structures while mitigating or otherwise preventing defect mechanisms such as damage to metal silicide structures or otherwise impeding or placing limitations on subsequent process flows.

Abstract: A contact for a semiconductor device is made by performing, inter alia, a CMP process on an interlayer insulation layer to expose a first hard mask layer of each conductive line. The interlayer insulation layer is partially removed. A second hard mask layer is formed on a resultant substrate. Another CMP process is performed on the second hard mask layer to expose the first hard mask layer of each conductive line. A hard mask pattern is formed by etching portions of the CMPed second hard mask layer. The interlayer insulation layer is etched by using the hard mask pattern as an etch barrier to open the contact forming regions of the substrate. A conductive layer is deposited on the resultant substrate to fill the opened contact forming regions. The conductive layer and the remaining hard mask pattern are removed to expose the first hard mask layer of each conductive line.

Abstract: Provided are methods for forming conductive plug structures, such as via plugs, from a plurality of conductive layer patterns and methods of fabricating semiconductor devices, including semiconductor memory devices such as phase change semiconductor memory devices. An example method forms a small via structure by forming a conductive layer on a semiconductor substrate. A molding insulating layer is formed on the conductive layer and a via hole is formed through the insulating layer to expose a region of the conductive layer. A first via filling layer is formed and then partially removed to form a partial via plug. The formation and removal of the phase change material layer are then repeated as necessary to form a multilayer plug structure that substantially fills the via hole with the multilayer structure typically exhibiting reduced defects and damage than plug structures prepared by conventional methods.

Abstract: A technology for inhibiting the dielectric breakdown occurred in a semiconductor device is provided. A semiconductor device includes a semiconductor substrate (not shown), an interlayer insulating film 102 formed on the semiconductor substrate and a multiple-layered insulating film 140 provided on the interlayer insulating film 102. The semiconductor device also includes an electric conductor that extends through the multiple-layered insulating film 140 and includes a Cu film 120 and a barrier metal film 118. The barrier metal film 118 is covers side surfaces and a bottom surface of the Cu film 120. An insulating film 116 is disposed between the multiple-layered insulating film 140 and the electric conductor (i.e., Cu film 120 and barrier metal film 118).

Abstract: The method of forming a semiconductor structure in a substrate comprises, forming a first trench with a first width We and a second trench with a second width Wc, wherein the first width We is larger than the second width Wc, depositing a protection material, lining the first trench, covering the substrate surface and filling the second trench and removing partially the protection material, wherein a lower portion of the second trench remains filled with the protection material.

Abstract: An etching solution for a metal hard mask. The etching solution comprises a mixture of a dilute HF (hydrofluoric acid) and a silicon containing precursor. The etching solution also comprises a surfactant agent, a carboxylic acid, and a copper corrosion inhibitor. The etching solution is selectively toward etching the metal hard mask material (e.g., Titanium) while suppressing Tungsten, Copper, oxide dielectric material, and carbon doped oxide.

Abstract: A method and system for forming dual damascene structures in a semiconductor package. In one embodiment, the method includes forming an intermediate dielectric layer on a bottom stop layer; forming an ashing removable dielectric layer on the intermediate dielectric layer; forming a patterned photoresist layer above the ashing removable dielectric layer in the semiconductor structure; and defining an in-situ hard mask in the ashing removable dielectric layer having an opening with a profile selected from the group consisting of a via, a trench, or a combination thereof. The profile of the in-situ mask preferably is capable of being transferred to the intermediate dielectric layer by etching.

Abstract: The present invention provides a method for manufacturing a semiconductor device having multiple gate dielectric thickness layers. The method, in one embodiment, includes forming a first layer of gate dielectric material over a semiconductor substrate in a first active region and a second active region of a semiconductor device, and patterning a masking layer to expose the first layer of gate dielectric material located in the first active region.

Abstract: A method for reducing line edge roughness comprises forming a masking structure on a substrate assembly, wherein the substrate assembly includes a number of layers. The method includes forming a layered masking structure by depositing a layer of material on the masking structure in order to reduce a line edge roughness (LER) of the masking structure, and etching a pattern of the layered masking structure into one or more of the number of layers of the substrate assembly before trimming the layered masking structure.

Abstract: The invention includes a template comprising one or both of Cbs and CdSe adhered to a base in a desired pattern. The base can be any transparent or translucent material, and the desired pattern can include two or more separated segments. The template can be utilized for patterning a plurality of substrates. For instance, the substrates can be provided to have masking layers thereover, and the CdS and/or CdSe can be utilized as catalytic material to sequentially impart patterns in the masking layers. The imparting of the patterns can modify some regions of the masking layers relative to others, and either the modified or unmodified regions can be selectively removed to form patterned masks from the masking layers. Patterns from the patterned masks can then be transferred into the substrates.

Abstract: A method for forming a dual damascene structure in a semiconductor device manufacturing process where via plugs which may include a thickness portion of a plug filling material overlying the process surface is formed by diffusing an acid into a plug filling material layer followed by reacting the acid with the plug filling material layer to form a soluble portion which is then removed using a solvent. A remaining portion of the plug filling material is cured and a BARC layer may be formed over the process surface prior to patterning trenches in an overlying resist layer and forming a dual damascene structure.

Abstract: A system and method of preventing pattern lifting during a trench etch/clean process is disclosed. A first layer comprising a first dip is formed over a first via pattern. A trench resist layer is formed. The trench resist layer is patterned with a trench reticle to produce a second via pattern in the trench resist layer over the first via pattern. A photo resist over the first via pattern is opened during a trench processing. Thus, an additional pattern added on a trench pattern reticle is used to open, i.e., remove resist over, a huge via feature area causing under layer dip.

Abstract: A method of forming a micro pattern of a semiconductor device method includes forming an etch target layer over a substrate, a hard mask layer over the etch target layer, and first auxiliary patterns over the etch target layer. The first auxiliary patterns defining a plurality of structures that are spaced apart from each other. Silicon is injected into the first auxiliary patterns to form silylated first auxiliary patterns. An insulating layer is formed over the hard mask layer and the silylated first auxiliary patterns, the insulating layer defining a space between two adjacent silylated first auxiliary patterns. A second auxiliary pattern is formed over the insulating layer at the space defined between the two silylated first auxiliary patterns. The insulating layer is etched to remove a portion of the insulating layer provided between the silylated first auxiliary patterns and the second auxiliary pattern while not removing a portion of the insulating layer provided below the second auxiliary pattern.

Abstract: A method for fabricating a semiconductor device includes: forming a first inter-layer insulation layer over a substrate where a plurality of first contact holes are formed; forming a conductive layer over the first inter-layer insulation layer to fill the first contact holes; etching the conductive layer such that a surface of the first inter-layer insulation layer is higher than that of the conductive layer, whereby a plurality of contact plugs filling the first contact holes are formed; and forming an etch stop layer more thickly over the surfaces of the contact plugs than the surface of the first inter-layer insulation layer.

Abstract: A method of opening a carbon-based hardmask layer composed of amorphous carbon containing preferably at least 60% carbon and between 10 and 40% hydrogen. The hardmask is opened by plasma etching using an etching gas composed of H2, N2, and CO. The etching is preferably performed in a plasma etch reactor having an HF biased pedestal electrode and a capacitively VHF biased showerhead.

Abstract: The invention includes semiconductor constructions containing optically saturable absorption layers. An optically saturable absorption layer can be between photoresist and a topography, with the topography having two or more surfaces of differing reflectivity relative to one another. The invention also includes methods of patterning photoresist in which a saturable absorption layer is provided between the photoresist and a topography with surfaces of differing reflectivity, and in which the differences in reflectivity are utilized to enhance the accuracy with which an image is photolithographically formed in the photoresist.

Abstract: By using a non-metallic hard mask for patterning low-k dielectric materials of advanced semiconductor devices, an enhanced degree of etch fidelity is obtained. The present invention may readily be applied to via first-trench last, trench first-via last schemes.

Abstract: A method of edge bevel rinse. First, a wafer having a coating material layer disposed thereon is provided. A light beam is optically projected on the wafer to form a reference pattern. The reference pattern defines a central region, and a bevel region surrounding the central region on the surface of the wafer. Subsequently, the coating material layer positioned in the bevel region is removed according to the reference pattern.

Abstract: Disclosed herein is an imaging method for patterning component shapes (e.g., fins, gate electrodes, etc.) into a substrate. By conducting a trim step prior to performing either an additive or subtractive sidewall image transfer process, the method avoids the formation of a loop pattern in a hard mask and, thus, avoids a post-SIT process trim step requiring alignment of a trim mask to sub-lithographic features to form a hard mask pattern with the discrete segments. In one embodiment a hard mask is trimmed prior to conducting an additive SIT process so that a loop pattern is not formed. In another embodiment an oxide layer and memory layer that are used to form a mandrel are trimmed prior to the conducting a subtractive SIT process. A mask is then used to protect portions of the mandrel during etch back of the oxide layer so that a loop pattern is not formed.

Abstract: Disclosed is a method of fabricating a semiconductor device, in which the process steps of a photoresist process for forming a metal line are simply reduced, and a process exerting an influence on the contact hole is minimized, so that the electrical characteristics of the semiconductor device can be improved. A reactive ion etching process is repeatedly performed, so that the depth of the trench or the aspect ratio of the contact hole can be adjusted. In addition, the region, in which the lower metal interconnection and the contact hole make contact with each other, can be cleaned.

Abstract: Techniques are disclosed for fabricating a device using a photolithographic process. The method includes providing a first anti-reflective coating over a surface of a substrate. A layer which is transparent to a wavelength of light used during the photolithographic process is provided over the first anti-reflective coating, and a photosensitive material is provided above the transparent layer. The photosensitive material is exposed to a source of radiation including the wavelength of light. Preferably, the first anti-reflective coating extends beneath substantially the entire transparent layer. The complex refractive index of the first anti-reflective coating can be selected to maximize the absorption at the first anti-reflective coating to reduce nothing of the photosensitive material.