Abstract: A method of forming a metal wire in a semiconductor device includes performing a first etching process on an insulating layer formed on a semiconductor substrate to form a trench and an insulating layer pattern, the insulating layer pattern defining the trench. A barrier metal layer is formed over the insulating layer pattern and the trench. A second etching process is performed on the barrier metal layer to expose upper corners of the trench while leaving the trench substantially covered with the barrier metal layer. A metal layer is formed over the barrier metal layer in the trench. A heat treatment process is performed for reflowing the metal layer. The metal layer is planarized.

Abstract: Methods are provided for fabricating a semiconductor device that include the steps of: sequentially forming a metal interconnection and a protecting layer on a semiconductor substrate; forming a contact hole on the protecting layer; isolating the contact hole by forming a molding layer and an etching stop layer stacked thereon; forming a sacrificial layer on the etching stop layer so as to fill the contact hole; forming a photoresist layer with an opening so as to expose the sacrificial layer and such that the opening of the photoresist layer aligns with the contact hole; forming a trench in the molding layer to penetrate the sacrificial layer and the etching stop layer; and performing a wet etching on the semiconductor substrate having the trench to remove the photoresist layer and the sacrificial layer, wherein the wet etching step is performed using an organic compound and fluoride ion-based buffered solution.

Abstract: A silicon bulk-micromachining technology is used to fabricate a GMR filter by exploiting the structure of a suspended silicon nitride (SiNx) membrane on the silicon substrate. A first silicon nitride (SiNx) thin film and a second silicon nitride (SiNx) thin film are formed on opposite sides of the silicon substrate. A first opening is defined in the first silicon nitride (SiNx) thin film, and a grating structure is defined in the second silicon nitride (SiNx) thin film. By etching off a portion of the silicon substrate exposed from the first opening until a portion of the second silicon nitride (SiNx) thin film is exposed from the first opening, a light path space is defined.

Abstract: A film (e.g., silicon polymer film, photoresist film) may be removed by applying a composition including a quaternary ammonium hydroxide, a sulfoxide compound, a dialkylene glycol alkyl ether, and/or water to the film. A silicon polymer film (e.g., hard mask layer) and a photoresist film, for example, may be removed by the composition using an in-situ process. Additionally, the composition may remove the silicon polymer film and the photoresist film while preventing or reducing damage to an underlying layer and the generation of particle-type etch residue.

Abstract: The present invention relates to a process for improved interfacial adhesion of dielectrics using patterned roughing. Improved adhesion strength between layers and substrates can be achieved through increasing the roughness of the interface between the materials. Roughness may including any disturbance of an otherwise generally smooth surface, such as grooves, indents, holes, trenches, and/or the like. Roughing on the interface may be achieved by depositing a material on a surface of the substrate to act as a mask and then using an etching process to induce the roughness. The material, acting as a mask, allows etching to occur on a fine, or sub-miniature, scale below the Scale achieved with a conventional photo mask and lithography to achieve the required pattern roughing. Another material is then deposited on the roughened surface of the substrate, filling in the roughing and adhering to the substrate.

Abstract: A method of performing a double-sided process is provided. First, a wafer having a structural pattern disposed on the front surface is provided. Following that, a plurality of front scribe lines are defined on the structural pattern, and a filling layer is filled into the front scribe lines. Subsequently, the structural pattern is bonded to a carrier wafer with a bonding layer, and a plurality of back scribe lines are defined on the back surface of the wafer. Finally, the filling layer filled in the front scribe lines is removed.

Abstract: A process is provided for forming vertical contacts in the manufacture of integrated circuits and devices. The process eliminates the need for precise mask alignment and allows the etch of the contact hole to be controlled independent of the etch of the interconnect trough. The process includes forming an insulating layer on the surface of a substrate; forming an etch stop layer on the surface of the insulating layer; forming an opening in the etch stop layer; etching to a first depth through the opening in the etch stop layer and into the insulating layer to form an interconnect trough; forming a photoresist mask on the surface of the etch stop layer and in the trough; and continuing to etch through the insulating layer until reaching the surface of the substrate to form a contact hole. The above process may be repeated during the formation of multilevel metal integrated circuits.

Abstract: Disclosed is a method for processing a two layer mask for use in fabrication of semiconductor devices whereby the critical dimension (CD) of a semiconductor device being fabricated with the mask can be controlled. After forming a carbon mask layer and a silicon containing photoresist layer on the carbon mask, a two-step process forms openings in the carbon mask layer, as required for subsequent device fabrication. The structure is placed in a plasma processing chamber, and an oxygen plasma is employed to partially etch the carbon layer. The oxygen plasma reacts with silicon in the photoresist to form a hard silicon oxide layer on the surface of the photoresist. A hydrogen plasma is then employed to complete the etch through the carbon layer with a reduced critical dimension. Damage to the silicon containing photoresist layer is kept to a minimum during the plasma etch process by limiting the low frequency RF power.

Abstract: A process is provided for forming vertical contacts in the manufacture of integrated circuits and devices so manufactured. The process eliminates the need for precise mask alignment and allows the etch of the contact hole to be controlled independent of the etch of the interconnect trough. The process includes forming an insulating layer on the surface of a substrate; forming an etch stop layer on the surface of the insulating layer; forming an opening in the etch stop layer; etching to a first depth through the opening in the etch stop layer and into the insulating layer to form an interconnect trough; forming a photoresist mask on the surface of the etch stop layer and in the trough; and continuing to etch through the insulating layer until reaching the surface of the substrate to form a contact hole. The above process may be repeated during the formation of multilevel metal integrated circuits.

Abstract: Provided is a method forming a desired pattern of electronically functional material 3 on a substrate 1. The method comprises the steps of: creating a first layer of patterning material 2 on the substrate whilst leaving areas of the substrate exposed to define said desired pattern; printing a suspension comprising particles of the electronically functional material 3 in a liquid dispersant, to which the patterning material is impervious, on the patterning material and the exposed substrate; removing at least some of the liquid dispersant from the suspension to consolidate the particles; and applying a first solvent to said consolidated particles which is capable of solubilizing the patterning material 2 and to which the consolidated particles are pervious so that the patterning material is removed from the substrate 1 together with any overlying electronically functional material 3.

Abstract: A fin-type field effect transistor has an insulator layer above a substrate and a fin extending above the insulator layer. The fin has a channel region, and source and drain regions. A gate conductor is positioned over the channel region. The insulator layer includes a heat dissipating structural feature adjacent the fin, and a portion of the gate conductor contacts the heat dissipating structural feature. The heat dissipating structural feature can comprise a recess within the insulator layer or a thermal conductor extending through the insulator layer.

Abstract: A method of forming trench openings in a dual damascene trench and via etch process by using a two component hard mask layer, termed a bi-layer, over different intermetal dielectrics, IMD, to solve dual damascene patterning problems, such as, fencing and sub-trench formation. Via first patterning in dual damascene processing is one of the major integration schemes for copper backend of line (BEOL) integration. Via first dual damascene scheme usually uses a hard mask layer deposited on top of an inter-metal dielectric (IMD) film stack. The dual damascene trench etch requires uniform trench depth across wafer after etch. In addition, via top corner profiles need to be well maintained without any fencing or faceting. The present method solves these problems by using a two component hard mask layer, termed a bi-layer, deposited directly on top of an inter-metal dielectric (IMD) film stack.

Abstract: An isotropic-diffusion filling method uses a thermal process on a result structure comprising a photoresist layer and an organic material layer to create a cross-linking layer there between, which minimizes step height differences between isolated and dense via-pattern regions for optimizing a subsequent trench process and simplifying process steps.

Abstract: An anti-reflective coating (ARC) is formed over the various layers involved in a cell fabrication process. The ARC is selectively etched such that the edges of the etched areas of the ARC slope downward at an angle determined by the thickness of the ARC. The etching process could include CF4 chemistry. The inner edges of the sloped ARC areas reduce the original photo-defined space since the underlying layers are now defined by the sloped edges.

Abstract: A method of fabricating a nonvolatile semiconductor memory including the steps of: sequentially forming a gate insulating layer and a first conductive layer of a floating gate on a semiconductor substrate; depositing an inter-gate insulating layer; forming an opening in a part of the inter-gate insulating layer; depositing a control gate electrode on the inter-gate insulating layer and an exposed portion of the first conductive layer by the opening; and forming the gate electrodes of the memory cell transistors and the gate electrodes of the select transistors by utilizing the etching processes of the control gate electrode, the inter-gate insulating layer and the first conductive layer, wherein the select transistors include at least a part of the exposed portion of the first conductive layer.

Abstract: An advanced back-end-of-line (BEOL) interconnect structure having a hybrid dielectric is disclosed. The inter-layer dielectric (ILD) for the via level is preferably different from the ILD for the line level. In a preferred embodiment, the via-level ILD is formed of a low-k SiCOH material, and the line-level ILD is formed of a low-k polymeric thermoset material.