Deposition Of Boron Or Phosphorus Doped Silicon Oxide, E.g., Bsg, Psg, Bpsg (epo) Patents (Class 257/E21.275)
  • Patent number: 10431450
    Abstract: A film forming method for a target object including a main surface and grooves formed in the main surface, includes a step of supplying of a first gas into the processing chamber, and a step of supplying a second gas and a high frequency power for plasma generation into the processing chamber to generate in the processing chamber a plasma of a gas including the second gas in the processing chamber. The first gas contains an oxidizing agent that does not include a hydrogen atom. The second gas contains a compound that includes one or more silicon atoms and one or more fluorine atoms and does not include a hydrogen atom. A film containing silicon and oxygen is selectively formed on the main surface of the target object except the grooves.
    Type: Grant
    Filed: March 8, 2018
    Date of Patent: October 1, 2019
    Assignee: TOKYO ELECTRON LIMITED
    Inventor: Kenji Ouchi
  • Patent number: 10361194
    Abstract: Semiconductor device having less defects in a gate insulating film and improved reliability and methods of forming the semiconductor devices are provided. The semiconductor devices may include a gate insulating film on a substrate and a gate electrode structure on the gate insulating film. The gate electrode structure may include a lower conductive film, a silicon oxide film, and an upper conductive film sequentially stacked on the gate insulating film. The lower conductive film may include a barrier metal layer.
    Type: Grant
    Filed: October 27, 2016
    Date of Patent: July 23, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Moon-Kyu Park, Jae-Yeol Song, Hoon-Joo Na, Yoon-Tae Hwang, Ki-Joong Yoon, Sang-Jin Hyun
  • Patent number: 10243058
    Abstract: According to one embodiment, a semiconductor device includes a first semiconductor layer including a nitride semiconductor, a first electrode separated from the first semiconductor layer in a first direction, and a first insulating film including silicon and oxygen and being provided between the first semiconductor layer and the first electrode. The first insulating film has a first thickness in the first direction. The first insulating film includes a first position, and a distance between the first position and the first semiconductor layer is ½ of the first thickness. A first hydrogen concentration of hydrogen at the first position is 2.5×1019 atoms/cm3 or less.
    Type: Grant
    Filed: August 21, 2017
    Date of Patent: March 26, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshiya Yonehara, Hisashi Saito, Yosuke Kajiwara, Daimotsu Kato, Tatsuo Shimizu, Yasutaka Nishida
  • Patent number: 10062563
    Abstract: Methods and apparatuses for depositing films in high aspect ratio features and trenches using a post-dose treatment operation during atomic layer deposition are provided. Post-dose treatment operations are performed after adsorbing precursors onto the substrate to remove adsorbed precursors at the tops of features prior to converting the adsorbed precursors to a silicon-containing film. Post-dose treatments include exposure to non-oxidizing gas, exposure to non-oxidizing plasma, and exposure to ultraviolet radiation.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: August 28, 2018
    Assignee: Lam Research Corporation
    Inventors: Purushottam Kumar, Adrien LaVoie, Ishtak Karim, Jun Qian, Frank L. Pasquale, Bart J. van Schravendijk
  • Patent number: 9972711
    Abstract: A metal-oxide-semiconductor field effect transistor (MOSFET) and a method of fabricating a MOSFET are described. The method includes depositing and patterning a dummy gate stack above an active channel layer formed on a base. The method also includes selectively etching the active channel layer leaving a remaining active channel layer, and epitaxially growing silicon doped active channel material adjacent to the remaining active channel layer.
    Type: Grant
    Filed: June 3, 2015
    Date of Patent: May 15, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Pranita Kerber, Qiqing C. Ouyang, Alexander Reznicek
  • Patent number: 9923074
    Abstract: A semiconductor device includes a gate disposed over a substrate; a source region and a drain region on opposing sides of the gate; and a pair of trench contacts over and abutting an interfacial layer portion of at least one of the source region and the drain region; wherein the interfacial layer includes boron in an amount in a range from about 5×1021 to about 5×1022 atoms/cm2.
    Type: Grant
    Filed: June 22, 2017
    Date of Patent: March 20, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chia-Yu Chen, Zuoguang Liu, Sanjay C. Mehta, Tenko Yamashita
  • Patent number: 9847221
    Abstract: Silicon oxide layer is deposited on a semiconductor substrate by PECVD at a temperature of less than about 200° C. and is treated with helium plasma to reduce stress of the deposited layer to an absolute value of less than about 80 MPa. Plasma treatment reduces hydrogen content in the silicon oxide layer, and leads to low stress films that can also have high density and low roughness. In some embodiments, the film is deposited on a semiconductor substrate that contains one or more temperature-sensitive layers, such as layers of organic material or spin-on dielectric that cannot withstand temperatures of greater than 250° C. In some embodiments the silicon oxide film is deposited to a thickness of between about 100-200 ?, and is used as a hardmask layer during etching of other layers on a semiconductor substrate.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: December 19, 2017
    Assignee: Lam Research Corporation
    Inventors: Kevin M. McLaughlin, Amit Pharkya, Kapu Sirish Reddy
  • Patent number: 9780113
    Abstract: A method for fabricating a semiconductor device includes forming a stacked structure on a substrate, forming a first interlayer dielectric covering the stacked structure, and forming a second interlayer dielectric covering the first interlayer dielectric. The stacked structure includes a stepwise shape. The first interlayer dielectric includes at least one step portion having a slope surface connecting a first top surface to a second top surface. The first top surface and the sloped surface define a first angle that is an obtuse angle. A level of the second top surface is higher than a level of the first top surface.
    Type: Grant
    Filed: December 9, 2015
    Date of Patent: October 3, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jiwoon Im, Kwangchul Park, Jiyoun Seo, Jongmyeong Lee, Kyung-Tae Jang, Byungho Chun, Won-Seok Jung, Jongwan Choi, Tae-Jong Han
  • Patent number: 9780028
    Abstract: A dielectric layer includes a reflow via. The reflow via is formed by reflow of the dielectric layer away from a raised feature. An interconnect is in contact with the raised feature through the reflow via.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: October 3, 2017
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Kevin Dooley, Roger McQuaid, Liam Cheevers, David Fitzpatrick, Lorraine Byrne
  • Patent number: 9773731
    Abstract: A semiconductor device includes a dummy fin structure disposed over a substrate, a dummy gate structure disposed over a part of the dummy fin structure, a first interlayer dielectric layer in which the dummy gate structure is embedded, a second interlayer dielectric layer disposed over the first interlayer dielectric layer, and a resistor wire formed of a conductive material and embedded in the second interlayer dielectric layer. The resistor wire overlaps the dummy gate structure in plan view.
    Type: Grant
    Filed: January 28, 2016
    Date of Patent: September 26, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Hsin Hu, Yu-Chiun Lin, Yi-Hsuan Chung, Chung-Peng Hsieh, Chung-Chieh Yang, Po-Nien Chen
  • Patent number: 9748518
    Abstract: A thin-film packaging method and an organic light-emitting device are provided. The method includes following steps: forming an OLED layer on a TFT substrate, forming a first inorganic packaging layer on the OLED layer, forming a coupling agent unit on the first inorganic packaging layer, and forming an organic packaging layer on the coupling agent unit. Wherein, the organic packaging layer includes a buffer sublayer and a resist sublayer sequentially formed. The coupling agent unit generates chemical reactions with the first inorganic packaging layer and the buffer sublayer in order to increase an adhesive strength between the first inorganic packaging layer and the organic packaging layer so that they are not easily to be separated, and have a good water and oxygen insulation property.
    Type: Grant
    Filed: September 11, 2015
    Date of Patent: August 29, 2017
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd
    Inventors: Weijing Zeng, Xingyu Zhou
  • Patent number: 9540733
    Abstract: A film forming method in which in a state in which a target substrate is loaded on a loading table body of a loading table installed in a processing container and an interior of the processing container is evacuated, a film forming material gas is supplied into the processing container while heating the target substrate with a heater installed in the loading table body, to be thermally decomposed or reacted on a surface of the target substrate to form a predetermined film on the target substrate, includes introducing a heat transfer gas containing an H2 gas or an He gas into the processing container to transfer heat of the loading table body to a radially outer side of the loading table body, before the film forming material gas is supplied.
    Type: Grant
    Filed: April 28, 2015
    Date of Patent: January 10, 2017
    Assignee: TOKYO ELECTRON LIMITED
    Inventor: Tadahiro Ishizaka
  • Patent number: 8846525
    Abstract: Hardmask films having high hardness and low stress are provided. In some embodiments a film has a stress of between about ?600 MPa and 600 MPa and hardness of at least about 12 GPa. In some embodiments, a hardmask film is prepared by depositing multiple sub-layers of doped or undoped silicon carbide using multiple densifying plasma post-treatments in a PECVD process chamber. In some embodiments, a hardmask film includes a high-hardness boron-containing film selected from the group consisting of SixByCz, SixByNz, SixByCzNw, BxCy, and BxNy. In some embodiments, a hardmask film includes a germanium-rich GeNx material comprising at least about 60 atomic % of germanium. These hardmasks can be used in a number of back-end and front-end processing schemes in integrated circuit fabrication.
    Type: Grant
    Filed: August 15, 2013
    Date of Patent: September 30, 2014
    Assignee: Novellus Systems, Inc.
    Inventors: Vishwanathan Rangarajan, George Andrew Antonelli, Ananda Banerji, Bart Van Schravendijk
  • Patent number: 8617989
    Abstract: Methods of forming a dielectric liner layer on a semiconductor substrate are described. The method may include flowing a phosphorus-containing precursor with a silicon-containing precursor and an oxygen-containing precursor over the substrate to deposit a dielectric material. The dielectric material may be deposited along a field region and within at least one via on the substrate having a depth of at least 1 ?m. The method may also include forming a liner layer within the via with the dielectric material. The liner may include a silicon oxide doped with phosphorus, and the thickness of the liner layer at an upper portion of the via sidewall may be less than about 5 times the thickness of the liner layer at a lower portion of the via sidewall.
    Type: Grant
    Filed: April 19, 2012
    Date of Patent: December 31, 2013
    Assignee: Applied Materials, Inc.
    Inventors: Kedar Sapre, Manuel Hernandez, Lei Luo
  • Patent number: 8617938
    Abstract: A device and method for semiconductor fabrication includes forming a buffer layer on a semiconductor substrate and depositing an amorphous elemental layer on the buffer layer. Elements of the elemental layer are diffused through the buffer layer and into the semiconductor layer.
    Type: Grant
    Filed: January 25, 2011
    Date of Patent: December 31, 2013
    Assignee: International Business Machines Corporation
    Inventors: Joel P. De Souza, Marinus Hopstaken, Jeehwan Kim, Devendra K. Sadana
  • Patent number: 8563443
    Abstract: A method of forming a dielectric film having at least Si—N, Si—C, or Si—B bonds on a semiconductor substrate by atomic layer deposition (ALD), includes: supplying a precursor in a pulse to adsorb the precursor on a surface of a substrate; supplying a reactant gas in a pulse over the surface without overlapping the supply of the precursor; reacting the precursor and the reactant gas on the surface; and repeating the above steps to form a dielectric film having at least Si—N, Si—C, or Si—B bonds on the substrate. The precursor has at least one Si—C or Si—N bond, at least one hydrocarbon, and at least two halogens attached to silicon in its molecule.
    Type: Grant
    Filed: August 3, 2012
    Date of Patent: October 22, 2013
    Assignee: ASM Japan K.K.
    Inventor: Atsuki Fukazawa
  • Patent number: 8513717
    Abstract: A first driver transistor includes a first gate insulating film that surrounds a periphery of a first island-shaped semiconductor, a first gate electrode having a first surface that is in contact with the first gate insulating film, and first and second first-conductivity-type high-concentration semiconductors disposed on the top and bottom of the first island-shaped semiconductor, respectively. A first load transistor includes a second gate insulating film having a first surface that is in contact with a second surface of the first gate electrode, a first arcuate semiconductor formed so as to be in contact with a portion of a second surface of the second gate insulating film, and first and second second-conductivity-type high-concentration semiconductors disposed on the top and bottom of the first arcuate semiconductor, respectively. A first gate line extends from the first gate electrode and is made of the same material as the first gate electrode.
    Type: Grant
    Filed: December 16, 2011
    Date of Patent: August 20, 2013
    Assignee: Unisantis Electronics Singapore Pte. Ltd.
    Inventors: Fujio Masuoka, Hiroki Nakamura
  • Patent number: 8481419
    Abstract: A method for producing an electrically conducting metal contact on a semiconductor component having a coating on the surface of a semiconductor substrate. In order to keep transfer resistances low while maintaining good mechanical strength, the invention proposes applying a particle-containing fluid onto the coating, where the particles contain at least metal particles and glass frits, curing the fluid while simultaneously forming metal areas in the substrate through heat treatment, removing the cured fluid and the areas of the coating covered by the fluid, and depositing, for the purposes of forming the contact without using intermediate layers, electrically conducting material from a solution onto areas of the semiconductor component in which the coating is removed while at the same time conductively connecting the metal areas present in said areas on the substrate.
    Type: Grant
    Filed: November 26, 2009
    Date of Patent: July 9, 2013
    Assignee: SHOTT Solar AG
    Inventors: Jorg Horzel, Gunnar Schubert, Stefan Dauwe, Peter Roth, Tobias Droste, Wilfried Schmidt, Ingrid Ernst
  • Patent number: 8399952
    Abstract: Strontium ruthenium oxide provides an effective interface between a ruthenium conductor and a strontium titanium oxide dielectric. Formation of the strontium ruthenium oxide includes the use of atomic layer deposition to form strontium oxide and subsequent annealing of the strontium oxide to form the strontium ruthenium oxide. A first atomic layer deposition of strontium oxide is preformed using water as an oxygen source, followed by a subsequent atomic layer deposition of strontium oxide using ozone as an oxygen source.
    Type: Grant
    Filed: May 9, 2011
    Date of Patent: March 19, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Bhaskar Srinivasan, Vassil Antonov, John Smythe
  • Patent number: 8384135
    Abstract: A phase-change random access memory device includes a semiconductor substrate, a bottom electrode structure formed on the semiconductor substrate, a cylindrical bottom electrode contact that includes a conductive material layer, which is in contact with the bottom electrode, and a cylindrical phase-change material layer that is in contact with the bottom electrode contact. Therefore, the contact area between the bottom electrode contact and the phase-change material layer can be minimized.
    Type: Grant
    Filed: June 20, 2011
    Date of Patent: February 26, 2013
    Assignee: SK hynix Inc.
    Inventors: Cheol Hwi Ryu, Hyung Soon Park, Jong Han Shin, Jum Yong Park, Sung Jun Kim
  • Patent number: 8324014
    Abstract: The present invention relates to a process for depositing films on a substrate by chemical vapour deposition (CVD) or physical vapour deposition (PVD), said process employing at least one boron compound. This process is particularly useful for fabricating photovoltaic solar cells. The invention also relates to the use of boron compounds for conferring optical and/or electrical properties on materials in a CVD or PVD deposition process. This process is also particularly useful for fabricating a photovoltaic solar cell.
    Type: Grant
    Filed: November 3, 2008
    Date of Patent: December 4, 2012
    Assignee: L'Air Liquide Societe Anonyme pour l'Etude et l'Exploitation des Procedes Georges Claude
    Inventors: Audrey Pinchart, Denis Jahan
  • Patent number: 8242544
    Abstract: A method for reducing resist poisoning is provided. The method includes forming a first structure in a dielectric on a substrate and reducing amine related contaminants from the dielectric and the substrate created after the formation of the first structure. The method further includes forming a second structure in the dielectric. A first organic film may be formed on the substrate which is then heated and removed from the substrate to reduce the contaminant. Alternatively, a plasma treatment or cap may be provided. A second organic film is formed on the substrate and patterned to define a second structure in the dielectric.
    Type: Grant
    Filed: December 7, 2004
    Date of Patent: August 14, 2012
    Assignee: International Business Machines Corporation
    Inventors: Xiaomeng Chen, William Cote, Anthony K. Stamper, Arthur C. Winslow
  • Patent number: 8072043
    Abstract: A semiconductor component and a method for manufacturing such a semiconductor component which has a resistance behavior which depends heavily on the temperature. This resistance behavior is obtained by a special multi-layer structure of the semiconductor component, one layer being designed in such a way that, for example, multiple p-doped regions are present in an n-doped region, said regions being short-circuited on one side via a metal-plated layer. For example, the semiconductor component may be used for reducing current peaks, by being integrated into a conductor. In the cold state, the semiconductor component has a high resistance which becomes significantly lower when the semiconductor component is heated as a result of the flowing current.
    Type: Grant
    Filed: September 12, 2005
    Date of Patent: December 6, 2011
    Assignee: Robert Bosch GmbH
    Inventors: Peter Flohrs, Alfred Goerlach, Peter Urbach, Wolfgang Feiler, Ning Qu, Klaus Heyers
  • Patent number: 8021991
    Abstract: Oxide films are deposited under conditions generating a silicon-rich oxide in which silicon nanoclusters form either during deposition or during subsequent annealing. Such deposition conditions include those producing films with optical indices (n) greater than 1.46. The method of the present invention reduces the TID radiation-induced shifts for the oxides.
    Type: Grant
    Filed: February 28, 2006
    Date of Patent: September 20, 2011
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Harold L Hughes, Bernard J Mrstik, Reed K Lawrence, Patrick J McMarr
  • Patent number: 8021992
    Abstract: A high density plasma chemical vapor deposition process including exciting gas mixture to create a plasma including ions, and directing the plasma into a dense region above the upper surface of the semiconductor wafer, heating the wafer using an additional heat source, and allowing a material from the plasma to deposit onto the semiconductor wafer.
    Type: Grant
    Filed: September 1, 2005
    Date of Patent: September 20, 2011
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Joung-Wei Liou, Tsang-Yu Liu, Chien-Feng Lin, Cheng-Liang Chang, Ming-Te Chen, Chia-Hui Lin, Ying-Hsiu Tsai, Szu-An Wu, Yin-Ping Lee
  • Patent number: 7981797
    Abstract: A method of manufacturing a phase-change random access memory device includes forming an interlayer insulating film on a semiconductor substrate, on which a bottom structure is formed, and patterning the interlayer insulating film to form a contact hole, forming a spacer on the side wall of the contact hole; forming a dielectric layer in the contact hole, and removing the spacer to form a bottom electrode contact hole. Therefore, the contact area between the bottom electrode contact and the phase-change material layer can be minimized.
    Type: Grant
    Filed: June 25, 2008
    Date of Patent: July 19, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Cheol-Hwi Ryu, Hyung-Soon Park, Jong-Han Shin, Jum-Yong Park, Sung-Jun Kim
  • Patent number: 7902582
    Abstract: Electronic apparatus and methods of forming the electronic apparatus include a tantalum lanthanide oxynitride film on a substrate for use in a variety of electronic systems. The tantalum lanthanide oxynitride film may be structured as one or more monolayers. Metal electrodes may be disposed on a dielectric containing a tantalum lanthanide oxynitride film.
    Type: Grant
    Filed: May 21, 2009
    Date of Patent: March 8, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Leonard Forbes, Kie Y. Ahn, Arup Bhattacharyya
  • Patent number: 7863200
    Abstract: A process to encapsulate electronic modules in a manner which is substantially resistant to water diffusion yet is carried out at moderate temperatures below 300° C., preferably below 150° C. is provided. The process forms a housing for electronic modules, in particular sensors, integrated circuits and optoelectronic components. The process includes the steps of: providing a substrate, of which at least a first substrate side is to be encapsulated; providing a vapor-deposition glass source; arranging the first substrate side in such a manner with respect to the vapor-deposition glass source that the first substrate side can be vapor-coated; and vapor-coating the first substrate side with a glass layer.
    Type: Grant
    Filed: April 15, 2003
    Date of Patent: January 4, 2011
    Assignee: Schott AG
    Inventors: Jürgen Leib, Dietrich Mund
  • Patent number: 7846850
    Abstract: A method for fabricating an insulation layer includes forming an insulation layer over a nitride layer using a silicon source and a phosphorus source, wherein the insulation layer includes a first insulation layer contacting the nitride layer and a second insulation layer formed on the first insulation layer, wherein the first insulation layer is formed using a higher flow rate of the silicon source and a lower flow rate of the phosphorus source than used with the second insulation layer.
    Type: Grant
    Filed: December 30, 2008
    Date of Patent: December 7, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventor: Yang-Han Yoon
  • Patent number: 7846795
    Abstract: A bit line of a semiconductor device includes a first interlayer dielectric film disposed on a semiconductor substrate, a plurality of bit line stacks disposed on the first interlayer dielectric film, a plurality of bit line spacers disposed on side walls of the bit line stacks, and a buffer film disposed on the bit line spacers, the first interlayer dielectric film and the bit line stacks; and a method for fabricating the same.
    Type: Grant
    Filed: June 18, 2008
    Date of Patent: December 7, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jie Won Chung
  • Patent number: 7790632
    Abstract: This invention includes methods of forming a phosphorus doped silicon dioxide comprising layers, and methods of forming trench isolation in the fabrication of integrated circuitry. In one implementation, a method of forming a phosphorus doped silicon dioxide comprising layer includes positioning a substrate within a deposition chamber. First and second vapor phase reactants are introduced in alternate and temporally separated pulses to the substrate within the chamber in a plurality of deposition cycles under conditions effective to deposit a phosphorus doped silicon dioxide comprising layer on the substrate. One of the first and second vapor phase reactants is PO(OR)3 where R is hydrocarbyl, and an other of the first and second vapor phase reactants is Si(OR)3OH where R is hydrocarbyl.
    Type: Grant
    Filed: November 21, 2006
    Date of Patent: September 7, 2010
    Assignee: Micron Technology, Inc.
    Inventor: Brian A. Vaartstra
  • Patent number: 7786002
    Abstract: The invention provides a process for producing a substrate having a conductor arrangement that is suitable for radio-frequency applications, with improved radio-frequency properties. For this purpose, the process includes the steps of: depositing a structured glass layer having at least one opening over a contact-connection region by evaporation coating on the substrate and applying at least one conductor structure to the structured glass layer so that the at least one conductor has electrical contact with the contact-connection region.
    Type: Grant
    Filed: May 23, 2003
    Date of Patent: August 31, 2010
    Assignee: Schott AG
    Inventors: Jürgen Leib, Dietrich Mund
  • Patent number: 7642204
    Abstract: In one aspect, the invention includes a method of forming an insulating material comprising: a) providing a substrate within a reaction chamber; b) providing reactants comprising a Si, F and ozone within the reaction chamber; and c) depositing an insulating material comprising fluorine, silicon and oxygen onto the substrate from the reactants. In another aspect, the invention includes a method of forming a boron-doped silicon oxide having Si—F bonds, comprising: a) providing a substrate within a reaction chamber; b) providing reactants comprising Triethoxy fluorosilane, a boron-containing precursor, and ozone within the reaction chamber; and c) depositing a boron-doped silicon oxide having Si—F bonds onto the substrate from the reactants.
    Type: Grant
    Filed: January 30, 2004
    Date of Patent: January 5, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Anand Srinivasan, Gurtej Sandhu, Ravi Iyer
  • Patent number: 7537971
    Abstract: A method for fabricating a complementary metal-oxide semiconductor (CMOS) image sensor includes performing an ion implantation process onto a photodiode region in a first conductivity type semiconductor layer to form a second conductivity type first impurity region, and performing an annealing process in a gas atmosphere including first conductivity type impurity atoms to form a first conductivity type second impurity region underneath a surface of the first conductivity type semiconductor layer in the second conductivity type first impurity region, wherein the first conductivity type second impurity region is doped with the diffused first conductivity impurity atoms.
    Type: Grant
    Filed: June 26, 2006
    Date of Patent: May 26, 2009
    Assignee: MagnaChip Semiconductor Ltd.
    Inventor: Han-Seob Cha
  • Patent number: 7534711
    Abstract: System and method for direct etching. According to an embodiment, the present invention provides a method for manufacturing an integrated circuit device. The method includes a step for providing a substrate having a contact region, which is provided between a first word line and a second word line. The contact region has an overlying plug structure, which is provided within a thickness of a first dielectric layer. The first dielectric layer includes a portion overlying the plug structure. The first dielectric layer has a planarized surface region. The method also includes a step for forming a first line and a second line and a space provided between the first word line and the second world line. The space is provided within a region overlying the plug structure.
    Type: Grant
    Filed: December 23, 2006
    Date of Patent: May 19, 2009
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Jingang Wu, Fei Luo, Guanqie Gao, Cheng Yang
  • Patent number: 7528059
    Abstract: By forming a capping layer after a CMP process for planarizing the surface topography of an ILD layer, any surface irregularities may be efficiently sealed, thereby reducing the risk for forming conductive surface irregularities during the further processing. Consequently, yield loss effects caused by leakage paths or short circuits in the first metallization layer may be significantly reduced.
    Type: Grant
    Filed: November 14, 2006
    Date of Patent: May 5, 2009
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Kai Frohberg, Sandra Bau, Johannes Groschopf
  • Patent number: 7521375
    Abstract: In methods of forming an oxide layer and an oxynitride layer, a substrate is loaded into a reaction chamber having a first pressure and a first temperature. The oxide layer is formed on the substrate using a reaction gas while increasing a temperature of the reaction chamber from the first temperature to a second temperature under a second pressure. Additionally, the oxide layer is nitrified in the reaction chamber to form the oxynitride layer on the substrate. When the oxide layer and/or the oxynitride layer are formed on the substrate, minute patterns of a semiconductor device, for example a DRAM device, an SRAM device or an LOGIC device may be easily formed on the oxide layer or the oxynitride layer.
    Type: Grant
    Filed: October 5, 2007
    Date of Patent: April 21, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-sub You, Hun-Hyeoung Leam, Seok-Woo Nam, Bong-Hyun Kim, Woong Lee, Sang-Hoon Lee
  • Patent number: 7485928
    Abstract: A process for the preparation of low resistivity arsensic or phosphorous doped (N+/N++) silicon wafers which, during the heat treatment cycles of essentially any arbitrary electronic device manufacturing process, reliably form oxygen precipitates.
    Type: Grant
    Filed: November 9, 2005
    Date of Patent: February 3, 2009
    Assignee: MEMC Electronic Materials, Inc.
    Inventors: Robert J. Falster, Vladimir Voronkov, Gabriella Borionetti
  • Patent number: 7482267
    Abstract: A spin on glass SOG layer 30 is formed, then a PECVD barrier layer 40 over the SOG layer. Holes 50 in the SOG layer for vias are formed with a wine glass profile, so that in a peripheral region around the periphery of the holes, the barrier layer is thinner or absent, and ion implantation is performed substantially perpendicular to the layers, to reach the SOG layer through the barrier layer preferentially in the peripheral region. This enables the implantation to be concentrated on the peripheral region, without the need for implantation at a high angle and wafer rotation. This enables the manufacturing process to be simplified and hence costs reduced. By concentrating the implantation in the peripheral region where it can reduce moisture transfer to material in the holes, there is less risk of deplanarization due to the SOG shrinkage associated with ion implantation.
    Type: Grant
    Filed: April 21, 2006
    Date of Patent: January 27, 2009
    Assignee: AMI Semiconductor Belgium BVBA
    Inventor: Peter Coppens
  • Publication number: 20090017640
    Abstract: Methods of forming boron-containing films are provided. The methods include introducing a boron-containing precursor into a chamber and depositing a network comprising boron-boron bonds on a substrate by thermal decomposition or a plasma process. The network may be post-treated to remove hydrogen from the network and increase the stress of the resulting boron-containing film. The boron-containing films have a stress between about ?10 GPa and 10 GPa and may be used as boron source layers or as strain-inducing layers.
    Type: Application
    Filed: July 11, 2008
    Publication date: January 15, 2009
    Inventors: Jeong-Uk Huh, Mihaela Balseanu, Li-Qun Xia, Derek R. Witty, Hichem M'Saad
  • Patent number: 7476609
    Abstract: A method for forming, by dry etch, an opening of a given shape in a silica glass layer, the layer having a doping profile similar to the shape and the etch plasma being a non-carbonated fluorinated plasma causing a non-directional etching.
    Type: Grant
    Filed: October 27, 2006
    Date of Patent: January 13, 2009
    Assignee: STMicroelectronics S.A.
    Inventor: Fabienne Judong
  • Patent number: 7468317
    Abstract: A method of forming a metal line, in which a nitride layer is used instead of a metal barrier layer, enabling a metal line structure with a relatively low resistance and therefore realizing a high integration of a device. In the method of forming the metal line of the semiconductor device, a first insulating layer and a second insulating layer with a different etch selectivity are sequentially formed on a semiconductor substrate. Predetermined regions of the first insulating layer and the second insulating layer are sequentially etched to form a contact hole. A metal barrier layer is formed on the entire surface including the contact hole. A first metal material is deposited on the entire surface to gap-fill the contact hole. The first metal material on the second insulating layer is stripped such that the first metal material remains only within the contact hole, thus forming a contact plug. A metal line is formed on a predetermined region of the second insulating layer including the contact plug.
    Type: Grant
    Filed: November 7, 2006
    Date of Patent: December 23, 2008
    Assignee: Hynix Semiconductor Inc.
    Inventors: Jik Ho Cho, Tae Kyung Kim
  • Patent number: 7387926
    Abstract: A method for manufacturing a CMOS image sensor is provided. The method includes forming a gate electrode on a semiconductor layer having defined regions of a photodiode region and a logic region, such that a gate oxide film is interposed between the semiconductor layer and the gate electrode; forming sidewall insulating films at both sides of the gate electrode, followed by forming a salicide-preventing film over an overall surface of the gate electrode and insulating films; removing the salicide-preventing film formed in the logic region; and removing a portion of the sidewall insulating films exposed by removing the salicide-preventing film, thereby exposing an upper side surface of the gate electrode.
    Type: Grant
    Filed: June 9, 2005
    Date of Patent: June 17, 2008
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Chang Hun Han
  • Patent number: 7351643
    Abstract: Even though photolithography with a diameter of 0.20 ?m or less is employed, a contact hole having a tapered shape with a required width including a positioning tolerance can be formed in a narrower gap between the gate electrodes. A method forms a minute contact hole between gate electrodes of a semiconductor device, which has a silicon dioxide film disposed at an upper layer of the semiconductor device and a BPSG film disposed below the silicon dioxide film. The BPSG film has gate electrodes therein, and no silicon nitride film is disposed on top and side surfaces of the gate electrodes, and no silicon nitride film is disposed above the gate electrodes. The silicon dioxide film is etched by a mixed gas of CF4, O2 and Ar at a substrate temperature of at least 40° C. The BPSG film is etched by over-etching of the silicon dioxide film so that a W-like shape is formed in the BPSG film.
    Type: Grant
    Filed: March 9, 2006
    Date of Patent: April 1, 2008
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Takeshi Nagao
  • Patent number: 7320944
    Abstract: A method of forming a phosphosilicate glass, includes flowing a pre-deposition gas comprising an inert gas into a deposition chamber containing a substrate, where the temperature of the substrate is at a pre-deposition temperature of at least 400° C; continuously increasing the temperature of gas in the chamber to a deposition temperature and simultaneously continuously increasing a flow rate of phosphine and silane until a phosphine:silane deposition ratio is achieved; and depositing the phosphosilicate glass on the substrate at the deposition temperature and at the phosphine:silane deposition ratio.
    Type: Grant
    Filed: June 27, 2005
    Date of Patent: January 22, 2008
    Assignee: Cypress Semiconductor Corporation
    Inventors: Michal Efrati Fastow, Ryan Holler
  • Patent number: 7297620
    Abstract: In methods of forming an oxide layer and an oxynitride layer, a substrate is loaded into a reaction chamber having a first pressure and a first temperature. The oxide layer is formed on the substrate using a reaction gas while increasing a temperature of the reaction chamber from the first temperature to a second temperature under a second pressure. Additionally, the oxide layer is nitrified in the reaction chamber to form the oxynitride layer on the substrate. When the oxide layer and/or the oxynitride layer are formed on the substrate, minute patterns of a semiconductor device, for example a DRAM device, an SRAM device or an LOGIC device may be easily formed on the oxide layer or the oxynitride layer.
    Type: Grant
    Filed: May 6, 2004
    Date of Patent: November 20, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Sub You, Hun-Hyeoung Leam, Seok-Woo Nam, Bong-Hyun Kim, Woong Lee, Sang-Hoon Lee
  • Patent number: 7223706
    Abstract: A method of forming a plasma enhanced deposited oxide film on a substrate includes introducing into a chamber containing the substrate silane gas and a dopant gas such as phosphine. The chamber is pressurized and energy is applied to create a plasma. The energy may be a dual frequency energy. The gas rates and pressure are selected to produce a plasma enhanced deposited oxide film on a substrate having a Si—O—Si bond peak absorbance in the IR spectrum of at least 1092 cm?1.
    Type: Grant
    Filed: September 30, 2004
    Date of Patent: May 29, 2007
    Assignee: Intersil Americas, Inc.
    Inventors: Katie H. Pentas, Mark D. Bordelon, Jack H. Linn
  • Patent number: 7220686
    Abstract: A method is provided for contact opening definition for active element electrical connections. According to the method, a layer of BPSG is formed on a surface of an integrated circuit, and a transparent layer of nitride UV is formed above the layer of BPSG. Preferably, the transparent layer of nitride UV is formed by deposition using an HDP process and has a thickness of less than about 500 ?. In one embodiment, after forming a transparent layer of nitride UV, two overlapped layers of BARC and resist are formed on the surface of the integrated circuit. Also provided is a machine-readable medium encoded with a program for contact opening definition for active element electrical connections.
    Type: Grant
    Filed: September 12, 2003
    Date of Patent: May 22, 2007
    Assignee: STMicroelectronics S.r.l.
    Inventor: Luca Pividori
  • Patent number: 7199057
    Abstract: A method by which a silicon wafer is prevented from increasing boron concentration near the surface and difference in the boron concentration does not arise between the surface of the annealed wafer and the silicon bulk to eliminate boron contamination in the silicon wafer caused by an annealing treatment is provided. The method includes, when annealing a silicon wafer having a surface on which a native oxide film has formed and boron of environmental origin or from chemical treatment prior to annealing has deposited, steps of carrying out temperature heat-up in a mixed gas atmosphere having a mixing ratio of hydrogen gas to inert gas of 5% to 100% so as to remove the boron-containing native oxide film, followed by annealing in an inert gas atmosphere.
    Type: Grant
    Filed: August 28, 2003
    Date of Patent: April 3, 2007
    Assignee: Sumco Corporation
    Inventors: So Ik Bae, Yoshinobu Nakada, Kenichi Kaneko
  • Patent number: RE40507
    Abstract: A method of forming a pre-metal dielectric film having good as deposited gapfill characteristics, as well as good mobile-ion gettering capability. The method involves first depositing a layer of high-ozone undoped silicon dioxide film having a high ozone/TEOS volume ratio. Then, a low-ozone doped BPSG film is deposited over the high-ozone undoped silicon dioxide layer. The film layers are heat treated to densify the film, and then the top layer is planarized using known planarization techniques to a thickness that allows for adequate mobile-ion gettering.
    Type: Grant
    Filed: June 25, 2003
    Date of Patent: September 16, 2008
    Assignee: Atmel Corporation
    Inventors: Amit S. Kelkar, Michael D. Whiteman