Deposition Of Carbon Doped Silicon Oxide, E.g., Sioc (epo) Patents (Class 257/E21.277)
  • Patent number: 10283324
    Abstract: Exemplary methods for laterally etching silicon nitride may include flowing oxygen-containing plasma effluents into a processing region of a semiconductor processing chamber. A substrate positioned within the processing region may include a trench formed through stacked layers including alternating layers of silicon nitride and silicon oxide. The methods may include passivating exposed surfaces of the silicon nitride with the oxygen-containing plasma effluents. The methods may include flowing a fluorine-containing precursor into the remote plasma region while maintaining the flow of the oxygen-containing precursor. The methods may include forming plasma effluents of the fluorine-containing precursor and the oxygen-containing precursor. The methods may include flowing the plasma effluents into the processing region of the semiconductor processing chamber. The methods may also include laterally etching the layers of silicon nitride from sidewalls of the trench.
    Type: Grant
    Filed: October 24, 2017
    Date of Patent: May 7, 2019
    Assignee: Applied Materials, Inc.
    Inventors: Zhijun Chen, Anchuan Wang, Jiayin Huang
  • Patent number: 10192782
    Abstract: A method of manufacturing the semiconductor device includes providing a first interlayer dielectric layer having a conductive pattern, sequentially forming a first etch stop layer, a second etch stop layer, a second interlayer dielectric layer and a mask pattern on the first interlayer dielectric layer, forming an opening in the second interlayer dielectric layer using the mask pattern as a mask, the opening exposing the second etch stop layer, and performing an etching process including simultaneously removing the mask pattern and the second etch stop layer exposed by the opening to expose the first etch stop layer.
    Type: Grant
    Filed: June 23, 2015
    Date of Patent: January 29, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Woojin Lee, VietHa Nguyen, Wookyung You, Doo-Sung Yun, Hyunbae Lee, Byunghee Kim, Sang Hoon Ahn, Seungyong Yoo, Naein Lee, Hoyun Jeon
  • Patent number: 10128086
    Abstract: Exemplary methods for treating a silicon-containing substrate may include flowing plasma effluents of a hydrogen-containing precursor into a processing region of the semiconductor processing chamber. A silicon-containing substrate may be positioned within the processing region and include a trench formed through stacked layers including alternating layers of silicon nitride and silicon oxide exposing a portion of the silicon-containing substrate. The methods may include contacting the exposed portion of the silicon-containing substrate with the plasma effluents. The methods may include flowing an oxygen-containing precursor into the processing region of the semiconductor processing chamber. The methods may include contacting the exposed portion of the silicon-containing substrate with the oxygen-containing precursor. The methods may also include converting the exposed portion of the silicon-containing substrate to silicon oxide.
    Type: Grant
    Filed: October 24, 2017
    Date of Patent: November 13, 2018
    Assignee: Applied Materials, Inc.
    Inventors: Jiayin Huang, Zhijun Chen, Anchuan Wang, Nitin Ingle
  • Patent number: 9947576
    Abstract: Methods are described for reducing shrinkage experienced by porous films on a patterned substrate. The film may be a silicon-and-hydrogen-containing layer which further contains one or two of carbon, oxygen and nitrogen. Shortly after deposition, the silicon-and-hydrogen-containing layer is treated by concurrent exposure to a relatively small molecule precursor (e.g. NH3 or C2H2) and a source of UV light. The treatment may reduce subsequent shrinkage experienced by the porous film even at the bottom of the film due to the significant penetration prior to reaction. The treatment may reduce shrinkage at the bottom of a trench filled with the porous film.
    Type: Grant
    Filed: July 13, 2015
    Date of Patent: April 17, 2018
    Assignee: Applied Materials, Inc.
    Inventors: Brian Saxton Underwood, Abhijit Basu Mallick
  • Patent number: 9865617
    Abstract: A semiconductor device includes a first interlayer insulating layer and a second interlayer insulating layer, and a horizontal conductive pattern interposed between the first interlayer insulating layer and the second interlayer insulating layer. Vertical structures extend through the first interlayer insulating layer, the second interlayer insulating layer, and the horizontal conductive pattern. Each of the first interlayer insulating layer and the second interlayer insulating layer has regions of different impurity concentrations.
    Type: Grant
    Filed: January 10, 2017
    Date of Patent: January 9, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hauk Han, Ji Woon Im, Do Hyung Kim, Hyun Seok Lim
  • Patent number: 9850574
    Abstract: A low-k dielectric porous silicon oxycarbon layer is formed within an integrated circuit. In one embodiment, a porogen and bulk layer containing silicon oxycarbon layer is deposited, the porogens are selectively removed from the formed layer without simultaneously cross-linking the bulk layer, and then the bulk layer material is cross-linked. In other embodiments, multiple silicon oxycarbon sublayers are deposited, porogens from each sub-layer are selectively removed without simultaneously cross-linking the bulk material of the sub-layer, and the sub-layers are cross-linked separately.
    Type: Grant
    Filed: February 16, 2015
    Date of Patent: December 26, 2017
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Taewan Kim, Kang Sub Yim, Alexandros T. Demos
  • Patent number: 9034675
    Abstract: Techniques are provided for manufacturing a light-emitting device having high internal quantum efficiency, consuming less power, having high luminance, and having high reliability. The techniques include forming a conductive light-transmitting oxide layer comprising a conductive light-transmitting oxide material and silicon oxide, forming a barrier layer in which density of the silicon oxide is higher than that in the conductive light-transmitting oxide layer over the conductive light-transmitting oxide layer, forming an anode having the conductive light-transmitting oxide layer and the barrier layer, heating the anode under a vacuum atmosphere, forming an electroluminescent layer over the heated anode, and forming a cathode over the electroluminescent layer. According to the techniques, the barrier layer is formed between the electroluminescent layer and the conductive light-transmitting oxide layer.
    Type: Grant
    Filed: June 9, 2014
    Date of Patent: May 19, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Kengo Akimoto, Junichiro Sakata, Yoshiharu Hirakata, Norihito Sone
  • Patent number: 8940639
    Abstract: A MEMS device with movable MEMS structure and electrodes is produced by fabricating electrodes and shielding the electrodes with diamond buttons during subsequent fabrication steps, such as the etching of sacrificial oxide using vapor HF. In some embodiments, the diamond buttons are removed after the movable MEMS structure is released.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: January 27, 2015
    Assignee: Analog Devices, Inc.
    Inventors: Fang Liu, Kuang L. Yang
  • Patent number: 8921235
    Abstract: A method of forming and controlling air gaps between adjacent raised features on a substrate includes forming a silicon-containing film in a bottom region between the adjacent raised features using a flowable deposition process. The method also includes forming carbon-containing material on top of the silicon-containing film and forming a second film over the carbon-containing material using a flowable deposition process. The second film fills an upper region between the adjacent raised features. The method also includes curing the materials at an elevated temperature for a period of time to form the air gaps between the adjacent raised features. The thickness and number layers of films can be used to control the thickness, vertical position and number of air gaps.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: December 30, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Kiran V. Thadani, Jingjing Xu, Abhijit Basu Mallick, Joe Griffith Cruz, Nitin K. Ingle, Pravin K. Narwankar
  • Patent number: 8759233
    Abstract: A method for fabricating a semiconductor device includes forming a metal layer on a substrate, forming a plurality of layers of a magnetic tunnel junction (MTJ) element on the metal layer, forming a carbon layer including a hole, wherein the hole penetrates through the carbon layer, forming a metal pattern in the hole of the carbon layer, removing the carbon layer; and patterning the plurality of layers of the MTJ element using the metal pattern as an etching mask.
    Type: Grant
    Filed: June 21, 2012
    Date of Patent: June 24, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventor: Sang Hoon Cho
  • Patent number: 8716150
    Abstract: Methods of forming a semiconductor device are provided. The methods include, for example, forming a low-k dielectric having a continuous planar surface, and, after forming the low-k dielectric, subjecting the continuous planar surface of the low-k dielectric to an ethylene plasma enhanced chemical vapor deposition (PECVD) treatment.
    Type: Grant
    Filed: April 11, 2013
    Date of Patent: May 6, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Zhiguo Sun, Songkram Srivathanakul, Huang Liu, Hung-Wei Liu
  • Patent number: 8673770
    Abstract: One method disclosed herein includes the steps of forming a ULK material layer, forming a hard mask layer above the ULK material layer, forming a patterned photoresist layer above the hard mask layer, performing at least one etching process to define an opening in at least the ULK material layer for a conductive structure to be positioned in at least the ULK material layer, forming a fill material such that it overfills the opening, performing a process operation to remove the patterned photoresist layer and to remove the fill material positioned outside of the opening, removing the fill material from within the opening and, after removing the fill material from within the opening, forming a conductive structure in the opening.
    Type: Grant
    Filed: October 25, 2011
    Date of Patent: March 18, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Torsten Huisinga, Jens Heinrich, Ronny Pfuetzner
  • Patent number: 8637403
    Abstract: A method of manufacturing a semiconductor structure includes varying local chemical mechanical polishing (CMP) abrading rates of an insulator film by selectively varying a carbon content of the insulator film.
    Type: Grant
    Filed: December 12, 2011
    Date of Patent: January 28, 2014
    Assignee: International Business Machines Corporation
    Inventors: Yoba Amoah, Graham M. Bates, Joseph P. Hasselbach, Thomas L. McDevitt, Eva A. Shah
  • Patent number: 8563443
    Abstract: A method of forming a dielectric film having at least Si—N, Si—C, or Si—B bonds on a semiconductor substrate by atomic layer deposition (ALD), includes: supplying a precursor in a pulse to adsorb the precursor on a surface of a substrate; supplying a reactant gas in a pulse over the surface without overlapping the supply of the precursor; reacting the precursor and the reactant gas on the surface; and repeating the above steps to form a dielectric film having at least Si—N, Si—C, or Si—B bonds on the substrate. The precursor has at least one Si—C or Si—N bond, at least one hydrocarbon, and at least two halogens attached to silicon in its molecule.
    Type: Grant
    Filed: August 3, 2012
    Date of Patent: October 22, 2013
    Assignee: ASM Japan K.K.
    Inventor: Atsuki Fukazawa
  • Patent number: 8536073
    Abstract: Hardmask films having high hardness and low stress are provided. In some embodiments a film has a stress of between about ?600 MPa and 600 MPa and hardness of at least about 12 GPa. In some embodiments, a hardmask film is prepared by depositing multiple sub-layers of doped or undoped silicon carbide using multiple densifying plasma post-treatments in a PECVD process chamber. In some embodiments, a hardmask film includes a high-hardness boron-containing film selected from the group consisting of SixByCz, SixByNz, SixByCzNw, BxCy, and BxNy. In some embodiments, a hardmask film includes a germanium-rich GeNx material comprising at least about 60 atomic % of germanium. These hardmasks can be used in a number of back-end and front-end processing schemes in integrated circuit fabrication.
    Type: Grant
    Filed: July 11, 2012
    Date of Patent: September 17, 2013
    Assignee: Novellus Systems, Inc.
    Inventors: Vishwanathan Rangarajan, George Andrew Antonelli, Ananda Banerji, Bart Van Schravendijk
  • Patent number: 8466073
    Abstract: A method of forming a silicon oxide layer is described. The method first deposits a silicon-nitrogen-and-hydrogen-containing (polysilazane) film by radical-component chemical vapor deposition (CVD). The silicon-nitrogen-and-hydrogen-containing film is formed by combining a radical precursor (excited in a remote plasma) with an unexcited carbon-free silicon precursor. A capping layer is formed over the silicon-nitrogen-and-hydrogen-containing film to avoid time-evolution of underlying film properties prior to conversion into silicon oxide. The capping layer is formed by combining a radical oxygen precursor (excited in a remote plasma) with an unexcited silicon-and-carbon-containing-precursor. The films are converted to silicon oxide by exposure to oxygen-containing environments. The two films may be deposited within the same substrate processing chamber and may be deposited without breaking vacuum.
    Type: Grant
    Filed: April 17, 2012
    Date of Patent: June 18, 2013
    Assignee: Applied Materials, Inc.
    Inventors: Linlin Wang, Abhijit Basu Mallick, Nitin K. Ingle
  • Patent number: 8445377
    Abstract: A mechanically robust semiconductor structure with improved adhesion strength between a low-k dielectric layer and a dielectric-containing substrate is provided. In particular, the present invention provides a structure that includes a dielectric-containing substrate having an upper region including a treated surface layer which is chemically and physically different from the substrate; and a low-k dielectric material located on a the treated surface layer of the substrate. The treated surface layer and the low-k dielectric material form an interface that has an adhesion strength that is greater than 60% of the cohesive strength of the weaker material on either side of the interface. The treated surface is formed by treating the surface of the substrate with at least one of actinic radiation, a plasma and e-beam radiation prior to forming of the substrate the low-k dielectric material.
    Type: Grant
    Filed: September 9, 2011
    Date of Patent: May 21, 2013
    Assignee: International Business Machines Corporation
    Inventors: Qinghuang Lin, Terry A. Spooner, Darshan D. Gandhi, Christy S. Tyberg
  • Patent number: 8399358
    Abstract: Silicon oxide based low-k dielectric materials may receive superior hydrophobic surface characteristics on the basis of a plasma treatment using hydrogen and carbon containing radicals. For this purpose, the surface of the low-k dielectric material may be exposed to these radicals, at least in one in situ process in combination with another reactive plasma ambient, for instance used for patterning the low-k dielectric material. Consequently, superior surface characteristics may be established or re-established without significantly contributing to product cycle time.
    Type: Grant
    Filed: May 25, 2010
    Date of Patent: March 19, 2013
    Assignee: GLOBALFOUNDRIES, Inc.
    Inventors: Daniel Fischer, Matthias Schaller
  • Patent number: 8390135
    Abstract: The reliability of a porous Low-k film is improved. The mean diameter of first pores and second pores in an interlayer insulation film of a second fine layer including a porous Low-k film is set at 1.0 nm or more and less than 1.45 nm. This prevents the formation of a modified layer over the surface of the interlayer insulation film by process damages. Further, the formation of the moisture-containing modified layer is inhibited to prevent oxidation of a barrier film and a main conductor film forming respective wirings. This prevents deterioration of breakdown voltage between respective wirings. This prevents deterioration of the EM lifetime of wirings formed adjacent to the interlayer insulation film and the inter-wiring TDDB lifetime of the wirings.
    Type: Grant
    Filed: May 18, 2011
    Date of Patent: March 5, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Yoshihiro Oka, Kinya Goto
  • Patent number: 8349746
    Abstract: Embodiments of the present invention pertain to the formation of microelectronic structures. Low k dielectric materials need to exhibit a dielectric constant of less than about 2.6 for the next technology node of 32 nm. The present invention enables the formation of semiconductor devices which make use of such low k dielectric materials while providing an improved flexural and shear strength integrity of the microelectronic structure as a whole.
    Type: Grant
    Filed: February 23, 2010
    Date of Patent: January 8, 2013
    Assignee: Applied Materials, Inc.
    Inventors: Bo Xie, Alexandros T. Demos, Daemian Raj, Sure Ngo, Kang Sub Yim
  • Patent number: 8338315
    Abstract: Processes for curing silicon based low k dielectric materials generally includes exposing the silicon based low k dielectric material to ultraviolet radiation in an inert atmosphere having an oxidant in an amount of about 10 to about 500 parts per million for a period of time and intensity effective to cure the silicon based low k dielectric material so to change a selected one of chemical, physical, mechanical, and electrical properties and combinations thereof relative to the silicon based low k dielectric material prior to the ultraviolet radiation exposure. Also disclosed herein are silicon base low k dielectric materials substantially free of sub-oxidized SiO species.
    Type: Grant
    Filed: February 26, 2008
    Date of Patent: December 25, 2012
    Assignee: Axcelis Technologies, Inc.
    Inventors: Darren L. Moore, Carlo Waldfried, Ganesh Rajagopalan
  • Patent number: 8318584
    Abstract: The formation of a gap-filling silicon oxide layer with reduced volume fraction of voids is described. The deposition involves the formation of an oxygen-rich less-flowable liner layer before an oxygen-poor more-flowable gapfill layer. However, the liner layer is deposited within the same chamber as the gapfill layer. The liner layer and the gapfill layer may both be formed by combining a radical component with an unexcited silicon-containing precursor (i.e. not directly excited by application of plasma power). The liner layer has more oxygen content than the gapfill layer and deposits more conformally. The deposition rate of the gapfill layer may be increased by the presence of the liner layer. The gapfill layer may contain silicon, oxygen and nitrogen and be converted at elevated temperature to contain more oxygen and less nitrogen. The presence of the gapfill liner provides a source of oxygen underneath the gapfill layer to augment the gas phase oxygen introduced during the conversion.
    Type: Grant
    Filed: June 3, 2011
    Date of Patent: November 27, 2012
    Assignee: Applied Materials, Inc.
    Inventors: DongQing Li, Jingmei Liang, Nitin K. Ingle
  • Patent number: 8258053
    Abstract: In sophisticated semiconductor devices including transistors having a high-k metal gate electrode structure, disposable spacers may be provided on the encapsulating spacer element with a reduced width so as to not unduly increase a lateral offset of a strain-inducing material to be incorporated into the active region. For this purpose, a multi-layer deposition may be used in combination with a low pressure CVD process.
    Type: Grant
    Filed: October 8, 2010
    Date of Patent: September 4, 2012
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Stephan Kronholz, Matthias Kessler, Andreas Kurz
  • Patent number: 8247332
    Abstract: Hardmask films having high hardness and low stress are provided. In some embodiments a film has a stress of between about ?600 MPa and 600 MPa and hardness of at least about 12 GPa. In some embodiments, a hardmask film is prepared by depositing multiple sub-layers of doped or undoped silicon carbide using multiple densifying plasma post-treatments in a PECVD process chamber. In some embodiments, a hardmask film includes a high-hardness boron-containing film selected from the group consisting of SixByCz, SixByNz, SixByCzNw, BxCy, and BxNy. In some embodiments, a hardmask film includes a germanium-rich GeNx material comprising at least about 60 atomic % of germanium. These hardmasks can be used in a number of back-end and front-end processing schemes in integrated circuit fabrication.
    Type: Grant
    Filed: December 4, 2009
    Date of Patent: August 21, 2012
    Assignee: Novellus Systems, Inc.
    Inventors: Vishwanathan Rangarajan, George Andrew Antonelli, Ananda Banerji, Bart van Schravendijk
  • Patent number: 8188576
    Abstract: A compound for filling small gaps in a semiconductor device, a composition for filling small gaps in a semiconductor device, and a method of fabricating a semiconductor capacitor, the compound including hydrolysates prepared by hydrolysis, in the presence of an acid catalyst, of compounds represented by Formulae 1, 2, and 3: [RO]3Si—[CH2]nR???(1) wherein, in Formula 1, n is an integer from 0 to about 10, and R and R? are each independently a hydrogen atom, a C1-C12 alkyl group, or a C6-C20 aryl group; HOOC[CH2]nR2Si—O—SiR?2[CH2]nCOOH??(2) wherein, in Formula 2, each n is independently an integer from 0 to about 10, and R and R? are each independently a C1-C12 alkyl group or a C6-C20 aryl group; and R3Si—O—X??(3) wherein, in Formula 3, X is R? or SiR?3, and R and R? are each independently a C1-C12 alkyl group or a C6-C20 aryl group, or a polycondensate prepared by polycondensation of the hydrolysates represented by Formulae 1, 2, and 3.
    Type: Grant
    Filed: March 2, 2011
    Date of Patent: May 29, 2012
    Assignee: Cheil Industries, Inc.
    Inventors: Sung Jae Lee, Hee Jae Kim, Tae Ho Kim, Sang Geun Yun, Chang Soo Woo
  • Patent number: 8168543
    Abstract: Methods of forming a barrier layer are provided. In one embodiment, the method includes providing a substrate into a physical vapor deposition (PVD) chamber, supplying at least two reactive gases and an inert gas into the PVD chamber, sputtering a source material from a target disposed in the processing chamber in the presence of a plasma formed from the gas mixture, and forming a metal containing dielectric layer on the substrate from the source material. In another embodiment, the method includes providing a substrate into a PVD chamber, supplying a reactive gas the PVD chamber, sputtering a source material from a target disposed in the PVD chamber in the presence of a plasma formed from the reactive gas, forming a metal containing dielectric layer on the substrate from the source material, and post treating the metal containing layer in presence of species generated from a remote plasma chamber.
    Type: Grant
    Filed: September 18, 2009
    Date of Patent: May 1, 2012
    Assignee: Applied Materials, Inc.
    Inventors: Xinyu Fu, Keyvan Kashefizadeh, Ashish Subhash Bodke, Winsor Lam, Yiochiro Tanaka, Wonwoo Kim
  • Patent number: 8110879
    Abstract: Properties of a hard mask liner are used against the diffusion of a removal agent to prevent air cavity formation in specific areas of an interconnect stack. According to one embodiment, there is provided a method in which there is defined a portion on a surface of an IC interconnect stack as being specific to air cavity introduction, with the defined portion being smaller than the surface of the substrate. At least one metal track is produced within the interconnect stack, and there is deposited at least one interconnect layer having a sacrificial material and a permeable material within the interconnect stack. There is defined at least one trench area surrounding the defined portion and forming at least one trench, and a hard mask layer is deposited to coat the trench. At least one air cavity is formed below the defined portion of the surface by using a removal agent for removing the sacrificial material to which the permanent material is resistant.
    Type: Grant
    Filed: October 19, 2009
    Date of Patent: February 7, 2012
    Assignees: STMicroelectronics (Crolles 2) SAS, Koninklijke Philips Electronics N.V.
    Inventors: Joaquin Torres, Laurent-Georges Gosset
  • Patent number: 8093089
    Abstract: Method of manufacturing image sensors having a plurality of gettering regions. In the method, a gate electrode may be formed on a semiconductor substrate. A source/drain region may be formed in the semiconductor substrate to be overlapped with the gate electrode. A gettering region may be formed in the semiconductor substrate to be adjacent to the source/drain region.
    Type: Grant
    Filed: April 19, 2010
    Date of Patent: January 10, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Hyun-Pil Noh
  • Patent number: 8076251
    Abstract: Provided is a method of manufacturing a semiconductor device. The method includes: loading a substrate into a process vessel; performing a process to form an oxide, nitride, or oxynitride film on the substrate by alternately repeating: (a) forming a layer containing an element on the substrate by supplying and exhausting first and second source gases containing the element into and from the process vessel; and (b) changing the layer containing the element into an oxide, nitride, or oxynitride layer by supplying and exhausting reaction gas different from the first and second source gases into and from the process vessel; and unloading the substrate from the process vessel. The first source gas is more reactive than the second source gas, and an amount of the first source gas supplied into the process vessel is set to be less than that of the second source gas supplied into the process vessel.
    Type: Grant
    Filed: September 29, 2010
    Date of Patent: December 13, 2011
    Assignee: Hitachi Kokusai Electric, Inc.
    Inventors: Naonori Akae, Yoshiro Hirose, Yushin Takasawa, Yosuke Ota, Ryota Sasajima
  • Patent number: 8026175
    Abstract: After a liquid chemical treatment is finished, in parallel with a washing away treatment and/or a drying treatment, by spraying from a nozzle for a cleaning liquid supplied by a cleaning line to an outer surface of a nozzle for a liquid chemical, crystals and the like of components of the liquid chemical adhered on the outer surface of the nozzle are removed. In the cleaning treatment, a spraying time of the cleaning liquid is five seconds to ten seconds. In addition, the components of the cleaning liquid is not specifically limited, however, since ammonium phosphate tends to be solved in purified water, if a liquid chemical containing ammonium phosphate is used, it is preferable to use purified water as the cleaning liquid. Depending on the components and the like of the liquid chemical, a solution that can solve the crystals and the like may be used in stead.
    Type: Grant
    Filed: June 28, 2006
    Date of Patent: September 27, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Tadashi Oshima
  • Patent number: 8017522
    Abstract: A mechanically robust semiconductor structure with improved adhesion strength between a low-k dielectric layer and a dielectric-containing substrate is provided. In particular, the present invention provides a structure that includes a dielectric-containing substrate having an upper region including a treated surface layer which is chemically and physically different from the substrate; and a low-k dielectric material located on a the treated surface layer of the substrate. The treated surface layer and the low-k dielectric material form an interface that has an adhesion strength that is greater than 60% of the cohesive strength of the weaker material on either side of the interface. The treated surface is formed by treating the surface of the substrate with at least one of actinic radiation, a plasma and e-beam radiation prior to forming of the substrate the low-k dielectric material.
    Type: Grant
    Filed: January 24, 2007
    Date of Patent: September 13, 2011
    Assignee: International Business Machines Corporation
    Inventors: Qinghuang Lin, Terry A. Spooner, Darshan D. Gandhi, Christy S. Tyberg
  • Publication number: 20110204492
    Abstract: Embodiments of the present invention pertain to the formation of microelectronic structures. Low k dielectric materials need to exhibit a dielectric constant of less than about 2.6 for the next technology node of 32 nm. The present invention enables the formation of semiconductor devices which make use of such low k dielectric materials while providing an improved flexural and shear strength integrity of the microelectronic structure as a whole.
    Type: Application
    Filed: February 23, 2010
    Publication date: August 25, 2011
    Inventors: Bo Xie, Alexandros T. Demos, Daemian Raj, Sure Ngo, Kang Sub Yim
  • Patent number: 8003549
    Abstract: A nitrogen-free anti-reflective layer for use in semiconductor photolithography is fabricated in a chemical vapor deposition process, optionally plasma-enhanced, using a gaseous mixture of carbon, silicon, and oxygen sources. By varying the process parameters, a substantially hermetic layer with acceptable values of the refractive index n and extinction coefficient k can be obtained. The nitrogen-free moisture barrier anti-reflective layer produced by this technique improves plasma etch of features such as vias in subsequent processing steps.
    Type: Grant
    Filed: November 20, 2009
    Date of Patent: August 23, 2011
    Assignee: Novellus Systems, Inc.
    Inventors: Ming Li, Bart Van Schravendijk, Tom Mountsier, Chiu Chi, Kevin Ilcisin, Julian Hsieh
  • Patent number: 7964442
    Abstract: The present invention generally provides a method for forming a dielectric barrier with lowered dielectric constant, improved etching resistivity and good barrier property. One embodiment provides a method for processing a semiconductor substrate comprising flowing a precursor to a processing chamber, wherein the precursor comprises silicon-carbon bonds and carbon-carbon bonds, and generating a low density plasma of the precursor in the processing chamber to form a dielectric barrier film having carbon-carbon bonds on the semiconductor substrate, wherein the at least a portion of carbon-carbon bonds in the precursor is preserved in the low density plasma and incorporated in the dielectric barrier film.
    Type: Grant
    Filed: October 9, 2007
    Date of Patent: June 21, 2011
    Assignee: Applied Materials, Inc.
    Inventors: Huiwen Xu, Yijun Liu, Li-Qun Xia, Derek R. Witty, Hichem M'Saad
  • Patent number: 7943531
    Abstract: A method of depositing a silicon oxide layer over a substrate includes providing a substrate to a deposition chamber. A first silicon-containing precursor, a second silicon-containing precursor and a NH3 plasma are reacted to form a silicon oxide layer. The first silicon-containing precursor includes at least one of Si—H bond and Si—Si bond. The second silicon-containing precursor includes at least one Si—N bond. The deposited silicon oxide layer is annealed.
    Type: Grant
    Filed: October 22, 2007
    Date of Patent: May 17, 2011
    Assignee: Applied Materials, Inc.
    Inventors: Srinivas D. Nemani, Abhijit Basu Mallick, Ellie Y. Yieh
  • Patent number: 7923383
    Abstract: This invention relates to a method of treating a semiconductor wafer and in particular, but not exclusively, to planarisation. The method consists of depositing a liquid short-chain polymer formed from a silicon containing bas or vapour. Subsequently water and OH are removed and the layer is stabilised.
    Type: Grant
    Filed: March 28, 2003
    Date of Patent: April 12, 2011
    Assignee: Tokyo Electron Limited
    Inventors: Knut Beekmann, Guy Patrick Tucker
  • Patent number: 7910475
    Abstract: A method for forming a semiconductor device is provided. In one embodiment, the method includes providing a semiconductor substrate with a surface region. The surface region includes one or more layers overlying the semiconductor substrate. In addition, the method includes depositing a dielectric layer overlying the surface region. The dielectric layer is formed by a CVD process. Furthermore, the method includes forming a diffusion barrier layer overlying the dielectric layer. In addition, the method includes forming a conductive layer overlying the diffusion barrier layer. Additionally, the method includes reducing the thickness of the conductive layer using a chemical-mechanical polishing process. The CVD process utilizes fluorine as a reactant to form the dielectric layer. In addition, the dielectric layer is associated with a dielectric constant equal or less than 3.3.
    Type: Grant
    Filed: July 17, 2009
    Date of Patent: March 22, 2011
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventor: Ting Cheong Ang
  • Patent number: 7820551
    Abstract: A line-form insulator is formed on a substrate and then the substrate is etched with the insulator used as a mask to form first trenches on both sides of the insulator. Side wall insulators are formed on the side walls of the first trenches, the substrate is etched with the insulator and side wall insulators used as a mask to form second trenches in the bottom of the first trenches. After, the substrate is oxidized with the insulator and side wall insulators used as an anti-oxidation mask to cause oxide regions formed on the adjacent side walls of the second trenches lying on both sides of the substrate to make contact with each other and the insulator and side wall insulators are removed. Then, a fin FET having a semiconductor region as a line-form fin is formed in the substrate.
    Type: Grant
    Filed: January 10, 2008
    Date of Patent: October 26, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Atsushi Yagishita, Akio Kaneko
  • Patent number: 7781351
    Abstract: Methods of preparing a carbon doped oxide (CDO) layer of low dielectric constant and low residual stress involving, for instance, providing a substrate to a deposition chamber and exposing it to an organosilicon precursor containing unsaturated C—C bonds or to multiple organic precursors including at least one organosilicon and at least one unsaturated C—C bond are provided. The methods may also involve igniting and maintaining a plasma in a deposition chamber using radio frequency power having high and low frequency components with a high percentage of the low frequency component, and depositing the carbon doped dielectric layer under conditions in which the resulting dielectric layer has a residual stress of not greater than, e.g., about 50 MPa, and a dielectric constant not greater than about 3.
    Type: Grant
    Filed: April 7, 2004
    Date of Patent: August 24, 2010
    Assignee: Novellus Systems, Inc.
    Inventors: Qingguo Wu, Haiying Fu, Dong Niu, Ananda K. Bandyopadhyay, David Mordo
  • Patent number: 7737052
    Abstract: A dielectric cap, interconnect structure containing the same and related methods are disclosed. The inventive dielectric cap includes a multilayered dielectric material stack wherein at least one layer of the stack has good oxidation resistance, Cu diffusion and/or substantially higher mechanical stability during a post-deposition curing treatment, and including Si—N bonds at the interface of a conductive material such as, for example, Cu. The dielectric cap exhibits a high compressive stress and high modulus and is still remain compressive stress under post-deposition curing treatments for, for example: copper low k back-end-of-line (BEOL) nanoelectronic devices, leading to less film and device cracking and improved reliability.
    Type: Grant
    Filed: March 5, 2008
    Date of Patent: June 15, 2010
    Assignees: International Business Machines Corporation, Advanced Micro Devices, Inc., Applied Materials, Inc.
    Inventors: Ritwik Bhatia, Griselda Bonilla, Alfred Grill, Joshua L. Herman, Son Van Nguyen, E. Todd Ryan, Hosadurga Shobha
  • Patent number: 7713854
    Abstract: A method of forming a gate dielectric layer includes forming a gate dielectric layer over a substrate. The gate dielectric layer is processed with carbon-containing ions. The gate dielectric layer is thermally processed, thereby providing the gate dielectric layer with a level of carbon between about 1 atomic % and about 20 atomic %.
    Type: Grant
    Filed: October 20, 2006
    Date of Patent: May 11, 2010
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chi-Chun Chen, Matt Yeh, Shih-Chang Chen, Mong-Song Liang, Jennifer Chen, Da-Yuan Lee
  • Patent number: 7670892
    Abstract: A transistor is fabricated upon a semiconductor substrate, where the yield strength or elasticity of the substrate is enhanced or otherwise adapted. A strain inducing layer is formed over the transistor to apply a strain thereto to alter transistor operating characteristics, and more particularly to enhance the mobility of carriers within the transistor. Enhancing carrier mobility allows transistor dimensions to be reduced while also allowing the transistor to operate as desired. However, high strain and temperature associated with fabricating the transistor result in deleterious plastic deformation. The yield strength of the silicon substrate is therefore adapted by incorporating nitrogen into the substrate, and more particularly into source/drain extension regions and/or source/drain regions of the transistor. The nitrogen can be readily incorporated during transistor fabrication by adding it as part of source/drain extension region formation and/or source/drain region formation.
    Type: Grant
    Filed: November 7, 2005
    Date of Patent: March 2, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: Srinivasan Chakravarthi, Pr Chidambaram, Rajesh Khamankar, Haowen Bu, Douglas T. Grider
  • Patent number: 7659206
    Abstract: A method of treating a substrate comprises depositing silicon oxycarbide on the substrate and removing the silicon oxycarbide from the substrate. The silicon oxycarbide on the substrate is decarbonized by exposure to an energized oxygen-containing gas that heats the substrate and converts the layer of silicon oxycarbide into a layer of silicon oxide. The silicon oxide is removed by exposure to a plasma of fluorine-containing process gas. Alternatively, the remaining silicon oxide can be removed by a fluorine-containing acidic bath. In yet another version, a plasma of a fluorine-containing gas and an oxygen-containing gas is energized to remove the silicon oxycarbide from the substrate.
    Type: Grant
    Filed: February 21, 2006
    Date of Patent: February 9, 2010
    Assignee: Applied Materials, Inc.
    Inventors: Krishna Vepa, Yashraj Bhatnagar, Ronald Rayandayan, Venkata Balagani
  • Patent number: 7642202
    Abstract: A nitrogen-free anti-reflective layer for use in semiconductor photolithography is fabricated in a chemical vapor deposition process, optionally plasma-enhanced, using a gaseous mixture of carbon, silicon, and oxygen sources. By varying the process parameters, a substantially hermetic layer with acceptable values of the refractive index n and extinction coefficient k can be obtained. The nitrogen-free moisture barrier anti-reflective layer produced by this technique improves plasma etch of features such as vias in subsequent processing steps.
    Type: Grant
    Filed: June 27, 2005
    Date of Patent: January 5, 2010
    Assignee: Novellus Systems, Inc.
    Inventors: Ming Li, Bart Van Schravendijk, Tom Mountsier, Chiu Chi, Kevin Ilcisin, Julian Hsieh
  • Publication number: 20090305514
    Abstract: Methods are provided for processing a substrate for depositing an adhesion layer having a low dielectric constant between two low k dielectric layers. In one aspect, the invention provides a method for processing a substrate including depositing a barrier layer on the substrate, wherein the barrier layer comprises silicon and carbon and has a dielectric constant less than 4, depositing a dielectric initiation layer adjacent the barrier layer, and depositing a first dielectric layer adjacent the dielectric initiation layer, wherein the dielectric layer comprises silicon, oxygen, and carbon and has a dielectric constant of about 3 or less.
    Type: Application
    Filed: July 21, 2009
    Publication date: December 10, 2009
    Inventors: Francimar Campana Schmitt, Li-Qun Xia, Son Van Nguyen, Shankar Venkataraman
  • Patent number: 7622400
    Abstract: Methods of forming a dielectric layer having a low dielectric constant and high mechanical strength are provided. The methods involve depositing a sub-layer of the dielectric material on a substrate, followed by treating the sub-layer with a plasma. The process of depositing and plasma treating the sub-layers is repeated until a desired thickness has been reached.
    Type: Grant
    Filed: May 18, 2004
    Date of Patent: November 24, 2009
    Assignee: Novellus Systems, Inc.
    Inventors: Keith Fox, Easwar Srinivasan, David Mordo, Qingguo Wu
  • Patent number: 7618893
    Abstract: Methods of forming a barrier layer are provided. In one embodiment, the method includes providing a substrate into a physical valor deposition (PVD) chamber, supplying at least two reactive gases and an inert gas into the PVD chamber, sputtering a source material from a target disposed in the processing chamber in the presence of a plasma formed from the gas mixture, and forming a metal containing dielectric layer on the substrate from the source material. In another embodiment, the method includes providing a substrate into a PVD chamber, supplying a reactive gas the PVD chamber, sputtering a source material from a target disposed in the PVD chamber in the presence of a plasma formed from the reactive gas, forming a metal containing dielectric layer on the substrate from the source material, and post treating the metal containing layer in presence of species generated from a remote plasma chamber.
    Type: Grant
    Filed: March 4, 2008
    Date of Patent: November 17, 2009
    Assignee: Applied Materials, Inc.
    Inventors: Xinyu Fu, Keyvan Kashefizadeh, Ashish Subhash Bodke, Winsor Lam, Yiochiro Tanaka, Wonwoo Kim
  • Patent number: 7615480
    Abstract: Presented are methods of fabricating three-dimensional integrated circuits that include post-contact back end of line through-hole via integration for the three-dimensional integrated circuits. In one embodiment, the method comprises forming metal plug contacts through a hard mask and a premetal dielectric to transistors in the semiconductor. The method also includes etching a hole for a through-hole via through the hard mask to the semiconductor using a patterned photoresist process, removing the patterned photoresist and using a hard mask process to etch the hole to an amount into the semiconductor. The method further includes depositing a dielectric liner to isolate the hole from the semiconductor, depositing a gapfill metal to fill the hole, and planarizing the surface of the substrate to the hard mask. Another aspect of the present invention includes three-dimensional integrated circuits fabricated according to methods of the present invention.
    Type: Grant
    Filed: June 20, 2007
    Date of Patent: November 10, 2009
    Assignee: Lam Research Corporation
    Inventors: John Boyd, Fritz Redeker, Yezdi Dordi, Hyungsuk Alexander Yoon, Shijian Li
  • Patent number: 7605071
    Abstract: Properties of a hard mask liner are used against the diffusion of a removal agent to prevent air cavity formation in specific areas of an interconnect stack. According to one embodiment, there is provided a method in which there is defined a portion on a surface of an IC interconnect stack as being specific to air cavity introduction, with the defined portion being smaller than the surface of the substrate. At least one metal track is produced within the interconnect stack, and there is deposited at least one interconnect layer having a sacrificial material and a permeable material within the interconnect stack. There is defined at least one trench area surrounding the defined portion and forming at least one trench, and a hard mask layer is deposited to coat the trench. At least one air cavity is formed below the defined portion of the surface by using a removal agent for removing the sacrificial material to which the permanent material is resistant.
    Type: Grant
    Filed: July 7, 2006
    Date of Patent: October 20, 2009
    Assignees: STMicroelectronics (Crolles 2) SAS, Koninklijke Philips Electronics N.V.
    Inventors: Joaquin Torres, Laurent-Georges Gosset
  • Patent number: 7602048
    Abstract: The object of the present invention is to improve the interfacial adhesion between the film with low dielectric constant and protective film, without damaging the excellent dielectric, flatness and gap-filling characteristics of the organic material of low dielectric constant, and for that purpose there is provided a wiring structure with the copper film embedded in the insulation film of the wiring layer, wherein the insulation film of the wiring layer is of a multi-layered structure with the laminated methyl silsesquioxane (MSQ) film, methylated hydrogen silsesquioxane (MHSQ) film and silicon oxide film.
    Type: Grant
    Filed: May 9, 2001
    Date of Patent: October 13, 2009
    Assignee: NEC Electronics Corporation
    Inventor: Tatsuya Usami