By Anodic Oxidation (epo) Patents (Class 257/E21.291)
  • Patent number: 8980686
    Abstract: An object is to provide a deposition technique for depositing an oxide semiconductor film. Another object is to provide a method for manufacturing a highly reliable semiconductor element using the oxide semiconductor film. A novel sputtering target obtained by removing an alkali metal, an alkaline earth metal, and hydrogen that are impurities in a sputtering target used for deposition is used, whereby an oxide semiconductor film containing a small amount of those impurities can be deposited.
    Type: Grant
    Filed: September 2, 2014
    Date of Patent: March 17, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 8470689
    Abstract: The method for forming a multilayer structure on a substrate comprises providing a stack successively comprising an electron hole blocking layer, a first layer made from N-doped semiconductor material having a dopant concentration greater than or equal to 1018 atoms/cm3 or P-doped semiconductor material, and a second layer made from semiconductor material of different nature. A lateral electric contact pad is made between the first layer and the substrate, and the material of the first layer is subjected to anodic treatment in an electrolyte.
    Type: Grant
    Filed: November 10, 2011
    Date of Patent: June 25, 2013
    Assignees: Commissariat a l'Energie Atomique et aux Energies Alternatives, STMicroelectronics (Crolles 2) SAS
    Inventors: S├ębastien Desplobain, Frederic-Xavier Gaillard, Yves Morand, Fabrice Nemouchi
  • Patent number: 8288771
    Abstract: A thin film transistor array panel is provided, which includes a substrate, a plurality of gate line formed on the substrate, a plurality of common electrodes having a transparent conductive layer on the substrate, a gate insulating layer covering the gate lines and the common electrodes, a plurality of semiconductor layers formed on the gate insulating layer, a plurality of data lines including a plurality of source electrodes and formed on the semiconductor layer and the gate insulating layer, a plurality of drain electrodes formed on the semiconductor layer and the gate insulating layer, and a plurality of pixel electrodes overlapping the common electrodes and connected to the drain electrodes.
    Type: Grant
    Filed: August 5, 2011
    Date of Patent: October 16, 2012
    Assignee: Samsung Electonics Co., Ltd.
    Inventors: Je-Hun Lee, Sung-Jin Kim, Hee-Joon Kim, Chang-Oh Jeong
  • Patent number: 8193030
    Abstract: Nonvolatile memory devices may be fabricated to include a switching device on a substrate and/or a storage node electrically connected to the switching device. A storage node may include a lower metal layer electrically connected to the switching device, a first insulating layer, a middle metal layer, a second insulating layer, an upper metal layer, a carbon nanotube layer, and/or a passivation layer stacked on the lower metal layer.
    Type: Grant
    Filed: January 3, 2011
    Date of Patent: June 5, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chang-wook Moon, Joong S. Jeon, El Mostafa Bourim, Hyun-deok Yang
  • Patent number: 8138046
    Abstract: The invention relates to a process for fabricating a vertical transistor structure. On a substrate (10), is a first conductive layer (11), providing the source or drain electrode function, and an upper conductive layer (17), providing the drain or source electrode function. The production of a membrane includes a stack of porous layers including a first insulating layer (20), a second conductive layer (12), providing the gate electrode function, and an upper insulating layer (13?) on the surface of the substrate covered with the first conductive layer (11) providing the drain or source electrode function. The porous layers having substantially stacked pores. The production of filaments made of a semiconductor material is inside some of the stacked pores of the porous layers. The production of the upper conductive layer provides the source or drain electrode function on the surface of the stack of porous layers filled with filaments made of semiconductor material.
    Type: Grant
    Filed: February 5, 2007
    Date of Patent: March 20, 2012
    Assignee: Ecole Polytechnique
    Inventors: Didier Pribat, Costel-Sorin Cojocaru
  • Patent number: 7943519
    Abstract: An etchant, a method for fabricating a multi-layered interconnection line using the etchant, and a method for fabricating a thin film transistor (TFT) substrate using the etchant. The etchant for the multi-layered line comprised of molybdenum/copper/molybdenum nitride illustratively includes 10-20 wt % hydrogen peroxide, 1-5 wt % organic acid, a 0.1-1 wt % triazole-based compound, a 0.01-0.5 wt % fluoride compound, and deionized water as the remainder.
    Type: Grant
    Filed: June 22, 2006
    Date of Patent: May 17, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hong-sick Park, Shi-yul Kim, Jong-hyun Choung, Won-suk Shin
  • Patent number: 7767502
    Abstract: In a thin film semiconductor device realized on a flexible substrate, an electronic device using the same, and a manufacturing method thereof, the thin film semiconductor device and an electronic device include a flexible substrate, a semiconductor chip, which is formed on the flexible substrate, and a protective cap, which seals the semiconductor chip. Durability of the thin film semiconductor device against stress due to bending of the substrate is improved by using the protective cap.
    Type: Grant
    Filed: February 5, 2007
    Date of Patent: August 3, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Do-young Kim, Wan-jun Park, Young-soo Park, June-key Lee, Yo-sep Min, Jang-yeon Kwon, Sun-ae Seo, Young-min Choi, Soo-doo Chae
  • Patent number: 7524750
    Abstract: A process is provided for depositing an silicon oxide film on a substrate disposed in a process chamber. A process gas that includes a halogen source, a fluent gas, a silicon source, and an oxidizing gas reactant is flowed into the process chamber. A plasma having an ion density of at least 1011 ions/cm3 is formed from the process gas. The silicon oxide film is deposited over the substrate with a halogen concentration less than 1.0%. The silicon oxide film is deposited with the plasma using a process that has simultaneous deposition and sputtering components. The flow rate of the halogen source to the process chamber to the flow rate of the silicon source to the process chamber is substantially between 0.5 and 3.0.
    Type: Grant
    Filed: October 27, 2006
    Date of Patent: April 28, 2009
    Assignee: Applied Materials, Inc.
    Inventors: Srinivas D. Nemani, Young S. Lee, Ellie Y. Yieh, Anchuan Wang, Jason Thomas Bloking, Lung-Tien Han
  • Patent number: 7485024
    Abstract: A fabricating method of field emission triodes is provided. First, a cathode conductive layer, an insulator layer, and a gate layer are formed on a substrate. An opening is formed in the insulator layer and the gate layer to expose a portion of the cathode conductive layer. A metal layer is formed on the cathode conductive layer. A first anodization is performed so as to form a first metal anodization layer from a portion of the metal layer. After the first metal anodization layer is removed, a second metal anodization layer having a plurality of pores is formed. Thereafter, a catalyst layer is formed in the pores. Then, a plurality of carbon nanotubes are formed in the pores.
    Type: Grant
    Filed: October 12, 2005
    Date of Patent: February 3, 2009
    Assignee: Chunghwa Picture Tubes, Ltd.
    Inventors: Fu-Ming Pan, Po-Lin Chen, Chen-Chun Lin, Mei Liu, Chi-Neng Mo
  • Patent number: 7479417
    Abstract: A method for manufacturing a pixel electrode contact structure of a thin-film transistors liquid crystal display is disclosed. First, a transparent substrate having a first insulating layer thereon is provided. Afterward, a first metal layer and a second metal layer are sequentially formed on the substrate and then be patterned by a halftone technology and an etching process, wherein the second metal layer is removed within the pixel electrode contact area. In the meantime, the drain lines of the thin-film transistor comprising the first metal layer and the second metal layer are formed. Next, a patterned passivation layer is formed on the substrate. Finally, a pixel electrode layer directly connecting the first metal layers within the pixel electrode contact structure is formed on the substrate. This invention provides the pixel electrode contact structure with low contact resistance and prevents the current leakage from the drain line to the storage capacitor.
    Type: Grant
    Filed: October 23, 2007
    Date of Patent: January 20, 2009
    Assignee: Au Optronics
    Inventor: Wen-Yi Shyu
  • Patent number: 7439091
    Abstract: A light-emitting diode (LED) and a method for manufacturing the same are described. The method for manufacturing the LED comprises the following steps. An illuminant epitaxial structure is provided, in which the illuminant epitaxial structure has a first surface and a second surface on opposite sides, and a substrate is deposed on the first surface of the illuminant epitaxial structure. A metal layer is formed on the second surface of the illuminant epitaxial structure. An anodic oxidization step is performed to oxidize the metal layer, so as to form a metal oxide layer. An etching step is performed to remove a portion of the metal oxide layer, so as to form a plurality of holes in the metal oxide layer.
    Type: Grant
    Filed: February 22, 2007
    Date of Patent: October 21, 2008
    Assignee: Epistar Corporation
    Inventors: Shi-Ming Chen, Mau-Phon Houng, Chang-Hsing Chu, Te-Chi Yen
  • Patent number: 7393727
    Abstract: A thin-film transistor, a thin-film transistor sheet, an electric circuit, and a manufacturing method thereof are disclosed, the method comprising the steps of forming a semiconductor layer by providing a semiconductive material on a substrate, b) forming an insulating area, which is electrode material-repellent, by providing an electrode material-repellent material on the substrate, and c) forming a source electrode on one end of the insulating area and a drain electrode on the other end of the insulating area, by providing an electrode material.
    Type: Grant
    Filed: October 5, 2006
    Date of Patent: July 1, 2008
    Assignee: Konica Minolta Holdings, Inc.
    Inventor: Katsura Hirai
  • Patent number: 7387648
    Abstract: The invention relates to a coil type solid electrolytic capacitor containing solid organic polymer with high electrical conductivity as electrolyte and its manufacturing method. In the invention, such processes as oxidation, carbonization, immersing, chemical oxypolymerization, and so on are fully disclosed. The solid electrolytic capacitor of the invention has a pretty low equivalent series resistance (ESR), good impedance frequency properties, so can be used at a frequency above 1 MHz. And it has a high anti-ripple current capacity, wide applicable range of temperature, good temperature properties, large capacity, long life, and reliable performance, therefore can be widely applied in the fields of modern communication, computer, and high performance civilian and military electronic products.
    Type: Grant
    Filed: August 11, 2006
    Date of Patent: June 17, 2008
    Assignee: Samxon Electronics (Dong Guan) Co., Ltd.
    Inventor: Lik Wing Kee
  • Patent number: 7371674
    Abstract: An embodiment of the present invention is an interconnect technique. A nanostructure bump is formed on a die. The nanostructure bump has a template defining nano-sized openings and metallic nano-wires extending from the nano-sized openings. The die is attached to a substrate via the nanostructure bump.
    Type: Grant
    Filed: December 22, 2005
    Date of Patent: May 13, 2008
    Assignee: Intel Corporation
    Inventors: Daewoong Suh, Nachiket R. Raravikar
  • Patent number: 7368331
    Abstract: A thin-film transistor, a thin-film transistor sheet, an electric circuit, and a manufacturing method thereof are disclosed, the method comprising the steps of forming a semiconductor layer by providing a semiconductive material on a substrate, b) forming an isolating area, which is electrode material-repellent, by providing an electrode material-repellent material on the substrate, and c) forming a source electrode on one end of the insulating area and a drain electrode on the other end of the insulating area, by providing an electrode material.
    Type: Grant
    Filed: December 19, 2003
    Date of Patent: May 6, 2008
    Assignee: Konica Minolta Holdings, Inc.
    Inventor: Katsura Hirai
  • Patent number: 7335538
    Abstract: A method for manufacturing liquid crystal display substrates comprises the steps of: (a) providing a substrate having a transparent electrode layer and a metal layer; (b) forming a patterned photoresist layer through half-tone or diffraction; (c) defining signal line area and thin film diode area, or pixel area and conductive electrode-lines by etching; and (d) forming an oxidized layer on partial surface of the metal layer. The disclosure here provides a patterning process of lithography and etching with one photolithography of one single mask in the manufacturing of liquid crystal display substrates. Furthermore, the method disclosed here can effectively increase the yield of manufacturing, and reduce the cost of manufacturing.
    Type: Grant
    Filed: June 28, 2006
    Date of Patent: February 26, 2008
    Assignee: AU Optronics Corporation
    Inventors: Weng-Bing Chou, Ko-Ching Yang
  • Patent number: 7129183
    Abstract: A method of manufacturing an element having a microstructure of an excellent grating groove pattern or the like is obtained. This method of manufacturing an element having a microstructure comprises steps of forming a metal layer on a substrate, forming a dot column of concave portions on the surface of the metal layer and anodically oxidizing the surface of the metal layer formed with the dot column of concave portions while opposing this surface to a cathode surface thereby forming a metal oxide film having a grating groove pattern. When the interval between the concave portions of the dot column is reduced, therefore, a linear grating groove pattern having a large depth with a uniform groove width along the depth direction is easily formed in a self-organized manner.
    Type: Grant
    Filed: June 20, 2005
    Date of Patent: October 31, 2006
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Kazushi Mori, Mitsuaki Matsumoto, Koji Tominaga, Atsushi Tajiri, Koutarou Furusawa