Abstract: The present invention provides semiconductor devices with super junction drift regions that are capable of blocking voltage. A super junction drift region is an epitaxial semiconductor layer located between a top electrode and a bottom electrode of the semiconductor device. The super junction drift region includes a plurality of pillars having P type conductivity, formed in the super junction drift region, which are surrounded by an N type material of the super junction drift region.

Abstract: In general, in a semiconductor active element such as a normally-off JFET based on SiC in which an impurity diffusion speed is significantly lower than in silicon, gate regions are formed through ion implantation into the side walls of trenches formed in source regions. However, to ensure the performance of the JFET, it is necessary to control the area between the gate regions thereof with high precision. Besides, there is such a problem that, since a heavily doped PN junction is formed by forming the gate regions in the source regions, an increase in junction current cannot be avoided. The present invention provides a normally-off power JFET and a manufacturing method thereof and forms the gate regions according to a multi-epitaxial method which repeats a process including epitaxial growth, ion implantation, and activation annealing a plurality of times.

Abstract: A solar cell, comprising: a doped silicon substrate, the silicon substrate comprising a front surface and a rear surface; a front phosphorous diffusion layer formed on the front surface; a front anti-reflective layer formed on the front phosphorous diffusion layer; a front metal electrode on the front surface in ohmic contact with the front phosphorous diffusion layer through the front anti-reflective layer; a rear passivation layer formed on the rear surface; a rear metal electrode in a pattern on the rear surface passing through the rear passivation layer; and a rear p+ diffusion area on the rear surface between the rear passivation layer and a boron-doped region of the silicon substrate, the rear p+ diffusion area surrounding the rear metal electrode.

Abstract: In general, in a semiconductor active element such as a normally-off JFET based on SiC in which an impurity diffusion speed is significantly lower than in silicon, gate regions are formed through ion implantation into the side walls of trenches formed in source regions. However, to ensure the performance of the JFET, it is necessary to control the area between the gate regions thereof with high precision. Besides, there is such a problem that, since a heavily doped PN junction is formed by forming the gate regions in the source regions, an increase in junction current cannot be avoided. The present invention provides a normally-off power JFET and a manufacturing method thereof and forms the gate regions according to a multi-epitaxial method which repeats a process including epitaxial growth, ion implantation, and activation annealing a plurality of times.

Abstract: A method of fabricating a metal interconnection and a method of fabricating image sensor using the same are provided. The method of fabricating a metal interconnection including forming a interlayer dielectric layer on a substrate, forming an interconnection formation region in the interlayer dielectric layer, performing an ultraviolet (UV) treatment on the substrate after the interconnection formation region is formed and forming a metal interconnection in the interconnection formation region.

Abstract: A gas inlet is disposed in a lower portion of a reaction chamber, a copper substrate is disposed in an upper portion thereof, and a tungsten catalytic body heated to 1600° C. is disposed midway between the two. Ammonia gas introduced from the gas inlet is decomposed by the tungsten catalytic body, a chemical species generated by the decomposition reacts with a surface of the copper substrate, and reduces and removes a contaminant on the copper surface, and a Cu3N thin film is formed on the copper substrate surface. This Cu3N film has the action of a film which prevents the oxidation of copper. This Cu3N film is thermally decomposed and removed when heated to temperatures of not less than 300° C., leaving a clean copper surface behind.

Abstract: A method of manufacturing a semiconductor device, comprising forming a metal silicide gate electrode on a semiconductor substrate surface. The method also comprises exposing the metal silicide gate electrode and the substrate surface to a cleaning process. The cleaning process includes a dry plasma etch using an anhydrous fluoride-containing feed gas and a thermal sublimation configured to leave the metal silicide gate electrode substantially unaltered. The method also comprises depositing a metal layer on source and drain regions of the substrate surface and annealing the metal layer and the source and drain regions of the substrate surface to form metal silicide source and drain contacts.

Abstract: A method of fabricating an opening or plug. In the process of forming the opening, before a photoresist layer is formed over a dielectric layer, a treatment process is performed to form a film on the dielectric layer, wherein the film can suppress the outgasing phenomenon of the dielectric layer and prevent the later formed photoresist layer from reacting with the running-off composition component from the dielectric layer. Therefore, the problem of incomplete development due to outgasing of the dielectric layer can be solved. Additionally, in the procedure for forming a plug, before a block layer is forming on a surface of a via, a treatment process is performed to form a film on the surface of the via. Therefore, the problem of having defects inside the block layer caused by outgasing of the dielectric layer can be overcome.

Abstract: A substrate processing apparatus has a processing space provided with a holding stand for holding a substrate to be processed. A hydrogen catalyzing member is arranged in the processing space to face the substrate and for decomposing hydrogen molecules into hydrogen radicals H*. A gas feeding port is arranged in the processing space on an opposite side of the hydrogen catalyzing member to the substrate for feeding a processing gas including at least hydrogen gas. An interval between the hydrogen catalyzing member and the substrate on the holding stand is set less than the distance that the hydrogen radicals H* can reach.

Abstract: A metal layer is formed over a metal oxide, where the metal oxide is formed over a semiconductor substrate. A predetermined critical dimension of the metal layer is determined. A first etch is performed to etch the metal layer down to the metal oxide and form footings at the sidewalls of the metal layer. A second etch to remove the footings to target a predetermined critical dimension, wherein the second etch is selective to the metal oxide. In one embodiment, a conductive layer is formed over the metal layer. The bulk of the conductive layer may be etched leaving a portion in contact with the metal layer. Next, the portion left in contact with the metal layer may be etched using chemistry selective to the metal layer.

Abstract: A substrate processing method includes the steps of removing carbon from a surface of a silicon substrate by irradiating an ultraviolet light on the surface in an essentially ultraviolet nonreactive gas atmosphere and forming an oxide film or an oxynitride film on the surface of the silicon substrate by irradiating an ultraviolet light thereon in an essentially ultraviolet reactive gas atmosphere. Further, a computer readable storage medium stores therein a program for controlling the substrate processing method.

Abstract: A process is provided for fabricating a via 52 between bonded wafers without undercutting an organic bonding material 32. The process for forming the via 52 in a structure including a dielectric material 14 and an organic bonding material 32, comprises forming a resist material 42 on the dielectric layer 14 and etching through the dielectric layer 14 and the organic bonding material 32 with 60CF4/20Ar/60CHF3/20N2. The resist may then be removed with an anisotropic high density oxygen plasma.