By Vapor Etching Only (epo) Patents (Class 257/E21.31)
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Patent number: 11447697Abstract: A substrate processing gas of the present invention contains IF5; and IF7, in which a content of the IF5 is equal to or more than 1 ppm and equal to or less than 2% on a volume basis with respect to a total amount of the IF5 and the IF7.Type: GrantFiled: March 5, 2019Date of Patent: September 20, 2022Assignee: CENTRAL GLASS COMPANY, LIMITEDInventors: Akifumi Yao, Yuuta Takeda, Jun Eto
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Patent number: 11134575Abstract: A method for manufacturing a dual conductor laminated substrate includes providing a first laminate including a first insulating layer and a first conductive layer; defining a first trace pattern including one or more traces in the first laminate; providing a second laminate including a second insulating layer and a second conductive layer; defining a second trace pattern including one or more traces in the second laminate; defining access holes in the second insulating layer; at least one of depositing and stenciling a conductive material in the access holes of the second insulating layer; and aligning and attaching the first laminate to the second laminate to create a laminated substrate.Type: GrantFiled: September 30, 2019Date of Patent: September 28, 2021Inventor: Timothy Hughes
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Patent number: 11121027Abstract: A method for the via etching steps of a substrate manufacturing process flow is provided. The substrate processing techniques described provide for etching vias by providing a protection layer on the via sidewall during at least portions of the via etching process. In one embodiment, an atomic layer deposition (ALD) layer is formed on the via sidewalls to protect the dielectric layers through which the via is formed. The ALD layer may lessen bowing effects in low k dielectric layers which may result from etching barrier low k (blok) layers or from other process steps. After via formation, the ALD layer may be removed. The techniques are particularly suited for forming skip vias and other high aspect ratio vias formed in low k and ultra-low k dielectric layers.Type: GrantFiled: December 7, 2018Date of Patent: September 14, 2021Assignee: Tokyo Electron LimitedInventors: Yen-Tien Lu, Xinghua Sun, Eric Chih-Fang Liu, Andrew W. Metz
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Patent number: 10886140Abstract: Methods of etching film stacks to from gaps of uniform width are described. A film stack is etched through a hardmask. A conformal liner is deposited in the gap. The bottom of the liner is removed. The film stack is selectively etched relative to the liner. The liner is removed. The method may be repeated to a predetermined depth.Type: GrantFiled: July 26, 2019Date of Patent: January 5, 2021Assignee: Applied Materials, Inc.Inventors: Shishi Jiang, Pramit Manna, Bo Qi, Abhijit Basu Mallick, Rui Cheng, Tomohiko Kitajima, Harry S. Whitesell, Huiyuan Wang
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Patent number: 10504912Abstract: Various embodiments of the present application are directed towards a method to integrate NVM devices with a logic or BCD device. In some embodiments, an isolation structure is formed in a semiconductor substrate. The isolation structure demarcates a memory region of the semiconductor substrate, and further demarcates a peripheral region of the semiconductor substrate. The peripheral region may, for example, correspond to BCD device or a logic device. A doped well is formed in the peripheral region. A dielectric seal layer is formed covering the memory and peripheral regions, and further covering the doped well. The dielectric seal layer is removed from the memory region, but not the peripheral region. A memory cell structure is formed on the memory region using a thermal oxidation process. The dielectric seal layer is removed from the peripheral region, and a peripheral device structure including a gate electrode is formed on the peripheral region.Type: GrantFiled: February 26, 2018Date of Patent: December 10, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Cheng-Bo Shu, Chung-Jen Huang, Yun-Chi Wu
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Patent number: 10497578Abstract: Methods for etching a bottom anti-reflective coating (BARC) and/or an anti-reflective coating (ARC) and/or a dielectric anti-reflective coating (DARC) to form high aspect ratio features using an etch process are provided. The methods described herein advantageously facilitate profile and dimension control of features with high aspect ratios through a proper sidewall and bottom management scheme during the bottom anti-reflective coating (BARC) and/or an anti-reflective coating (ARC) and/or a dielectric anti-reflective coating (DARC) open process.Type: GrantFiled: July 22, 2016Date of Patent: December 3, 2019Assignee: Applied Materials, Inc.Inventors: Hailong Zhou, Gene Lee, Abhijit Patil, Shan Jiang, Akhil Mehrotra, Jonathan Kim
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Patent number: 10217662Abstract: A method for processing an interconnection structure for minimizing barrier sidewall recess, comprises the following steps: step 1, remove a metal layer (408) to generate a uniform dishing value inside the recessed area (409), the uniform dishing value is generated to make sure that the top surface of the metal layer (408) in the recessed area (409) is aligned with the bottom surface of the hard mask layer (405), step 2, introduce noble-gas-halogen compound gas to remove a first barrier layer (406) on top surface and at least a portion of a second barrier layer (407) on sidewall by a gas phase chemical reaction process, the top surface of the second barrier layer (407) on sidewall is aligned with the bottom surface of the hard mask layer (405), step 3, introduce oxidizing gas to generate a barrier surface oxide (411) on the top surface of the second barrier layer (407) on sidewall, a metal surface oxide (412) is generated at the same time, step 4, introduce noble-gas-halogen compound gas to remove hard mask lType: GrantFiled: August 12, 2015Date of Patent: February 26, 2019Assignee: ACM Research (Shanghai) Inc.Inventors: Zhaowei Jia, Jian Wang, Hui Wang
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Patent number: 9543148Abstract: Various embodiments herein relate to methods, apparatus and systems for forming a recessed feature in a dielectric-containing stack on a semiconductor substrate. In many embodiments, a mask shrink layer is deposited on a patterned mask layer to thereby narrow the openings in the mask layer. The mask shrink layer may be deposited through a vapor deposition process including, but not limited to, atomic layer deposition or chemical vapor deposition. The mask shrink layer can result in narrower, more vertically uniform etched features. In some embodiments, etching is completed in a single etch step. In some other embodiments, the etching may be done in stages, cycled with a deposition step designed to deposit a protective sidewall coating on the partially etched features. Metal-containing films are particularly suitable as mask shrink films and protective sidewall coatings.Type: GrantFiled: September 1, 2015Date of Patent: January 10, 2017Assignee: Lam Research CorporationInventors: Eric A. Hudson, Mark H. Wilcoxson, Kalman Pelhos, Hyunjong Shim, Merrett Wong
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Patent number: 9306109Abstract: A semiconductor device manufacturing method is provided. The method includes forming a first, second and third films, forming a first mask pattern on the third film, forming a gate electrode by using the first mask pattern, forming a second mask pattern having an opening above a portion of the first mask pattern and a region adjacent to the gate electrode, and performing ion implantation by using the first and second mask patterns. The gate electrode formation includes etching the third film, etching the second film and overetching the second film by using a first, second and third processing gases. A first, second and third depositions formed on the sidewalls of the gate electrode in the third and second films etching and overetching, contain at least one of chlorine or bromine and do not contain fluorine.Type: GrantFiled: June 18, 2015Date of Patent: April 5, 2016Assignee: CANON KABUSHIKI KAISHAInventors: Hiroaki Sano, Takashi Usui
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Patent number: 9018109Abstract: A thin film transistor in which deterioration at initial operation is not likely to be caused and a manufacturing method thereof. A transistor which includes a gate insulating layer at least whose uppermost surface is a silicon nitride layer, a semiconductor layer over the gate insulating layer, and a buffer layer over the semiconductor layer and in which the concentration of nitrogen in the vicinity of an interface between the semiconductor layer and the gate insulating layer, which is in the semiconductor layer is lower than that of the buffer layer and other parts of the semiconductor layer. Such a thin film transistor can be manufactured by exposing the gate insulating layer to an air atmosphere and performing plasma treatment on the gate insulating layer before the semiconductor layer is formed.Type: GrantFiled: March 2, 2010Date of Patent: April 28, 2015Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hidekazu Miyairi, Erika Kato, Kunihiko Suzuki
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Patent number: 8598039Abstract: This invention relates to a method and apparatus by integrating semiconductor manufacturing processes of stress free electrochemical copper polishing (SFP), removal of the Tantalum oxide or Titanium oxide formed during SFP process and XeF2 gas phase etching barrier layer Ta/TaN or Ti/TiN process. Firstly, at least portion of plated copper film is polished by SFP. Secondly the barrier metal oxide film formed during SFP process is etched away by etchant. Finally, the barrier layer Ta/TaN or Ta/TiN is removed with XeF2 gas phase etching. The apparatus accordingly consists of three sub systems: stress free copper electropolishing system, barrier layer oxide film removal system and barrier layer Ta/TaN or Ti/TiN gas phase etching system.Type: GrantFiled: August 20, 2008Date of Patent: December 3, 2013Assignee: ACM Research (Shanghai) Inc.Inventors: Jian Wang, Zhaowei Jia, Junping Wu, Liangzhi Xie, Hui Wang
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Patent number: 8471994Abstract: A liquid crystal display device including first and second substrates, with a liquid crystal layer sealed therebetween; and first and second electrodes formed, respectively, on the first and second substrates. A first molecule orientation film is formed on the first substrate so as to cover the first electrode and a second molecule orientation film formed on the second substrate so as to cover the second electrode. A polarizer with a light absorption axis P is provided outside of the first substrate, and an analyzer with a light absorption axis A is provided outside of the second substrate. The light absorption axis A crosses the light absorption axis P. A plurality of micro structures are associated with at least one of the first and second electrodes, wherein the micro structures are obliquely arranged with respect to the light absorption axis P and the light absorption axis A.Type: GrantFiled: March 18, 2011Date of Patent: June 25, 2013Assignee: Sharp Kabushiki KaishaInventors: Shingo Kataoka, Arihiro Takeda, Takahiro Sasaki, Tsutomu Seino, Yoshio Koike, Hidefumi Yoshida, Yuichi Inoue, Kazutaka Hanaoka, Seiji Tanuma, Takatoshi Mayama, Kimiaki Nakamura, Hideo Chida, Seiji Doi, Tetsuya Fujikawa, Takashi Takagi, Hiroyasu Inoue
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Patent number: 8441070Abstract: A sinker layer is in contact with a first conductivity-type well, and is separated from a first conductivity-type collector layer and a second conductivity-type drift layer. A second conductivity-type diffusion layer (second second-conductivity-type high-concentration diffusion layer) is formed in the surface layer of the sinker layer. The second conductivity-type diffusion layer has a higher impurity concentration than that of the sinker layer. The second conductivity-type diffusion layer and the first conductivity-type collector layer are isolated from each other with an element isolation insulating film interposed therebetween.Type: GrantFiled: August 6, 2012Date of Patent: May 14, 2013Assignee: Renesas Electronics CorporationInventor: Hiroki Fujii
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Publication number: 20130059437Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes forming a film containing boron on a semiconductor substrate, forming a film containing silicon oxide on the film containing boron, patterning the film containing silicon oxide and etching the film containing boron with a gas containing chlorine by using the patterned film containing silicon oxide as a mask.Type: ApplicationFiled: March 8, 2012Publication date: March 7, 2013Inventor: Yusuke KASAHARA
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Patent number: 8264037Abstract: A sinker layer is in contact with a first conductivity-type well, and is separated from a first conductivity-type collector layer and a second conductivity-type drift layer. A second conductivity-type diffusion layer (second second-conductivity-type high-concentration diffusion layer) is formed in the surface layer of the sinker layer. The second conductivity-type diffusion layer has a higher impurity concentration than that of the sinker layer. The second conductivity-type diffusion layer and the first conductivity-type collector layer are isolated from each other with an element isolation insulating film interposed therebetween.Type: GrantFiled: January 20, 2012Date of Patent: September 11, 2012Assignee: Renesas Electronics CorporationInventor: Hiroki Fujii
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Patent number: 8258063Abstract: A method of manufacturing a metal gate/high K dielectric gate stack includes the steps of: forming an interfacial layer of SiON or SiO2 on a silicon substrate; depositing a high K dielectric film on the interfacial layer; performing a rapid thermal anneal of the high K dielectric film; depositing a TaN metal gate electrode film on the high K dielectric film; depositing a polysilicon gate layer on the TaN metal gate electrode film, and then depositing a hard mask layer; patterning a photoresist mask, and performing an anisotropic etching of the hard mask layer; removing the photoresist mask, and etching the polysilicon by reactive ion etching with the hard mask as masking layer using a mixed gas of Cl2/HBr; and etching the TaN metal gate electrode/high K dielectric gate stack by reactive ion etching with the hard mask as masking layer using BCl3-based etchant gas.Type: GrantFiled: September 21, 2010Date of Patent: September 4, 2012Assignee: Institute of Microelectronics, Chinese Academy of SciencesInventors: Qiuxia Xu, Yongliang Li
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Patent number: 8120104Abstract: A sinker layer is in contact with a first conductivity-type well, and is separated from a first conductivity-type collector layer and a second conductivity-type drift layer. A second conductivity-type diffusion layer (second second-conductivity-type high-concentration diffusion layer) is formed in the surface layer of the sinker layer. The second conductivity-type diffusion layer has a higher impurity concentration than that of the sinker layer. The second conductivity-type diffusion layer and the first conductivity-type collector layer are isolated from each other with an element isolation insulating film interposed therebetween.Type: GrantFiled: January 31, 2011Date of Patent: February 21, 2012Assignee: Renesas Electronics CorporationInventor: Hiroki Fujii
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Publication number: 20110186908Abstract: A sinker layer is in contact with a first conductivity-type well, and is separated from a first conductivity-type collector layer and a second conductivity-type drift layer. A second conductivity-type diffusion layer (second second-conductivity-type high-concentration diffusion layer) is formed in the surface layer of the sinker layer. The second conductivity-type diffusion layer has a higher impurity concentration than that of the sinker layer. The second conductivity-type diffusion layer and the first conductivity-type collector layer are isolated from each other with an element isolation insulating film interposed therebetween.Type: ApplicationFiled: January 31, 2011Publication date: August 4, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventor: Hiroki FUJII
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Patent number: 7981734Abstract: A manufacturing method of a thin film transistor includes forming a pair of source/drain electrodes on a substrate, such that the source/drain electrodes define a gap therebetween; forming low resistance conductive thin films, which define a gap therebetween, on the source/drain electrodes; and forming an oxide semiconductor thin film layer on upper surface of the low resistance conductive thin films and in the gap defined between the low resistance conductive thin films so that the oxide semiconductor thin film layer functions as a channel. The low resistance conductive thin films and the oxide semiconductor thin film layer are etched so that side surfaces of the resistance conductive thin films and corresponding side surfaces of the oxide semiconductor thin film layer coincide with each other in a channel width direction of the channel. A gate electrode is mounted over the oxide semiconductor thin film layer.Type: GrantFiled: July 8, 2009Date of Patent: July 19, 2011Assignees: Kochi Industrial Promotion Center, Casio Computer Co., Ltd.Inventors: Mamoru Furuta, Takashi Hirao, Hiroshi Furuta, Tokiyoshi Matsuda, Takahiro Hiramatsu, Hiromitsu Ishii, Hitoshi Hokari, Motohiko Yoshida
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Patent number: 7952675Abstract: A liquid crystal display device including 1st and 2nd substrates. A linearly extending scan electrode and a linearly extending signal electrode are formed on the 1st substrate, wherein the scan electrode extends in a direction crossing an extension direction of the signal electrode. A liquid crystal layer is between the 1st and 2nd substrates, and a pixel electrode is formed on the 1st substrate. The pixel electrode is electrically connected to both the scan and signal electrodes. The pixel electrode is divided into at least two regions such that at least two domains of different liquid crystal orientation directions are defined within a single pixel. A 1st and a 2nd of the at least two regions are not aligned in parallel with either the extension direction of the scan electrode or the extension direction of the signal electrode. The 1st and 2nd regions each include a micro-cutout pattern.Type: GrantFiled: November 11, 2008Date of Patent: May 31, 2011Assignee: Sharp Kabushiki KaishaInventors: Shingo Kataoka, Arihiro Takeda, Takahiro Sasaki, Tsutomu Seino, Yoshio Koike, Hidefumi Yoshida, Yuichi Inoue, Kazutaka Hanaoka, Seiji Tanuma, Takatoshi Mayama, Kimiaki Nakamura, Hideo Chida, Seiji Doi, Tetsuya Fujikawa, Takashi Takagi, Hiroyasu Inoue
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Patent number: 7759748Abstract: A semiconductor device is disclosed that comprises a fully silicided electrode formed of an alloy of a semiconductor material and a metal, a workfunction modulating element for modulating a workfunction of the alloy, and a dielectric in contact with the fully silicided electrode. At least a part of the dielectric which is in direct contact with the fully silicided electrode comprises a stopping material for substantially preventing the workfunction modulating element from implantation into and/or diffusing towards the dielectric. A method for forming such a semiconductor device is also disclosed.Type: GrantFiled: October 23, 2007Date of Patent: July 20, 2010Assignees: IMEC, Taiwan Semiconductor Manufacturing Company Ltd. (TSMC)Inventors: HongYu Yu, Shou-Zen Chang, Jorge Adrian Kittl, Anne Lauwers, Anabela Veloso
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Patent number: 7718457Abstract: A method of producing a MEMS device provides an apparatus having structure on a first layer that is proximate to a substrate. The apparatus has a space proximate to the structure. The method adds doped material to the space. The doped material dopes at least a portion of the first layer.Type: GrantFiled: April 5, 2005Date of Patent: May 18, 2010Assignee: Analog Devices, Inc.Inventors: Thomas Chen, Michael Judy
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Patent number: 7709394Abstract: A method for processing a substrate having an insulation film and a metal layer thereon comprises the steps of supplying a carboxylic acid anhydride to the substrate, and heating the substrate during the step of supplying the carboxylic acid anhydride to the substrate.Type: GrantFiled: March 19, 2007Date of Patent: May 4, 2010Assignees: Tokyo Electron Limited, Fujitsu Limited, Ebara CorporationInventors: Hidenori Miyoshi, Kenji Ishikawa, Yukio Takigawa, Yoshihiro Nakata, Hideki Tateishi
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Publication number: 20100009534Abstract: A method for patterning a semiconductor device can include forming a conductive layer over a semiconductor substrate; alternatively forming positive photoresists and negative photoresists over the conductive layer, forming a plurality of first conductive lines by selectively removing a portion of the conductive layer using the positive photoresist and the negative photoresist as masks; forming an oxide film over the semiconductor substrate including the first conductive lines and the conductive layer; performing a planarization process over the oxide film using the uppermost surface of the first conductive line as a target; removing the plurality of first conductive lines using the oxide film as a mask; forming a plurality if trenches in the semiconductor substrate and removing a portion of the oxide film to expose the uppermost surface of the conductive layer; and then forming a plurality of second conductive lines by removing the exposed conductive layer using the oxide film as a mask.Type: ApplicationFiled: September 15, 2009Publication date: January 14, 2010Inventor: Eun-Soo Jeong
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Patent number: 7572685Abstract: On a glass substrate, an insulating protective layer comprising SiO2 film is formed, and an active layer comprising a p-Si film is formed thereon. Further, a first gat insulating film comprising an SiN film which serves as a lower layer and a second gate insulating film comprising an SiN film which serves as an upper layer are stacked thereon. The second gate insulating layer is then removed by etching with a gate electrode formed thereon acting as a mask. Thus, ions can be doped only through the first gate insulating film to the p-Si film with a low acceleration energy.Type: GrantFiled: April 25, 2006Date of Patent: August 11, 2009Assignee: Sanyo Electric Co., Ltd.Inventor: Koji Suzuki
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Patent number: 7553721Abstract: Flash memory devices and methods for fabricating the same. In one example embodiment, a method of fabricating a flash memory includes various acts. First, a tunnel oxide layer is formed on an active region of a semiconductor substrate. Next, a gate region is formed by sequentially forming a floating gate, a gate insulating layer, and a control gate over the tunnel oxide layer. Then, a sidewall oxide layer is formed on a gate region. Next, a fluorine plasma ion implantation process is performed on the sidewall oxide layer. Then, a nitride layer is deposited on the sidewall oxide layer. Next, an etch process is performed to form spacer insulating layers.Type: GrantFiled: December 4, 2007Date of Patent: June 30, 2009Assignee: Dongbu Hitek Co., Ltd.Inventor: Jae Yuhn Moon
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Patent number: 7486366Abstract: In a liquid crystal display device, liquid crystal molecules are oriented in a vertical direction to the first substrate and the second substrate by the first molecule orientation film and the second molecule orientation film, respectively, in a non-driving state. A structural pattern is formed so as to extend in a first direction parallel to a surface of the liquid crystal layer and so as to form, in a driving state, an electric field periodically changing in a second direction that is parallel to the liquid crystal layer and vertical to the first direction. The liquid crystal molecules substantially tilt in the first direction in the driving state.Type: GrantFiled: October 2, 2006Date of Patent: February 3, 2009Assignee: Sharp Kabushiki KaishaInventors: Shingo Kataoka, Arihiro Takeda, Takahiro Sasaki, Tsutomu Seino, Yoshio Koike, Hidefumi Yoshida, Yuichi Inoue, Kazutaka Hanaoka, Seiji Tanuma, Takatoshi Mayama, Kimiaki Nakamura, Hideo Chida
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Publication number: 20080253166Abstract: According to one embodiment of the present invention, a memory cell array comprises a plurality of voids, the spatial positions and dimensions of the voids being chosen such that mechanical stress occurring within the memory cell array is at least partly compensated by the voids.Type: ApplicationFiled: April 16, 2007Publication date: October 16, 2008Inventors: Wolfgang Raberg, Cay-Uwe Pinnow
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Publication number: 20080246076Abstract: Methods for nanopatterning and methods for production of nanoparticles utilizing such nanopatterning are described herein. In exemplary embodiments, masking nanoparticles are disposed on various substrates and to form a nanopatterned mask. Using various etching and filling techniques, nanoparticles and nanocavities can be formed using the masking nanoparticles and methods described throughout.Type: ApplicationFiled: January 3, 2008Publication date: October 9, 2008Applicant: NANOSYS, Inc.Inventor: Jian Chen
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Patent number: 7419916Abstract: The present invention provides a method for preventing the defect the in shape of via holes cased when an alumina mask is used for the dry etching of an interlayer insulator composed of an SiOC film in the dual damascene process in which via holes are formed prior to forming wiring trenches. That is, after forming an alumina mask on an interlayer insulator composed of a low-k SiOC film via a cap insulator, the cap insulator and the interlayer insulator are dry-etched with using a photoresist film as a mask to form via holes. Next, after removing the photoresist film, the inside of the via holes are cleaned by using dilute hydrofluoric acid solution to remove alumina residue. Thereafter, the cap insulator and the interlayer insulator are dry-etched with using the alumina mask as a mask to form wiring trenches.Type: GrantFiled: September 7, 2006Date of Patent: September 2, 2008Assignee: Renesas Technology Corp.Inventors: Junji Noguchi, Hideo Aoki, Shoji Hotta, Takayuki Oshima
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Patent number: 7371688Abstract: A process for the selective removal of a substance from a substrate for etching and/or cleaning applications is disclosed herein. In one embodiment, there is provided a process for removing a substance from a substrate comprising: providing the substrate having the substance deposited thereupon wherein the substance comprises a transition metal ternary compound, a transition metal quaternary compound, and combinations thereof; reacting the substance with a process gas comprising a fluorine-containing gas and optionally an additive gas to form a volatile product; and removing the volatile product from the substrate to thereby remove the substance from the substrate.Type: GrantFiled: September 15, 2004Date of Patent: May 13, 2008Assignee: Air Products and Chemicals, Inc.Inventors: Bing Ji, Martin Jay Plishka, Dingjun Wu, Peter Richard Badowski, Eugene Joseph Karwacki, Jr.
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Publication number: 20080038929Abstract: Provided is a dry etching method for an oxide semiconductor film containing at least In, Ga, and Zn, which includes etching an oxide semiconductor film in a gas atmosphere containing a halogen-based gas.Type: ApplicationFiled: July 10, 2007Publication date: February 14, 2008Applicant: CANON KABUSHIKI KAISHAInventor: Chienliu Chang
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Patent number: 7259105Abstract: A method of fabricating the gate spacers of semiconductor devices is disclosed. An example method forms a gate on a semiconductor substrate, deposits a buffer oxide layer and a nitride layer sequentially on the whole semiconductor substrate including the gate, and forms spacers by etching the nitride layer.Type: GrantFiled: December 30, 2004Date of Patent: August 21, 2007Assignee: Dongbu Electronics Co., Ltd.Inventor: In Su Kim
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Patent number: 7208424Abstract: A metal layer is formed over a metal oxide, where the metal oxide is formed over a semiconductor substrate. A predetermined critical dimension of the metal layer is determined. A first etch is performed to etch the metal layer down to the metal oxide and form footings at the sidewalls of the metal layer. A second etch to remove the footings to target a predetermined critical dimension, wherein the second etch is selective to the metal oxide. In one embodiment, a conductive layer is formed over the metal layer. The bulk of the conductive layer may be etched leaving a portion in contact with the metal layer. Next, the portion left in contact with the metal layer may be etched using chemistry selective to the metal layer.Type: GrantFiled: September 17, 2004Date of Patent: April 24, 2007Assignee: Freescale Semiconductor, Inc.Inventors: Tab A. Stephens, Brian J. Goolsby, Bich-Yen Nguyen, Voon-Yew Thean
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Patent number: 7166543Abstract: Methods of forming a metal oxide surface that is enriched with metal oxide in its higher oxidation state for use in a semiconductor device are provided. A metal oxide surface that is enriched with metal oxide in its higher oxidation state for use in a semiconductor device is also provided.Type: GrantFiled: August 30, 2004Date of Patent: January 23, 2007Assignee: Micron Technology, Inc.Inventors: Stephen W. Russell, Max Hineman