With Channel Containing Layer, E.g., P-base, Fo Rmed In Or On Drain Region, E.g., Dmos Transistor (epo) Patents (Class 257/E21.417)
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Publication number: 20120231597Abstract: A manufacturing method for a high voltage transistor includes the following steps. A substrate is provided. A P-type epitaxial (P-epi) layer is provided above the substrate. An N-well is formed in the P-epi layer. A P-well is formed in the P-epi layer. Field oxide (FOX) layers are formed above the P-epi layer. A gate oxide (GOX) layer is formed between the FOX layers. P-type implants are doped into the P-well or N-type implants are doped into the N-well to adjust an electrical function of the high voltage transistor.Type: ApplicationFiled: March 7, 2011Publication date: September 13, 2012Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Yu-Hsien Chin, Chih-Chia Hsu, Yin-Fu Huang
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Publication number: 20120228704Abstract: A high-voltage transistor is formed in a deep well of a first conductivity type that has been formed in a semiconductor substrate or epitaxial layer of a second conductivity type. A body region of the second conductivity type is formed in the deep well, into which a source region of the first conductivity type is formed. A drain region of the first conductivity type is formed in the deep well and separated from the body region by a drift region in the deep well. A gate dielectric layer is formed over the body region, and a first polysilicon layer formed over the gate dielectric layer embodies the gate of the transistor. The field plate dielectric layer is formed over the drift region after the gate has been formed. Finally, the field plate dielectric is covered by a second polysilicon layer having a field plate positioned over the field plate dielectric layer in the drift region.Type: ApplicationFiled: March 7, 2011Publication date: September 13, 2012Inventor: Dong-Hyuk Ju
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Publication number: 20120228705Abstract: An LDMOS is formed with a second gate stack over the n? drift region, having a common gate electrode with the gate stack, and having a higher work function than the gate stack. Embodiments include forming a first conductivity type well, having a source, surrounded by a second conductivity type well, having a drain, in a substrate, forming first and second gate stacks on the substrate over a portion of the first well and a portion of the second well, respectively, the first and second gate stacks sharing a common gate electrode, and tuning the work functions of the first and second gate stacks to obtain a higher work function for the second gate stack. Other embodiments include forming the first gate stack with a first high-k dielectric and the second gate stack with a second high-k dielectric, and forming the first and second gate stacks with asymmetric dielectrics.Type: ApplicationFiled: March 11, 2011Publication date: September 13, 2012Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Eng Huat Toh, Jae Gon Lee, Chung Foong Tan, Elgin Quek
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Patent number: 8264037Abstract: A sinker layer is in contact with a first conductivity-type well, and is separated from a first conductivity-type collector layer and a second conductivity-type drift layer. A second conductivity-type diffusion layer (second second-conductivity-type high-concentration diffusion layer) is formed in the surface layer of the sinker layer. The second conductivity-type diffusion layer has a higher impurity concentration than that of the sinker layer. The second conductivity-type diffusion layer and the first conductivity-type collector layer are isolated from each other with an element isolation insulating film interposed therebetween.Type: GrantFiled: January 20, 2012Date of Patent: September 11, 2012Assignee: Renesas Electronics CorporationInventor: Hiroki Fujii
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Publication number: 20120223384Abstract: The present invention discloses a high voltage device and a manufacturing method thereof. The high voltage device includes: a first conductive type substrate in which isolation regions are formed for defining a device region; a gate formed on the first conductive type substrate; a source and a drain formed in the device region and located at both sides of the gate respectively, and doped with second conductive type impurities; a second conductive type well, which is formed in the first conductive type substrate, and surrounds the drain from top view; and a first deep trench isolation structure, which is formed in the first conductive type substrate, and is located in the second conductive type well between the source and the drain from top view, wherein the depth of the first deep trench isolation structure is deeper than the second conductive type well from the cross-sectional view.Type: ApplicationFiled: March 1, 2011Publication date: September 6, 2012Inventors: TSUNG-YI HUANG, Kuo-Hsuan Lo
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Publication number: 20120217579Abstract: The present invention discloses a high voltage device and a manufacturing method thereof. The high voltage device includes: a substrate, having a P (or N) type well and an isolation structure for defining a device region; a drift region, located in the device region, having a first region and a second region wherein the first region is an N (or P) type region, and the second region is a P (or N) type region or an N (or P) type region with different dopant concentration from the first region, and from top view, the first region and the second region include sub-regions distributed in the drift region; an N (or P) type source and drain; and a gate on a surface of the substrate, between the source and drain in the device region.Type: ApplicationFiled: August 8, 2011Publication date: August 30, 2012Inventors: Tsung-Yi Huang, Ying-Shiou Lin
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Patent number: 8247870Abstract: A method for integration is disclosed herein. The method includes forming an N-type double drain (NDD) layer, and fabricating at least one transistor from a controller circuitry and a transistor switch on a single chip. The controller circuitry is operable for controlling the transistor switch.Type: GrantFiled: September 25, 2007Date of Patent: August 21, 2012Assignee: O2Micro, Inc.Inventors: Jungcheng Kao, Luming Guo
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Publication number: 20120205669Abstract: In a semiconductor device according to the present invention, a p-type well region disposed in an outer peripheral portion of the power semiconductor device is divided into two parts, that is, an inside and an outside, and a field oxide film having a greater film thickness than the gate insulating film is provided on a well region at the outside to an inside of an inner periphery of the well region. Therefore, it is possible to prevent, in the gate insulating film, a dielectric breakdown due to the voltage generated by the flow of the displacement current in switching.Type: ApplicationFiled: October 14, 2009Publication date: August 16, 2012Applicant: Mitsubishi Electric CorporationInventors: Naruhisa Miura, Shuhei Nakata, Kenichi Ohtsuka, Shoyu Watanabe, Shiro Hino, Akihiko Furukawa
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Publication number: 20120199904Abstract: A field drain insulating part has a first insulating film and a high dielectric constant insulating film. The first insulating film is positioned at least in the center of the field drain insulating part in a plan view. The high dielectric constant insulating film is positioned at a part close to a drain region in the edge of the bottom surface of the field drain insulating part, and has a higher dielectric constant than the first insulating film. The high dielectric constant insulating film is not positioned in the center of the field drain insulating part in a plan view.Type: ApplicationFiled: January 26, 2012Publication date: August 9, 2012Applicant: RENESAS ELECTRONICS CORPORATIONInventor: Kenji SASAKI
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Patent number: 8236640Abstract: Embodiments of the present invention describe a semiconductor device implementing the reduced-surface-field (RESURF) effect. The semiconductor device comprises a source/drain region having a plurality of isolation regions interleaved with source/drain extension regions. A gate electrode is formed on the semiconductor device, where the gate electrode includes gate finger elements formed over the isolation regions to induce capacitive coupling. The gate finger elements enhance the depletion of the source/drain extension regions, thus inducing a higher breakdown voltage.Type: GrantFiled: December 18, 2009Date of Patent: August 7, 2012Assignee: Intel CorporationInventor: Michael Andrew Smith
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Publication number: 20120193707Abstract: The present invention discloses a high voltage multigate device and a manufacturing method thereof. The high voltage multigate device includes: a semiconductor fin doped with first conductive type impurities; a dielectric layer, which overlays a portion of the semiconductor fin; a gate which overlays the dielectric layer; a drain doped with second conductive type impurities, which is formed in the semiconductor fin or coupled to the semiconductor fin; a source doped with second conductive type impurities, which is formed in the semiconductor fin or coupled to the semiconductor fin, wherein the drain and the source are located at different sides of the gate; and a drift region or a well doped with second conductive type impurities, which is formed in the semiconductor fin at least between the drain and the gate.Type: ApplicationFiled: March 24, 2011Publication date: August 2, 2012Inventors: Tsung-Yi Huang, Chien-Wei Chiu
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Publication number: 20120193709Abstract: A high-voltage MOS transistor has a semiconductor substrate formed with a first well of a first conductivity type in which a drain region and a drift region are formed and a second well of a second, opposite conductivity type in which a source region and a channel region are formed, a gate electrode extends over the substrate from the second well to the first well via a gate insulation film, wherein there is formed a buried insulation film in the drift region underneath the gate insulation film at a drain edge of the gate electrode, there being formed an offset region in the semiconductor substrate between the channel region and the buried insulation film, wherein the resistance of the offset region is reduced in a surface part thereof by being introduced with an impurity element of the first conductivity type with a concentration exceeding the first well.Type: ApplicationFiled: November 10, 2011Publication date: August 2, 2012Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Takae SUKEGAWA, Youichi Momiyama
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Patent number: 8232594Abstract: A semiconductor device includes an isolation layer formed on and/or over a semiconductor substrate to define an isolation layer, a drift area formed in an active area separated by the isolation layer, a pad nitride layer pattern formed in a form of a plate on the drift area, and a gate electrode having step difference between lateral sides thereof due to the pad nitride layer pattern.Type: GrantFiled: December 21, 2009Date of Patent: July 31, 2012Assignee: Dongbu HiTek Co., Ltd.Inventor: Hyun-Tae Kim
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Patent number: 8232613Abstract: Example embodiments relate to a method of forming a germanium (Ge) silicide layer, a semiconductor device including the Ge silicide layer, and a method of manufacturing the semiconductor device. A method of forming a Ge silicide layer according to example embodiments may include forming a metal layer including vanadium (V) on a silicon germanium (SiGe) layer. The metal layer may have a multiple-layer structure and may further include at least one of platinum (Pt) and nickel (Ni). The metal layer may be annealed to form the germanium silicide layer. The annealing may be performed using a laser spike annealing (LSA) method.Type: GrantFiled: November 3, 2010Date of Patent: July 31, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Chang-wook Moon, Hyun-deok Yang, Joong S. Jeon, Hwa-sung Rhee, Nae-in Lee, Weiwei Chen
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Publication number: 20120187483Abstract: The present invention discloses a double diffused metal oxide semiconductor (DMOS) device and a manufacturing method thereof. The DMOS device includes: an isolation structure for defining device regions; a gate with a ring-shaped structure; a drain located outside the ring; and a lightly doped drain, a source, and a body electrode located inside the ring. To increase the sub-threshold voltage at the corners of the gate, the corners are located completely on the isolation structure, or the lightly doped drain is apart from the corners by a predetermined distance.Type: ApplicationFiled: April 20, 2011Publication date: July 26, 2012Inventors: Ching-Yao Yang, Tsung-Yi Huang, Huan-Ping Chu, Hung-Der Su
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Patent number: 8227871Abstract: A semiconductor device and a method for manufacturing the same are disclosed. The semiconductor device includes a substrate having a first conductor-type, a buried layer of a second conductor-type on the substrate, a drain, and a first guard-ring on one side of the drain, a second guard-ring on one side of the first guard-ring, and a third guard-ring on one side of the second guard-ring.Type: GrantFiled: December 4, 2009Date of Patent: July 24, 2012Assignee: Dongbu HiTek Co., Ltd.Inventor: Choul Joo Ko
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Publication number: 20120175679Abstract: A novel semiconductor power transistor is presented. The semiconductor structure is simple and is based on a MOS configuration with a drift region and an additional gate that modulates the carrier density in the drift region, so that the control on the carrier transport is enhanced and the specific on-resistance per area is reduced. This characteristic enables the use of short gate lengths while maintaining the electric field under the gate within reasonable values in high voltage applications, without increasing the device on-resistance. It offers the advantage of extremely lower on-resistance for the same silicon area while improving on its dynamic performances with respect to the standard CMOS technology. Another inherent advantage is that the switching gate losses are smaller due to lower VGS voltages required to operate the device.Type: ApplicationFiled: January 10, 2011Publication date: July 12, 2012Inventors: Fabio Alessio Marino, Paolo Menegoli
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Publication number: 20120168817Abstract: Disclosed are embodiments of a lateral, extended drain, metal oxide semiconductor, field effect transistor (LEDMOSFET) having a high drain-to-body breakdown voltage. Discrete conductive field (CF) plates are adjacent to opposing sides of the drain drift region, each having an angled sidewall such that the area between the drain drift region and the CF plate has a continuously increasing width along the length of the drain drift region from the channel region to the drain region. The CF plates can comprise polysilicon or metal structures or dopant implant regions within the same semiconductor body as the drain drift region. The areas between the CF plates and the drain drift region can comprise tapered dielectric regions or, alternatively, tapered depletion regions within the same semiconductor body as the drain drift region. Also disclosed are embodiments of a method for forming an LEDMOSFET and embodiments of a silicon-controlled rectifier (SCR) incorporating such LEDMOSFETs.Type: ApplicationFiled: September 21, 2011Publication date: July 5, 2012Applicant: International Business Machines CorporationInventors: Michel J. Abou-Khalil, Alan B. Botula, Alvin J. Joseph, Theodore J. Letavic, James A. Slinkman
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Patent number: 8212329Abstract: A short channel Lateral MOSFET (LMOS) and method are disclosed with interpenetrating drain-body protrusions (IDBP) for reducing channel-on resistance while maintaining high punch-through voltage. The LMOS includes lower device bulk layer; upper source and upper drain region both located atop lower device bulk layer; both upper source and upper drain region are in contact with an intervening upper body region atop lower device bulk layer; both upper drain and upper body region are shaped to form a drain-body interface; the drain-body interface has an IDBP structure with a surface drain protrusion lying atop a buried body protrusion while revealing a top body surface area of the upper body region; gate oxide-gate electrode bi-layer disposed atop the upper body region forming an LMOS with a short channel length defined by the horizontal length of the top body surface area delineated between the upper source region and the upper drain region.Type: GrantFiled: November 6, 2010Date of Patent: July 3, 2012Assignee: Alpha and Omega Semiconductor Inc.Inventors: Shekar Mallikarjunaswamy, Amit Paul
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Patent number: 8212310Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type; a deep well of a second conductivity type formed in a portion of an upper layer portion of the semiconductor layer; a well of the first conductivity type formed in a portion of an upper layer portion of the deep well; a source layer of the second conductivity type formed in the well; a drain layer of the second conductivity type formed in the well apart from the source layer; and a contact layer of the second conductivity type formed outside the well in an upper layer portion of the deep well and connected to the drain layer. The drain layer is electrically connected to the deep well via the well by applying a driving voltage between the source layer and the drain layer.Type: GrantFiled: February 7, 2011Date of Patent: July 3, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Tomoko Matsudai, Norio Yasuhara, Kazutoshi Nakamura
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Publication number: 20120161232Abstract: An integrated circuit contains a voltage protection structure having a diode isolated DENMOS transistor with a guard element proximate to the diode and the DENMOS transistor. The guard element includes an active area coupled to ground. The diode anode is connected to an I/O pad. The diode cathode is connected to the DENMOS drain. The DENMOS source is grounded. A process of forming the integrated circuit is also disclosed.Type: ApplicationFiled: December 28, 2011Publication date: June 28, 2012Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Farzan Farbiz, Akram Salman
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Publication number: 20120153388Abstract: A semiconductor device in which a reliable high voltage p-channel transistor is formed without an increase in cost and the number of manufacturing steps. The transistor includes: a semiconductor substrate having a main surface and a p-type region therein; a p-type well region located over the p-type region and in the main surface, having a first p-type impurity region to obtain a drain electrode; an n-type well region adjoining the p-type well region along the main surface and having a second p-type impurity region to obtain a source electrode; a gate electrode between the first and second p-type impurity regions along the main surface; and a p-type buried channel overlying the n-type well region and extending along the main surface. The border between the n-type and p-type well regions is nearer to the first p-type impurity region than the gate electrode end near to the first p-type impurity region.Type: ApplicationFiled: December 7, 2011Publication date: June 21, 2012Inventor: Hirokazu SAYAMA
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Patent number: 8187937Abstract: A method for producing a semiconductor component has the following step: the front side (101) of the semiconductor body (100) is irradiated with high-energy particles using the terminal electrode (40) as a mask, in order to produce recombination centers (80A, 80B) in the semiconductor body (100) for the recombination of the first and second conduction type of charge carriers.Type: GrantFiled: January 3, 2008Date of Patent: May 29, 2012Assignee: Infineon Technologies AGInventors: Reiner Barthelmess, Hans-Joachim Schulze
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Publication number: 20120126320Abstract: A method for manufacturing a Power Metal-Oxide-Semiconductor Field-Effect-Transistor (MOSFET) has the steps of: implanting a base region of the Power MOSFET within an epitaxial layer of a semiconductor chip comprising an insulated gate structure, implanting a source link region on one side of the gate through a first mask, wherein the first mask is partially formed by an edge of the gate, the source link extending from a surface into the epitaxial layer and having a width defined by the first window, subsequently forming a spacer extending from the edge of the gate which defines the first window and forming a second mask which is partially formed by the spacer, and implanting a source region through the second mask.Type: ApplicationFiled: November 8, 2011Publication date: May 24, 2012Inventors: Rohan S. Braithwaite, Gregory Dix
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Publication number: 20120126319Abstract: A disposable structure displaced from an edge of a gate electrode and a drain region aligned to the disposable structure is formed. Thus, the drain region is self-aligned to the edge of the gate electrode. The disposable structure may be a disposable spacer, or alternately, the disposable structure may be formed simultaneously with, and comprise the same material as, a gate electrode. After formation of the drain regions, the disposable structure is removed. The self-alignment of the drain region to the edge of the gate electrode provides a substantially constant drift distance that is independent of any overlay variation of lithographic processes.Type: ApplicationFiled: February 2, 2012Publication date: May 24, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Natalie B. Feilchenfeld, Jeffrey P. Gambino, Xuefeng Liu, Benjamin T. Voegeli, Steven H. Voldman, Michael J. Zierak
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Publication number: 20120112274Abstract: According to one embodiment, a semiconductor device, including a semiconductor layer including a first region and a second region isolated from the first region, a source in a surface of the first region, a drain in a surface of the second region, a back-gate in the surface of the first region, an end of a drain side of the back-gate being located closer to the drain side than an end of the drain side of the source, a gate insulator on a surface of the semiconductor layer between the first region and the second region, a gate electrode on the gate insulator, a source electrode being contacted to both the source and the back-gate, and a drain electrode being contacted to the drain area.Type: ApplicationFiled: March 17, 2011Publication date: May 10, 2012Applicant: Kabushiki Kaisha ToshibaInventor: Tsubasa YAMADA
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Publication number: 20120112277Abstract: An integrated circuit containing a dual drift layer extended drain MOS transistor with an upper drift layer contacting a lower drift layer along at least 75 percent of a common length of the two drift layers. An average doping density in the lower drift layer is between 2 and 10 times an average doping density in the upper drift layer. A process of forming an integrated circuit containing a dual drift layer extended drain MOS transistor with a lower drift extension under the body region and an isolation link which electrically isolates the body region, using an epitaxial process. A process of forming an integrated circuit containing a dual drift layer extended drain MOS transistor with a lower drift extension under the body region and an isolation link which electrically isolates the body region, on a monolithic substrate.Type: ApplicationFiled: October 28, 2011Publication date: May 10, 2012Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Marie Denison, Sameer Pendharkar, Philip L. Hower
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Publication number: 20120104492Abstract: The present invention relates to a low on-resistance RESURF MOS transistor, comprising: a drift region; two isolation regions formed on the drift region; a first-doping-type layer disposed between the two isolation regions; and a second-doping-type layer disposed below the first-doping-type layer.Type: ApplicationFiled: October 29, 2010Publication date: May 3, 2012Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Chien-Wen CHU, Wing-Chor CHAN, Shyi-Yuan WU
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Publication number: 20120098065Abstract: An integrated circuit containing an MOS transistor with a drain drift region adjacent to the channel region, a field oxide element in the drain region, a first gate section over the channel region and a second gate section over the field oxide element, with a gap between the gate sections so that at least half of the drift region is not covered by gate. A process of forming an integrated circuit containing an MOS transistor with a drain drift region adjacent to the channel region, a field oxide element in the drain region, a first gate section over the channel region and a second gate section over the field oxide element, with a gap between the gate sections so that at least half of the drift region is not covered by gate, so that the source/drain implant is blocked from the drift region below the gap.Type: ApplicationFiled: October 25, 2011Publication date: April 26, 2012Applicant: TEXAS INSTRUMENTS INCORPORATEDInventor: Sameer P. Pendharkar
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Publication number: 20120098062Abstract: An integrated circuit includes an extended drain MOS transistor with parallel alternating active gap drift regions and field gap drift regions. The extended drain MOS transistor includes a gate having field plates over the field gap drift regions. The extended drain MOS transistor may be formed in a symmetric nested configuration. A process for forming an integrated circuit containing an extended drain MOS transistor provides parallel alternating active gap drift regions and field gap drift regions with a gate having field plates over the field gap drift regions.Type: ApplicationFiled: October 25, 2011Publication date: April 26, 2012Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Sameer P. Pendharkar, John Lin
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Publication number: 20120094458Abstract: An MOS-bipolar hybrid-mode LDMOS device has a main gate input and a control gate input wherein the device operates in an MOS mode when both gate inputs are enabled, and operates in a bipolar mode when the main gate input is enabled and the control gate input is disabled. The device can drive the gate of a power MOSFET to deliver the high current required by the power MOSFET while in the bipolar mode, and provide a fully switching between supply voltage and ground to the gate of the power MOSFET while in the MOS mode.Type: ApplicationFiled: October 21, 2011Publication date: April 19, 2012Applicant: Fairchild Semiconductor CorporationInventor: Jun Cai
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Patent number: 8159026Abstract: This invention provides a lateral high-voltage semiconductor device, which is a three-terminal one with two types of carriers for conduction and consists of a highest voltage region and a lowest voltage region referring to the substrate and a surface voltage-sustaining region between the highest voltage region and the lowest voltage region. The highest voltage region and the lowest region have an outer control terminal and an inner control terminal respectively, where one terminal is for controlling the flow of majorities of one conductivity type and another for controlling the flow of majorities of the other conductivity type. The potential of the inner control terminal is regulated by the voltage applied to the outer control terminal.Type: GrantFiled: April 2, 2010Date of Patent: April 17, 2012Assignee: University of Electronics Science and TechnologyInventor: Xingbi Chen
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Patent number: 8154078Abstract: A semiconductor structure is provided. A second conductivity type well region is disposed on a first conductivity type substrate. A gate structure comprising a first sidewall and second sidewall is provided. The first sidewall is disposed on the second conductivity type well region. A second conductivity type diffused source is disposed on the first conductivity type substrate outside of the second sidewall. A second conductivity type diffused drain is disposed on the second conductivity type well region outside of the first sidewall. First conductivity type buried rings are arranged in a horizontal direction, separated from each other, and formed in the second conductivity type well region. Doped profiles of the first conductivity type buried rings gradually become smaller in a direction from the second conductivity type diffused source to the second conductivity type diffused drain.Type: GrantFiled: February 17, 2010Date of Patent: April 10, 2012Assignee: Vanguard International Semiconductor CorporationInventors: Yih-Jau Chang, Shang-Hui Tu, Gene Sheu
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Publication number: 20120074492Abstract: Methods and systems for monolithically fabricating a lateral double-diffused MOSFET (LDMOS) transistor having a source, drain, and a gate on a substrate, with a process flow that is compatible with a CMOS process flow are described.Type: ApplicationFiled: December 5, 2011Publication date: March 29, 2012Applicant: VOLTERRA SEMICONDUCTOR CORPORATIONInventors: Budong Yu, Marco A. Zuniga
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Publication number: 20120074493Abstract: Transistors having improved breakdown voltages and methods of forming the same are provided herein. In one embodiment, a method of forming a transistor comprises the steps of: forming a drain and a source by doping a semiconductor with a first dopant type to form a first type of semiconductor, the drain and source being separated from one another, wherein the drain comprises a first drain region of a first dopant concentration adjacent a second drain region, such that at least a portion of the second drain region is positioned between the first drain region and the source, and further comprising forming an intermediate region by doping the semiconductor so as to form a second type of semiconductor intermediate the drain and source, the intermediate region spaced apart from the second drain region.Type: ApplicationFiled: September 29, 2010Publication date: March 29, 2012Applicant: ANALOG DEVICES, INC.Inventors: Edward John Coyne, Paul Malachy Daly, Jagar Singh, Seamus Whiston, Patrick Martin McGuinness, William Allan Lane
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Patent number: 8143126Abstract: A method is used to form a vertical MOS transistor. The method utilizes a semiconductor layer. An opening is etched in the semiconductor layer. A gate dielectric is formed in the opening that has a vertical portion that extends to a top surface of the first semiconductor layer. A gate is formed in the opening having a major portion laterally adjacent to the vertical portion of the gate dielectric and an overhang portion that extends laterally over the vertical portion of the gate dielectric. An implant is performed to form a source region at the top surface of the semiconductor layer while the overhang portion is present.Type: GrantFiled: May 10, 2010Date of Patent: March 27, 2012Assignee: Freescale Semiconductor, Inc.Inventors: Jingjing Chen, Ganming Qin, Edouard D. de Fresart, Pon Sung Ku
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Patent number: 8138047Abstract: In the specification and drawing a super junction semiconductor device is disclosed. The super junction semiconductor device comprises a P-type layer, a N+ substrate, a N-type layer, a silicon dioxide layer and a P+ layer. The N+ substrate is disposed under the P-type layer. The N-type layer is disposed on the N+ substrate. The silicon dioxide layer is disposed between the N-type layer and the P-type layer. The P+ layer is disposed on the P-type layer and the N-type layer.Type: GrantFiled: April 7, 2009Date of Patent: March 20, 2012Assignee: inergy Technology Inc.Inventor: Ming-Jang Lin
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Publication number: 20120061756Abstract: According to one embodiment, a semiconductor device includes a channel formation region of first conductivity type, a first offset region of second conductivity type, a first insulating region, a first liner layer, a first semiconductor region of second conductivity type, a second semiconductor region of second conductivity type, a gate insulating film, and a gate electrode. The first liner layer is provided between the first offset region and the first insulating region. The first semiconductor region of second conductivity type is provided on the side opposite to the channel formation region sandwiching the first insulating region therebetween and having impurity concentration higher than that of the first offset region. The second semiconductor region of second conductivity type is provided on the side opposite to the first semiconductor region sandwiching the channel formation region therebetween and having impurity concentration higher than that of the first offset region.Type: ApplicationFiled: September 12, 2011Publication date: March 15, 2012Applicant: Kabushiki Kaisha ToshibaInventor: Takao IBI
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Publication number: 20120061688Abstract: In a power semiconductor device that switches at a high speed, a displacement current flows at a time of switching, so that a high voltage occurs which may cause breakdown of a thin insulating film such as a gate insulating film.Type: ApplicationFiled: July 15, 2009Publication date: March 15, 2012Applicant: Mitsubishi Electric CorporationInventors: Shoyu Watanabe, Shuhei Nakata, Naruhisa Miura
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Publication number: 20120043608Abstract: An partially depleted Dieler LDMOSFET transistor (100) is provided which includes a substrate (150), a drift region (110) surrounding a drain region (128), a first well region (107) surrounding source region (127), a well buffer region (106) separating the drift region and first well region to at least partly define a first channel region, a gate electrode (118) formed over the first channel region having a source-side gate edge aligned with the first well region (107), an LDD extension region (120) extending from the source region to the channel region, and a dielectric RESURF drain extension structure (161) formed at the drain of the gate electrode (118) using the plurality of STI stripes (114).Type: ApplicationFiled: August 20, 2010Publication date: February 23, 2012Inventors: Hongning Yang, Jiang-Kai Zuo
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Patent number: 8120104Abstract: A sinker layer is in contact with a first conductivity-type well, and is separated from a first conductivity-type collector layer and a second conductivity-type drift layer. A second conductivity-type diffusion layer (second second-conductivity-type high-concentration diffusion layer) is formed in the surface layer of the sinker layer. The second conductivity-type diffusion layer has a higher impurity concentration than that of the sinker layer. The second conductivity-type diffusion layer and the first conductivity-type collector layer are isolated from each other with an element isolation insulating film interposed therebetween.Type: GrantFiled: January 31, 2011Date of Patent: February 21, 2012Assignee: Renesas Electronics CorporationInventor: Hiroki Fujii
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Publication number: 20120037987Abstract: A semiconductor structure includes a substrate, a first well region of a first conductivity type overlying the substrate, a second well region of a second conductivity type opposite the first conductivity type overlying the substrate, a cushion region between and adjoining the first and the second well regions, an insulation region in a portion of the first well region and extending from a top surface of the first well region into the first well region, a gate dielectric extending from over the first well region to over the second well region, wherein the gate dielectric has a portion over the insulation region, and a gate electrode on the gate dielectric.Type: ApplicationFiled: October 24, 2011Publication date: February 16, 2012Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsueh-Liang Chou, Chen-Bau Wu, Weng-Chu Chu, Tsung-Yi Huang, Fu-Jier Fan
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Publication number: 20120037989Abstract: LDMOS devices having a single-strip contact pad in the source region, and related methods of manufacturing are disclosed. The LDMOS may comprise a first well lightly doped with a first dopant and formed into a portion of a substrate, the first well having a drain region at its surface heavily doped with the first dopant, and a second well lightly doped with a second dopant formed in another portion of the substrate, the second well having a source region at its surface comprising first portions heavily doped with the first dopant directly adjacent second portions heavily doped with the second dopant. Also, the LDMOS device may comprise a field oxide at the upper surface of the substrate between the source and drain regions, and contacting the first well but separated from the second well, and a gate formed partially over the field oxide and partially over the source region.Type: ApplicationFiled: August 16, 2010Publication date: February 16, 2012Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Hsueh-I Huang, Shuo-Lun Tu, Ming-Tung Lee, Yin-Fu Huang, Shih-Chin Lien, Shyi-Yuan WU
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Publication number: 20120037988Abstract: A semiconductor device can include a source region near a working top surface of a semiconductor region. The device can also include a gate located above the working top surface and located laterally between the source and a drain region. The source region and the gate can at least partially laterally overlap a body region near the working top surface. The source region can include a first portion having the first conductivity type, a second portion having a second conductivity type, and a third portion having the second conductivity type. The second portion can be located laterally between the first and third portions and can penetrate into the semiconductor region to a greater depth than the third portion but no more than the first portion. The lateral location of the third portion can be determined at least in part using the lateral location of the gate.Type: ApplicationFiled: August 11, 2010Publication date: February 16, 2012Inventor: Jifa Hao
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Publication number: 20120032262Abstract: A p-channel LDMOS device with a controlled n-type buried layer (NBL) is disclosed. A Shallow Trench Isolation (STI) oxidation is defined, partially or totally covering the drift region length. The NBL layer, which can be defined with the p-well mask, connects to the n-well diffusion, thus providing an evacuation path for electrons generated by impact ionization. High immunity to the Kirk effect is also achieved, resulting in a significantly improved safe-operating-area (SOA). The addition of the NBL deep inside the drift region supports a space-charge depletion region which increases the RESURF effectiveness, thus improving BV. An optimum NBL implanted dose can be set to ensure fully compensated charge balance among n and p doping in the drift region (charge balance conditions). The p-well implanted dose can be further increased to maintain a charge balance, which leads to an Rdson reduction.Type: ApplicationFiled: August 5, 2010Publication date: February 9, 2012Applicants: LAAS-CNRS, ATMEL ROUSSET SASInventors: Willem-Jan Toren, Bruno Villard, Elsa Hugonnard-Bruyere, Gaetan Toulon, Frederic Morancho, Ignasi Cortes Mayol, Thierry Pedron
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Publication number: 20120032254Abstract: An electrostatic discharge (ESD) protection device includes a substrate; a source region of a first conductivity type in the substrate; a drain region of the first conductivity type in the substrate; a gate electrode overlying the substrate between the source region and the drain region; and a core pocket doping region of the second conductivity type within the drain region. The core pocket doping region does not overlap with an edge of the drain region.Type: ApplicationFiled: May 9, 2011Publication date: February 9, 2012Inventors: Ming-Tzong Yang, Ming-Cheng Lee
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Publication number: 20120018803Abstract: In one form a lateral MOSFET includes an active gate positioned laterally between a source region and a drain region, the drain region extending from an upper surface of a monocrystalline semiconductor body to a bottom surface of the monocrystalline semiconductor body, and a non-active gate positioned above the drain region. In another form the lateral MOSFET includes a gate positioned laterally between a source region and a drain region, the drain region extending from an upper surface of a monocrystalline semiconductor body to a bottom surface of the monocrystalline semiconductor body, the source region and the drain region being of a first conductivity type, a heavy body region of a second conductivity type in contact with and below the source region, and the drain region comprising a lightly doped drain (LDD) region proximate an edge of the gate and a sinker extending from the upper surface of the monocrystalline body to the bottom surface of the monocrystalline semiconductor body.Type: ApplicationFiled: September 29, 2011Publication date: January 26, 2012Inventors: Thomas E. Grebs, Gary M. Dolny, Daniel M. Kinzer
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Publication number: 20120018804Abstract: An LDMOSFET transistor (100) is provided which includes a substrate (101), an epitaxial drift region (104) in which a drain region (116) is formed, a first well region (107) in which a source region (112) is formed, a gate electrode (120) formed adjacent to the source region (112) to define a first channel region (14), and a grounded substrate injection suppression guard structure that includes a patterned buried layer (102) in ohmic contact with an isolation well region (103) formed in a predetermined upper region of the substrate so as to be spaced apart from the first well region (107) and from the drain region (116), where the buried layer (102) is disposed below the first well region (107) but not below the drain region (116).Type: ApplicationFiled: July 23, 2010Publication date: January 26, 2012Inventors: Vishnu K. Khemka, Stephen J. Cosentino, Tahir A. Khan, Adolfo C. Reyes, Ronghua Zhu
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Publication number: 20120009740Abstract: A method of manufacturing a SOI high voltage power chip with trenches is disclosed. The method comprises: forming a cave and trenches at a SOI substrate; filling oxide in the cave; oxidizing the trenches, forming oxide isolation regions for separating low voltage devices at the same time; filling oxide in the oxidized trenches; and then forming drain regions, source regions and gate regions for a high voltage power device and low voltage devices. The process involves depositing an oxide layer overlapping the cave of the SOI substrate. A SOI high voltage power chip thus made will withstand at least above 700V voltage.Type: ApplicationFiled: September 7, 2010Publication date: January 12, 2012Applicant: SHANGHAI INSTITUTE OF MICROSYSTEM AND INFORMATION TECHNOLOGY, CHINESE ACADEMYInventors: Xinhong Cheng, Zhongjian Wang, Yuehui Yu, Dawei He, Dawei Xu, Chao Xia
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Patent number: 8084817Abstract: A semiconductor device includes a high voltage first conduction type well in a semiconductor substrate, a second conduction type body in the high voltage first conduction type well, a source region in the second conduction type body, a trench in the high voltage first conduction type well, a first isolation oxide, an impurity doped polysilicon film, and a second isolation oxide stacked in the trench in succession, a drain region in the high voltage first conduction type well on one side of the trench, and a polygate on and/or over the high voltage first conduction type well.Type: GrantFiled: December 27, 2009Date of Patent: December 27, 2011Assignee: Dongbu HiTek Co., Ltd.Inventor: Mi-Young Kim