Abstract: Processes for selectively patterning a magnetic film structure generally include selectively etching an exposed portion of a freelayer disposed on a tunnel barrier layer by a wet process, which includes exposing the freelayer to an etchant solution comprising at least one acid and an organophosphorus acid inhibitor or salt thereof, stopping on the tunnel barrier layer.

Abstract: A memory device is provided. The memory device including memory cells having at least three stacked electrodes spaced apart pairwise by dielectric material so that the pairs of electrodes form respective capacitor layers. The capacitors are connected electrically in parallel to each other. The dielectric material is optionally ferroelectric material, in which case the capacitors are ferrocapacitors.

Abstract: A non-volatile memory device and a method for fabricating the same are provided. The method includes: forming a gate structure on a substrate, the gate structure including a first insulation layer, a first electrode layer for a floating gate and a second insulation layer; forming a third insulation layer on the gate structure covering predetermined regions of the substrate adjacent to the gate structure; and forming a second electrode layer for a control gate on the third insulation layer disposed on sidewalls of the gate structure and the predetermined regions of the substrate.

Abstract: A method of forming a STT-MTJ MRAM cell that utilizes transfer of spin angular momentum as a mechanism for changing the magnetic moment direction of a free layer. The device includes an IrMn pinning layer, a SyAP pinned layer, a naturally oxidized, crystalline MgO tunneling barrier layer that is formed on an Ar-ion plasma smoothed surface of the pinned layer and, in one embodiment, a free layer that comprises an amorphous layer of Co60Fe20B20. of approximately 20 angstroms thickness formed between two crystalline layers of Fe of 3 and 6 angstroms thickness respectively. The free layer is characterized by a low Gilbert damping factor and by very strong polarizing action on conduction electrons. The resulting cell has a low critical current, a high dR/R and a plurality of such cells will exhibit a low variation of both resistance and pinned layer magnetization angular dispersion.

Abstract: The fabrication of seek-scan probe (SSP) memory devices involves processing on both-sides of a wafer. However, there are temperature restrictions on the mover circuitry side of the wafer and doping level constrains for either side of wafer. Using a low doped EPI layer on a highly doped substrate solves this issue and provides good STO growth.

Abstract: In a method of forming a phase-change memory unit, a conductive layer is formed on a substrate having a trench. The conductive layer is planarized until the substrate is exposed to form a first electrode. A spacer partially covering the first electrode is formed. A phase-change material layer is formed on the first electrode and the second spacer. A second electrode is formed on the phase-change material layer. Reset/set currents of the phase-change memory unit may be reduced and deterioration of the phase-change material layer may be reduced and/or prevented.

Abstract: Ferroelectric structures and methods of making the structures are presented. The ferroelectric structures can include an electrode in contact with a ferroelectric thin film. The contact can be arranged so that a portion of the atoms of the ferroelectric thin film are in contact with at least a portion of the atoms of the electrode. The electrode can be made of metal, a metal alloy, or a semiconducting material. A second electrode can be used and placed in contact with the ferroelectric thin film. Methods of making and using the ferroelectric structures are also presented.

Abstract: Nonvolatile memory devices are provided and methods of manufacturing such devices. In the method, conductive layers and insulating layers are alternatingly stacked on a substrate. A first sub-active bar is formed which penetrates a first subset of the conductive layers and a first subset of the insulating layers. The first sub-active bar is electrically connected with the substrate. A second sub-active bar is formed which penetrates a second subset of the conductive layers and a second subset of the insulating layers. The second sub-active bar is electrically connected to the first sub-active bar. A width of a bottom portion of the second sub-active bar is less than a width of a top portion of the second sub-active bar.

Abstract: A memory comprises a number of word lines in a first direction, a number of bit lines in a second direction, each coupled to at least one of the word lines, and a number of memory elements, each coupled to one of the word lines and one of the bit lines. Each memory element comprises a top electrode for connecting to a corresponding word line, a bottom electrode for connecting to a corresponding bit line, a resistive layer on the bottom electrode, and at least two separate liners, each liner having resistive materials on both ends of the liner and each liner coupled between the top electrode and the resistive layer.

Abstract: A dual-gate non-volatile memory cell includes a first dielectric layer extending over a first gate, a semiconductor region extending over the first dielectric layer, a second dielectric layer comprising tunnel oxide extending over the semiconductor region, a ferroelectric layer extending over the second dielectric layer, and a second gate extending over the ferroelectric layer.

Abstract: The disclosed memory cell (10) comprises a graphene layer (16) having controllable resistance states representing data values of the memory cell (10) In one exemplary embodiment a non-volatile memory is provided by having a ferroelectric layer (18) control the resistance states. In the exemplary embodiment, binary ‘0’s and ‘1’s are respectively represented by low and high resistance states of the graphene layer (16), and these states are switched in a non-volatile manner by the polarization directions of the ferroelectric layer (18).

Abstract: Methods of forming planar carbon nanotube (“CNT”) resistivity-switching materials for use in memory cells are provided, that include depositing first dielectric material, patterning the first dielectric material, etching the first dielectric material to form a feature within the first dielectric material, depositing CNT resistivity-switching material over the first dielectric material to fill the feature at least partially with the CNT resistivity-switching material, depositing second dielectric material over the CNT resistivity-switching material, and planarizing the second dielectric material and the CNT resistivity-switching material so as to expose at least a portion of the CNT resistivity-switching material within the feature. Other aspects are also provided.

Abstract: A phase-change memory device and a method of manufacturing the same, wherein the phase-change memory device includes a semiconductor substrate having a switching device, a phase-change layer formed on the semiconductor substrate having the switching device to change a phase thereof as the switching device is driven, and a bottom electrode contact in contact with the switching device through a first contact area and in contact with the phase-change layer through a second contact area, which is smaller than the first contact area.

Abstract: A lower electrode (22) is provided on a semiconductor chip substrate (26). A lower electrode (22) is covered with a first interlayer insulating layer (27) from above. A first contact hole (28) is provided on the lower electrode (22) to penetrate through the first interlayer insulating layer (27). A low-resistance layer (29) forming the resistance variable layer (24) is embedded to fill the first contact hole (28). A high-resistance layer (30) is provided on the first interlayer insulating layer (27) and the low-resistance layer (29). The resistance variable layer (24) is formed by a multi-layer resistance layer including a single layer of the high-resistance layer (30) and a single layer of the low-resistance layer (29). The low-resistance layer (29) forming the memory portion (25) is isolated from at least its adjacent memory portion (25).

Abstract: A nonvolatile ferroelectric memory device using a silicon substrate includes an insulating layer formed in an etching region of the silicon substrate, a bottom word line formed in the insulating layer so as to be enclosed by the insulating layer, a floating channel layer formed over the bottom word line, an impurity layer formed at both ends of the floating channel layer and including a source region formed over the insulating layer and a drain region formed over the silicon substrate, a ferroelectric layer formed over the floating channel layer, and a word line formed over the ferroelectric layer.

Abstract: A method of manufacturing a magnetoresistive element includes a tunnel barrier forming step. The tunnel barrier forming step comprises a metal layer forming step of forming a metal layer to have a first thickness, a plasma processing step of performing a plasma treatment which exposes the metal layer to a plasma of an inert gas to etch the metal layer to have a second thickness smaller than the first thickness, and an oxidation step of oxidizing the metal layer having undergone the plasma treatment to form a metal oxide which forms a tunnel barrier.

Abstract: A first passive ferroelectric memory element comprising a first electrode system and a second electrode system, wherein said first electrode system is at least partly insulated from said second electrode system by an element system comprising at least one ferroelectric element, wherein said first electrode system is a conductive surface, or a conductive layer; wherein said second electrode system is an electrode pattern or a plurality of isolated conductive areas in contact with, for read-out or data-input purposes only, a plurality of conducting pins isolated from one another.

Abstract: A ferroelectric capacitor having a three-dimensional structure, a nonvolatile memory device having the same, and a method of fabricating the same are provided. The ferroelectric capacitor may include a trench-type lower electrode, at least one layer formed around the lower electrode, a ferroelectric layer (PZT layer) formed on the lower electrode and the at least one layer and an upper electrode formed on the ferroelectric layer. The at least one layer may be at least one insulating interlayer and the at least one layer may also be at least one diffusion barrier layer. The at least one layer may be formed of an insulating material excluding SiO2 or may have a perovskite crystal structure excluding Pb.

Abstract: A capacitor includes a pair of electrodes and a ferroelectric film sandwiched between the electrodes. The electrodes are provided perpendicular to the direction of the polarization axis of the ferroelectric film.

Abstract: Provided are a ferroelectric recording medium and a method of manufacturing the same. The ferroelectric recording medium includes a substrate, a plurality of supporting layers which are formed on the substrate, each of the supporting layers having at least two lateral surfaces; and data recording layers formed on the lateral surfaces of the supporting layers. First and second data recording layers may be respectively disposed on two facing lateral surfaces of each of the supporting layers. The supporting layers may be polygonal pillars having at least three lateral surfaces. A plurality of the supporting layers can be disposed at uniform intervals in a two-dimensional array.

Abstract: A ferroelectric memory device manufacturing method includes the steps of forming an interlayer isolating film for covering a transistor formed on a semiconductor substrate; forming a conductive plug in the interlayer insulating film to contact a diffusion region of the transistor formed on the semiconductor substrate; forming a ferroelectric capacitor including a lower electrode, a ferroelectric film and an upper electrode; and forming a compound film including silicon (Si) and a CH group on a surface of the interlayer insulating film and a surface of the conductive plug by depositing a Si compound containing Si atoms and the CH groups; wherein the compound film is formed after forming the conductive plug, and the compound film is formed before forming the lower electrode; and a self-orientation film is formed on a surface of the compound film.

Abstract: The present invention is to provide a semiconductor memory device capable of providing excellent storage properties, scaling and high integration and a method of fabricating the same. A semiconductor memory device has a multiferroic film exhibiting ferroelectricity and ferromagnetism, a channel region on an interface of a semiconductor substrate below the multiferroic film, source and drain regions formed on both sides of the channel region, a gate electrode (data write electrode) applying gate voltage to the multiferroic film to write data in such a way that the orientation of magnetization is changed as corresponding to the orientation of dielectric polarization, and source and drain electrodes (data read electrodes) that read data based on a deviation in a flow of the carrier, the deviation caused by applying the Lorentz force to the carrier flowing in the channel region from a magnetic field occurring in the channel region because of magnetization.

Abstract: A first electrode film, a ferroelectric film, and a second electrode film are accumulated above a semiconductor in this order, a hard mask is accumulated above the second electrode, scrub cleaning is performed on the surface of the hard mask with an surfactant, the hard mask on which the scrub cleaning is performed has been patterned according to a planar shape of a ferroelectric capacitor, and etching is performed by using as a hard mask the hard mask that has been patterned.

Abstract: A nonvolatile ferroelectric memory device includes a plurality of unit cells. Each of the unit cells includes a cell capacitor and a cell transistor. The cell capacitor includes a storage node, a ferroelectric layer, and a plate line. The cell capacitors of more than one of the plurality of unit cells are provided in a trench.

Abstract: Recesses are formed in the drain and source regions of an MOS transistor. An ohmic contact layer is formed in the recesses, and a stressed silicon-nitride layer is formed over the ohmic contact layer. The recesses allow the stressed silicon nitride layer to provide strain in the plane of the channel region. In a particular embodiment, a tensile silicon nitride layer is formed over recesses of an NMOS transistor in a CMOS cell, and a compressive silicon nitride layer is formed over recesses of a PMOS transistor in the CMOS cell. In a particular embodiment the stressed silicon nitride layer(s) is a chemical etch stop layer.

Abstract: The present invention describes a method including: providing a substrate; forming an underlying layer over the substrate; heating the substrate; forming a ferroelectric layer over the underlying layer, the ferroelectric layer having a thickness below a critical thickness, the underlying layer having a smaller lattice constant than the ferroelectric layer; cooling the substrate to room temperature; and inducing a compressive strain in the ferroelectric layer.

Abstract: A Spin-Dependent Tunnelling cell comprises a first barrier layer of a first material and a second barrier layer of a second material sandwiched between a first ferromagnetic layer and a second ferromagnetic layer. The first and second barrier layers are formed to a combined thicknesses so that a Tunnelling Magnetoresistance versus voltage characteristic of the cell has a maximum at a non-zero bias voltage.

Abstract: Provided is a ferroelectric memory including a silicon substrate, a transistor formed on the silicon substrate, and a ferroelectric capacitor formed above the transistor. The ferroelectric capacitor includes a lower electrode, a ferroelectric film formed on the lower electrode, an upper electrode formed on the ferroelectric film, and a metal film formed on the upper electrode.

Abstract: This disclosure relates to a system and method for creating nano-object arrays. A nano-object array can be created by exposing troughs in a corrugated surface to nano-objects and depositing the nano-objects within or orienting the nano-objects with the troughs.

Abstract: A magnetoresistive memory element has a free layer, and a write current path aligned with a free layer plane. The memory element has a pinned layer with a magnetization direction aligned with that of the free layer. A barrier layer is disposed between the free layer and the pinned layer. The free, barrier and pinned layers together form a layer stack that has a read current path that extends through the layer stack and that is not aligned with the write current path in the free layer.

Abstract: A nonvolatile memory device including one resistor and one transistor. The resistor may correspond to a resistance layer electrically connected to a first impurity region and a second impurity region of the transistor.

Abstract: In a method for manufacturing a nonvolatile memory device, an etch mask layer formed on a dielectric layer to define contact holes in the dielectric layer is slope-etched to form an etch mask pattern having an opening wider at the upper end thereof than the lower end thereof. Thus, the contact holes are defined in the dielectric layer to have a finer size than the upper end of the opening of the etch mask pattern. The method for manufacturing a nonvolatile memory device includes forming an etch mask pattern on a dielectric layer such that a width of a lower end of each opening defined in the etch mask pattern is less than a width of an upper end thereof; and defining contact holes by removing portions of the dielectric layer using the etch mask pattern.

Abstract: Provision of a process capable of preferably etching particularly PtMn used for a pin layer of an MRAM is an object: a dry etching method for performing dry etching on a layer including platinum and/or manganese by using pulse plasma and a production method of an MRAM, wherein the dry etching method is applied to processing of the pin layer. The MRAM is configured to have a memory portion comprising a magnetic memory element composed of tunnel magnetoresistive effect element formed by stacking a magnetic fixed layer having a fixed magnetization direction, a tunnel barrier layer and a magnetic layer capable of changing the magnetization direction.

Abstract: A ferroelectric polymer memory module includes a first set of layers including: a first ILD layer defining trenches therein; a first electrode layer disposed in the trenches of the first ILD layer; a first conductive polymer layer disposed on the first electrode layer and in the trenches of the first ILD layer; and a ferroelectric polymer layer disposed on the first conductive polymer layer and in the trenches of the first ILD layer; and a second set of layers disposed on the first set of layers to define memory cells therewith, the second set of layers including: a second ILD layer defining trenches therein; a second conductive polymer layer disposed in the trenches of the second ILD layer; and a second electrode layer disposed on the second conductive polymer layer.

Abstract: A nonvolatile memory device and its fabrication method of the present invention may ensure a margin of the threshold drive voltage during a design process of the device by forming a resistance layer determining phase of ReRAM along an upper edge of a lower electrode, and improve operating characteristics of the device

Abstract: Provided are a transparent nonvolatile memory thin film transistor (TFT) and a method of manufacturing the same. The memory TFT includes source and drain electrodes disposed on a transparent substrate. A transparent semiconductor thin layer is disposed on the source and drain electrodes and the transparent substrate interposed between the source and drain electrodes. An organic ferroelectric thin layer is disposed on the transparent semiconductor thin layer. A gate electrode is disposed on the organic ferroelectric thin layer in alignment with the transparent semiconductor thin layer. Thus, the transparent nonvolatile memory TFT employs the organic ferroelectric thin layer, the oxide semiconductor thin layer, and auxiliary insulating layers disposed above and below the organic ferroelectric thin layer, thereby enabling low-cost manufacture of a transparent nonvolatile memory device capable of a low-temperature process.

Abstract: A method for fabricating a ferroelectric memory device, including terminating a surface of the interlayer insulation film and a surface of the contact plug with an OH group; forming a layer containing Si, oxygen and a CH group on the surface of the interlayer insulation film and the contact hole terminated with the OH group by coating a Si compound containing a Si atom and a CH group in a molecule thereof; converting the layer containing Si, oxygen and the CH group to a layer containing nitrogen at a surface thereof, by substituting the CH group in the layer containing Si, oxygen and the CH group at least at a surface part thereof with nitrogen atoms; and forming a layer showing self-orientation on the surface containing nitrogen.

Abstract: A nonvolatile magnetic memory device including a magnetoresistance device having a recording layer formed of a ferromagnetic material for storing information by use of variation in resistance depending on the magnetization inversion state. The plan-view shape of the recording layer includes a pseudo-rhombic shape having four sides, at least two of the four sides each include a smooth curve having a central portion curved toward the center of the pseudo-rhombic shape. The easy axis of magnetization of the recording layer is substantially parallel to the longer axis of the pseudo-rhombic shape. The hard axis of magnetization of the recording layer is substantially parallel to the shorter axis of the pseudo-rhombic shape. The sides constituting the plan-view shape of the recording layer are smoothly connected to each other.

Abstract: An electro-resistance element that has a different configuration from conventional elements and is excellent in both affinity with semiconductor manufacturing processes and resistance change characteristics is provided. An electro-resistance element has two or more states in which electric resistance values between a pair of electrodes and is switchable from one of the two or more states into another by applying a predetermined voltage or current between the electrodes.

Abstract: A semiconductor device fabrication method that improves the efficiency of semiconductor device production. A plurality of wafer substrates are set and a process for fabricating semiconductor devices each having a ferroelectric capacitor is begun. After ferroelectric layers are formed over the plurality of wafer substrates, the ferroelectric layers formed are damaged. The plurality of wafer substrates are then rearranged and treatment is performed. In each step in which the ferroelectric layers formed may be damaged, the plurality of wafer substrates are rearranged and treatment is performed. As a result, retention characteristic variations among wafer substrates in the same lot are reduced and the productivity of semiconductor devices is improved.

Abstract: The magnetic device comprises a least two layers made of a magnetic material that are separated by at least one interlayer made of a non-magnetic material. The layers made of a magnetic material each have magnetization oriented substantially perpendicular to the plane of the layers. The layer of non-magnetic material induces an antiferromagnetic coupling field between the layers made of a magnetic material, the direction and amplitude of this field attenuating the effects of the ferromagnetic coupling field of magnetostatic origin that occurs between the magnetic layers.

Abstract: Ferroelectric structures and methods of making the structures are presented. The ferroelectric structures can include an electrode in contact with a ferroelectric thin film. The contact can be arranged so that a portion of the atoms of the ferroelectric thin film are in contact with at least a portion of the atoms of the electrode. The electrode can be made of metal, a metal alloy, or a semiconducting material. A second electrode can be used and placed in contact with the ferroelectric thin film. Methods of making and using the ferroelectric structures are also presented.

Abstract: An MRAM is disclosed that has a MTJ comprised of a ferromagnetic layer with a magnetization direction along a first axis, a super-paramagnetic (SP) free layer, and an insulating layer formed therebetween. The SP free layer has a remnant magnetization that is substantially zero in the absence of an external field, and in which magnetization is roughly proportional to an external field until reaching a saturation value. In one embodiment, a separate storage layer is formed above, below, or adjacent to the MTJ and has uniaxial anisotropy with a magnetization direction along its easy axis which parallels the first axis. In a second embodiment, the storage layer is formed on a non-magnetic conducting spacer layer within the MTJ and is patterned simultaneously with the MTJ. The SP free layer may be multiple layers or laminated layers of CoFeB. The storage layer may have a SyAP configuration and a laminated structure.

Abstract: A method of manufacturing a semiconductor device. The method comprises fabricating a ferroelectric capacitor. The capacitor's fabrication includes forming conductive and ferroelectric material layers on a semiconductor substrate, forming a hardmask layer on the conductive and ferroelectric material layers, forming an organic bottom antireflective coating layer on the hardmask layer, and, patterning the organic bottom antireflective coating layer. Seasoning in a hardmask etching chamber is substantially unaffected by the patterning.

Abstract: By selectively performing a pre-amorphization implantation process in logic areas and memory areas, the negative effect of the interaction between stressed overlayers and dislocation defects may be avoided or at least significantly reduced in the memory areas, thereby increasing production yield and stability of the memory areas.

Abstract: The invention relates to a semiconductor element used for a nonvolatile semiconductor storage device or the like, a semiconductor storage device using the same, a data writing method thereof, a data reading method thereof and a manufacturing method of those, and has an object to provide a semiconductor element in which scaling and integration of cells are possible, storage characteristics of data are excellent, and reduction in power consumption is possible, a semiconductor storage device using the same, a data writing method thereof, a data reading method thereof, and a manufacturing method of those.

Abstract: The present invention is directed to an SOI device with charging protection and methods of making same. In one illustrative embodiment, a device is formed on an SOI substrate including a bulk substrate, a buried insulation layer and an active layer. The device includes a transistor formed in an isolated portion of the active layer, the transistor including a gate electrode and a source region. The device further includes a first conductive bulk substrate contact extending through the active layer and the buried insulation layer, the first conductive bulk substrate contact being conductively coupled to the source region and the bulk substrate, and a second conductive bulk substrate contact extending through the active layer and the buried insulation layer, the second conductive bulk substrate being conductively coupled to the gate electrode and the bulk substrate.

Abstract: This disclosure relates to amorphous ferroelectric memory devices and methods for forming them.

Abstract: The semiconductor device according to the present invention includes a ferroelectric film and an electrode stacked on the ferroelectric film. The electrode has a multilayer structure of an electrode lower layer in contact with the ferroelectric film and an electrode upper layer stacked on the electrode lower layer. The electrode upper layer is made of a conductive material having an etching selection ratio with respect to the materials for the ferroelectric film and the electrode lower layer. The upper surface of the electrode upper layer is planarized.

Abstract: A composite arrangement has a substrate material with a main surface, a metal-insulator arrangement including a metal sheet with an insulation area on the main surface, and a magnetoresistive structure on the metal-insulator arrangement. Thereupon, a cover layer arrangement is heated, so that the same at least partially covers the magnetoresistive structure with a target thickness D, and finally the magnetoresistive structure is heated by light radiation with given wavelength ?. The absorbed portion of the emitted radiation depends on the actual thickness D? of the cover layer arrangement and the wavelength ?, wherein the target thickness D of the cover layer arrangement is adjusted so that, if the cover layer deviates from the target thickness D in a range of ±20% with reference to the target thickness D, a change of the absorbed portion of the emitted radiation in the magnetoresistive structure of less than ±40% is caused.