Read-only Memory Structures (rom), I.e., Nonvolatile Memory Structures (epo) Patents (Class 257/E21.662)

  • Patent number: 10339982
    Abstract: Under one aspect, a covered nanotube switch includes: (a) a nanotube element including an unaligned plurality of nanotubes, the nanotube element having a top surface, a bottom surface, and side surfaces; (b) first and second terminals in contact with the nanotube element, wherein the first terminal is disposed on and substantially covers the entire top surface of the nanotube element, and wherein the second terminal contacts at least a portion of the bottom surface of the nanotube element; and (c) control circuitry capable of applying electrical stimulus to the first and second terminals. The nanotube element can switch between a plurality of electronic states in response to a corresponding plurality of electrical stimuli applied by the control circuitry to the first and second terminals. For each different electronic state, the nanotube element provides an electrical pathway of different resistance between the first and second terminals.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: July 2, 2019
    Assignee: Nantero, Inc.
    Inventors: Claude L. Bertin, X. M. Henry Huang, Thomas Rueckes, Ramesh Sivarajan
  • Patent number: 9812460
    Abstract: The present disclosure relates to an integrated circuit (IC) that includes a HKMG hybrid non-volatile memory (NVM) device and that provides small scale and high performance, and a method of formation. In some embodiments, the integrated circuit includes a memory region having a NVM device with a pair of control gate electrodes separated from a substrate by corresponding floating gates. A pair of select gate electrodes are disposed at opposite sides of the pair of control gate electrodes comprise polysilicon. A logic region is disposed adjacent to the memory region and has a logic device with a metal gate electrode disposed over a logic gate dielectric and having bottom and sidewall surfaces covered by a high-k gate dielectric layer.
    Type: Grant
    Filed: May 24, 2016
    Date of Patent: November 7, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei Cheng Wu, Chien-Hung Chang
  • Patent number: 9589631
    Abstract: The invention refers to an ultrafast quench based nonvolatile bistable device which consists of an active material on a passive or active substrate which changes its physical properties, after exposure to a sufficiently temporally short external perturbation causing an ultrafast quench. The perturbation can be from an external ultrashort laser pulse or ultrafast electrical pulse from an electrooptic device or any other generator of ultrashort pulses. This change of the materials properties can be detected as a change of optical properties or electrical resistance. The dielectric properties can be reverted back to their original state by the application of a heat pulse applied by an electrical heater within the device or an external laser.
    Type: Grant
    Filed: September 30, 2013
    Date of Patent: March 7, 2017
    Assignee: Institut “Jozef Stefan”
    Inventors: Ljupka Stojcevska, Tomaz Mertelj, Igor Vaskivskyi, Dragan Mihailovic
  • Patent number: 9589982
    Abstract: Embodiments of the present invention provide improved three-dimensional memory cells, arrays, devices, and/or the like and associated methods. In one embodiment, a three-dimensional memory cell is provided. The three-dimensional memory cell comprises a first conductive layer; a third conductive layer spaced apart from the first conductive layer; a channel conductive layer connecting the first conductive layer and the third conductive layer to form an opening having internal surfaces; a dielectric layer disposed along the internal surfaces of the opening surrounded by the first conductive layer, the channel conductive layer and the third conductive layer; and a second conductive layer interposed and substantially filling a remaining open portion formed by the dielectric layer. The first conductive layer, the dielectric layer, and the second conductive layer are configured to form a staircase structure.
    Type: Grant
    Filed: September 15, 2015
    Date of Patent: March 7, 2017
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Cheng-Hsien Cheng, Chih-Wei Lee, Shaw-Hung Ku, Wen-Pin Lu
  • Patent number: 8993441
    Abstract: A method of forming a thin layer and a method of manufacturing a phase change memory device, the method of forming a thin layer including providing a first deposition source onto a substrate, the first deposition source not including tellurium; and providing a second deposition source onto the substrate, the second deposition source including a first tellurium precursor represented by the following Formula 1 and a second tellurium precursor represented by following the Formula 2: Te(CH(CH3)2)2??Formula 1 Ten(CH(CH3)2)2??Formula 2 wherein, in Formula 2, n is an integer greater than or equal to 2.
    Type: Grant
    Filed: February 25, 2014
    Date of Patent: March 31, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Do-Hyung Kim, Eun-Tae Kim, Sung-Lae Cho
  • Patent number: 8936984
    Abstract: A three-dimensional (3-D) nonvolatile memory device includes channel layers protruding perpendicular to a surface of a substrate, interlayer insulating layers and conductive layer patterns alternately formed to surround each of the channel layers, a slit formed between the channel layers, the slit penetrating the interlayer insulating layers and the conductive layer patterns, and an etch-stop layer formed on the surface of the substrate at the bottom of the slit.
    Type: Grant
    Filed: August 29, 2012
    Date of Patent: January 20, 2015
    Assignee: SK Hynix Inc.
    Inventor: Joo Hee Han
  • Patent number: 8927331
    Abstract: A method of manufacturing a nonvolatile memory device includes: forming a tantalum oxide material layer including an oxygen-deficient transition metal oxide; forming a tantalum oxide material layer including a transition metal oxide and having a degree of oxygen deficiency lower than a degree of oxygen deficiency of the tantalum oxide material layer; and exposing, after the forming of a tantalum oxide material layer, the tantalum oxide material layer to plasma generated from a noble gas.
    Type: Grant
    Filed: March 9, 2012
    Date of Patent: January 6, 2015
    Assignee: Panasonic Corporation
    Inventors: Ichirou Takahashi, Takumi Mikawa
  • Patent number: 8901632
    Abstract: A method of making a semiconductor structure includes forming a select gate over a substrate in an NVM region and a first protection layer over a logic region. A control gate and a storage layer are formed over the substrate in the NVM region. The control gate has a top surface below a top surface of the select gate. The charge storage layer is under the control gate, along adjacent sidewalls of the select gate and control gate, and is partially over the top surface of the select gate. A second protection layer is formed over the NVM portion and the logic portion. The first and second protection layers are removed from the logic region. A portion of the second protection layer is left over the control gate and the select gate. A gate structure, formed over the logic region, has a high k dielectric and a metal gate.
    Type: Grant
    Filed: September 30, 2013
    Date of Patent: December 2, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Asanga H. Perera, Cheong Min Hong, Sung-Taeg Kang, Byoung W. Min, Jane A. Yater
  • Patent number: 8853791
    Abstract: A memory cell includes diffusion regions formed in a substrate. Each of the diffusion regions extends along a vertical direction in a layout view at a substrate level. A first gate electrode structure at a gate electrode level is generally dogleg shaped. The first gate electrode structure extends in an oblique direction, turns to a horizontal direction, extends over and crosses the diffusion regions in the horizontal direction. A first contact structure at a contact level is generally rectangular shaped in the layout view of the cell. The first contact structure electrically connects a first source/drain region of the first diffusion region to the first gate electrode structure and the first source/drain region of the second diffusion region. The first contact structure extends from the first source/drain region of the first diffusion region to the first source/drain region of the second diffusion region at the contact level.
    Type: Grant
    Filed: November 6, 2006
    Date of Patent: October 7, 2014
    Assignee: Infineon Technologies AG
    Inventors: Uwe Paul Schroeder, Martin Ostermayr
  • Patent number: 8815681
    Abstract: Nonvolatile memory devices and methods of forming the same are provided, the nonvolatile memory devices may include first regions and second regions which extend in a first direction and are alternately disposed in a semiconductor substrate along a second direction crossing the first direction. Buried doped lines are formed at the first regions respectively and extend in the first direction. The buried doped lines may be doped with a dopant of a first conductivity type. Bulk regions doped with a dopant of a second conductivity type and device isolation patterns are disposed along the second direction. The bulk regions and the device isolation patterns may be formed in the second regions. Word lines crossing the buried doped lines and the bulk regions are formed parallel to one another. Contact structures are connected to the buried doped lines and disposed between the device isolation patterns.
    Type: Grant
    Filed: November 16, 2012
    Date of Patent: August 26, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yongsik Jeong, Jeonguk Han, Weonho Park, Byungsup Shim
  • Patent number: 8785268
    Abstract: A method for manufacturing a memory system is provided including forming a charge-storage layer on a first insulator layer including insulating the charge-storage layer from a vertical fin, forming a second insulator layer from the charge-storage layer, and forming a gate over the second insulator includes forming a fin field effect transistor.
    Type: Grant
    Filed: December 21, 2006
    Date of Patent: July 22, 2014
    Assignee: Spansion LLC
    Inventors: Wei Zheng, Lei Xue, Kuo-Tung Chang
  • Patent number: 8779495
    Abstract: An integrated circuit includes a first SONOS memory cell and a second SONOS memory cell. The second memory cell is stacked on the first memory cell.
    Type: Grant
    Filed: April 19, 2007
    Date of Patent: July 15, 2014
    Assignee: Qimonda AG
    Inventors: Thomas Happ, Jan Boris Philipp
  • Patent number: 8772852
    Abstract: Provided is a nonvolatile memory device including a common source. The device includes a first active region crossing a second active region, a common source disposed in the second active region, and a source conductive line disposed on the common source in parallel to the common source. The source conductive line is electrically connected to the common source.
    Type: Grant
    Filed: December 4, 2008
    Date of Patent: July 8, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hong-Soo Kim, Keon-Soo Kim
  • Patent number: 8766374
    Abstract: According to one disclosed embodiment, an integrated one-time programmable (OTP) semiconductor device pair includes a split-thickness dielectric under an electrode and over an isolation region formed in a doped semiconductor substrate, where a reduced-thickness center portion of the dielectric forms, in conjunction with the isolation region, programming regions of the OTP semiconductor device pair, and where the thicker, outer portions of the dielectric form dielectrics for transistor structures. In one embodiment, the split-thickness dielectric comprises a gate dielectric. In one embodiment, multiple OTP semiconductor device pairs are formed in an array that minimizes the number of connections required to program and sense states of specific OTP cells.
    Type: Grant
    Filed: July 19, 2012
    Date of Patent: July 1, 2014
    Assignee: Broadcom Corporation
    Inventor: Douglas Smith
  • Patent number: 8742586
    Abstract: A stacked multilayer structure according to an embodiment of the present invention comprises: a stacked layer part including a plurality of conducting layers and a plurality of insulating layers, said plurality of insulating layers being stacked alternately with each layer of said plurality of conducting layers, one of said plurality of insulating layers being a topmost layer among said plurality of conducting layers and said plurality of insulating layers; and a plurality of contacts, each contact of said plurality of contacts being formed from said topmost layer and each contact of said plurality of contacts being in contact with a respective conducting layer of said plurality of conducting layers, a side surface of each of said plurality of contacts being insulated from said plurality of conducting layers via an insulating film.
    Type: Grant
    Filed: October 18, 2013
    Date of Patent: June 3, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Makoto Mizukami, Takeshi Kamigaichi
  • Patent number: 8716814
    Abstract: The invention provides a processor obtained by forming a high functional integrated circuit using a polycrystalline semiconductor over a substrate which is sensitive to heat, such as a plastic substrate or a plastic film substrate. Moreover, the invention provides a wireless processor, a wireless memory, and an information processing system thereof which transmit and receive power or signals wirelessly. According to the invention, an information processing system includes an element forming region including a transistor which has at least a channel forming region formed of a semiconductor film separated into islands with a thickness of 10 to 200 nm, and an antenna. The transistor is fixed on a flexible substrate. The wireless processor in which a high functional integrated circuit including the element forming region is formed and the semiconductor device transmit and receive data through the antenna.
    Type: Grant
    Filed: July 7, 2005
    Date of Patent: May 6, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Kiyoshi Kato, Jun Koyama, Yutaka Shionoiri
  • Patent number: 8698239
    Abstract: A semiconductor device includes an active region in a substrate, first to third gate structures crossing the active region and sequentially arranged parallel to each other, a first doped region in the active region between the first and second gate structures and having a first horizontal width and a first depth, and a second doped region in the active region between the second and third gate structures and having a second horizontal width and a second depth. The second horizontal width is larger than the first horizontal width and the second depth is shallower than the first depth. A distance between the first and second gate structures adjacent to each other is smaller than that between the second and third gate structures adjacent to each other. Related fabrication methods are also described.
    Type: Grant
    Filed: January 17, 2012
    Date of Patent: April 15, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ji-Do Ryu, Hee-Seog Jeon, Hyun-Khe Yoo, Yong-Suk Choi
  • Patent number: 8664108
    Abstract: A stacked multilayer structure according to an embodiment of the present invention comprises: a stacked layer part including a plurality of conducting layers and a plurality of insulating layers, said plurality of insulating layers being stacked alternately with each layer of said plurality of conducting layers, one of said plurality of insulating layers being a topmost layer among said plurality of conducting layers and said plurality of insulating layers; and a plurality of contacts, each contact of said plurality of contacts being formed from said topmost layer and each contact of said plurality of contacts being in contact with a respective conducting layer of said plurality of conducting layers, a side surface of each of said plurality of contacts being insulated from said plurality of conducting layers via an insulating film.
    Type: Grant
    Filed: November 17, 2010
    Date of Patent: March 4, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Makoto Mizukami, Takeshi Kamigaichi
  • Patent number: 8653578
    Abstract: A semiconductor device having a string gate structure and a method of manufacturing the same suppress leakage current. The semiconductor device includes a selection gate and a memory gate. The channel region of the selection gate has a higher impurity concentration than that of the memory gate. Impurities may be implanted at different angles to form the channel regions having different impurity concentrations.
    Type: Grant
    Filed: September 9, 2009
    Date of Patent: February 18, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Changhyun Lee, Jungal Choi
  • Patent number: 8598644
    Abstract: A nonvolatile semiconductor storage device including a first transistor comprising a first gate electrode including a charge storage layer, an interelectrode insulating film, and a control electrode layer; a second transistor comprising a second gate electrode including a lower electrode, an upper electrode, and an upper silicide portion above the upper electrode; and a third transistor comprising a third gate electrode including a lower electrode, an upper electrode, and an upper silicide portion above the upper electrode; wherein the lower electrodes of the second and the third gate electrodes have a first side and a second side taken along a length direction of the second and the third gate electrodes, the lower electrodes of the second and the third gate electrodes including a lower silicide portion in which at least the first side of the lower electrodes are partially silicided.
    Type: Grant
    Filed: August 20, 2012
    Date of Patent: December 3, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Wataru Sakamoto
  • Patent number: 8587036
    Abstract: A non-volatile memory is formed on a substrate. The non-volatile memory includes an isolation structure, a floating gate, and a gate dielectric layer. The isolation structure is disposed in the substrate to define an active area. The floating gate is disposed on the substrate and crosses over the active area. The gate dielectric layer is disposed between the floating gate and the substrate. The floating gate includes a first region and a second region. An energy band of the second region is lower than an energy band of the first region, so that charges stored in the floating gate are away from an overlap region of the floating gate and the gate dielectric layer.
    Type: Grant
    Filed: December 12, 2008
    Date of Patent: November 19, 2013
    Assignee: eMemory Technology Inc.
    Inventors: Shih-Chen Wang, Wen-Hao Ching
  • Patent number: 8574992
    Abstract: A vertical interconnect architecture for a three-dimensional (3D) memory device suitable for low cost, high yield manufacturing is described. Conductive lines (e.g. word lines) for the 3D memory array, and contact pads for vertical connectors used for couple the array to decoding circuitry and the like, are formed as parts of the same patterned level of material. The same material layer can be used to form the contact pads and the conductive access lines by an etch process using a single mask. By forming the contact pads concurrently with the conductive lines, the patterned material of the contact pads can protect underlying circuit elements which could otherwise be damaged during patterning of the conductive lines.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: November 5, 2013
    Assignee: Macronix International Co., Ltd.
    Inventors: Shih-Hung Chen, Yen-Hao Shih, Hang-Ting Lue
  • Patent number: 8569133
    Abstract: A nonvolatile semiconductor memory device includes a plurality of memory strings, each of which has a plurality of electrically rewritable memory cells connected in series; and select transistors, one of which is connected to each of ends of each of the memory strings. Each of the memory strings is provided with a first semiconductor layer having a pair of columnar portions extending in a perpendicular direction with respect to a substrate, and a joining portion formed so as to join lower ends of the pair of columnar portions; a charge storage layer formed so as to surround a side surface of the columnar portions; and a first conductive layer formed so as to surround the side surface of the columnar portions and the charge storage layer, and configured to function as a control electrode of the memory cells.
    Type: Grant
    Filed: February 6, 2012
    Date of Patent: October 29, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masaru Kito, Yoshiaki Fukuzumi, Ryota Katsumata, Masaru Kidoh, Hiroyasu Tanaka, Megumi Ishiduki, Yosuke Komori, Hideaki Aochi
  • Patent number: 8551809
    Abstract: A nonvolatile memory device and methods of manufacturing the same has one electrode with a higher work function and a second electrode with a lower work function. The nonvolatile memory device further comprises one or more resistive random access memory (RRAM) cells. The RRAM cells comprise a semiconductor layer with a bandgap of at least four electron volts and a barrier layer between the semiconductor layer and one of the electrodes.
    Type: Grant
    Filed: February 24, 2009
    Date of Patent: October 8, 2013
    Assignee: Intermolecular, Inc.
    Inventors: Pragati Kumar, Yun Wang, Prashant Phatak, Tony P. Chiang
  • Patent number: 8536007
    Abstract: A first conductive layer and an underlying charge storage layer are patterned to form a control gate in an NVM region. A first dielectric layer is formed over the control gate. A sacrificial layer is formed over the first dielectric layer and planarized. A patterned masking layer is formed over the sacrificial layer which includes a first portion which defines a select gate location laterally adjacent the control gate in the NVM region and a second portion which defines a logic gate in a logic region. Exposed portions of the sacrificial layer are removed such that a first portion remains at the select gate location. A second dielectric layer is formed over the first portion and planarized to expose the first portion. The first portion is removed to result in an opening at the select gate location. A gate dielectric layer and a select gate are formed in the opening.
    Type: Grant
    Filed: February 22, 2012
    Date of Patent: September 17, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Mark D. Hall, Mehul D. Shroff
  • Patent number: 8524557
    Abstract: A control gate overlying a charge storage layer is formed. A thermally-grown oxygen-containing layer is formed over the control gate. A polysilicon layer is formed over the oxygen-containing layer and planarized. A first masking layer is formed defining a select gate location laterally adjacent the control gate and a second masking layer is formed defining a logic gate location. Exposed portions of the polysilicon layer are removed such that a select gate remains at the select gate location and a polysilicon portion remains at the logic gate location. A dielectric layer is formed around the select and control gates and polysilicon portion. The polysilicon portion is removed to result in an opening in the dielectric. A high-k gate dielectric and logic gate are formed in the opening.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: September 3, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Mark D. Hall, Mehul D. Shroff, Frank K. Baker, Jr.
  • Patent number: 8519485
    Abstract: A method of forming a memory device. The method provides a semiconductor substrate having a surface region. A first dielectric layer is formed overlying the surface region of the semiconductor substrate. A bottom wiring structure is formed overlying the first dielectric layer and a second dielectric material is formed overlying the top wiring structure. A bottom metal barrier material is formed to provide a metal-to-metal contact with the bottom wiring structure. The method forms a pillar structure by patterning and etching a material stack including the bottom metal barrier material, a contact material, a switching material, a conductive material, and a top barrier material. The pillar structure maintains a metal-to-metal contact with the bottom wiring structure regardless of the alignment of the pillar structure with the bottom wiring structure during etching. A top wiring structure is formed overlying the pillar structure at an angle to the bottom wiring structure.
    Type: Grant
    Filed: May 7, 2012
    Date of Patent: August 27, 2013
    Assignee: Crossbar, Inc.
    Inventor: Scott Brad Herner
  • Patent number: 8502322
    Abstract: According to the nonvolatile memory device in one embodiment, contact plugs connect between second wires and third wires in a memory layer and a first wire connected to a control element. Drawn wire portions connect the second wires and the third wires with the contact plug. The drawn wire portion connected to the second wires and the third wires of the memory layer is formed of a wire with a critical dimension same as the second wires and the third wires and is in contact with the contact plug on an upper surface and both side surfaces of the drawn wire portion.
    Type: Grant
    Filed: March 10, 2011
    Date of Patent: August 6, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hiroyuki Nitta
  • Patent number: 8497544
    Abstract: A memory module includes multiple memory devices mounted to a substrate and one or more discrete heating elements disposed in thermal contact with the memory devices. Each of the memory devices includes charge-storing memory cells subject to operation-induced defects that degrade ability of the memory cells to store data. The discrete heating elements, or single discrete heating element, heats the memory devices to a temperature that anneals the defects.
    Type: Grant
    Filed: June 1, 2012
    Date of Patent: July 30, 2013
    Assignee: Rambus Inc.
    Inventors: Gary B. Bronner, Ming Li, Donald R. Mullen, Frederick Ware, Kevin S. Donnelly
  • Patent number: 8470645
    Abstract: A method for forming a memory cell including a selection transistor and an antifuse transistor, in a technological process adapted to the manufacturing of a first and of a second types of MOS transistors of different gate thicknesses, this method including the steps of: forming the selection transistor according to the steps of manufacturing of the N-channel transistor of the second type; and forming the antifuse transistor essentially according the steps of manufacturing of the N-channel transistor of the first type, by modifying the following step: instead of performing a P-type implantation in the channel region at the same time as in the N-channel transistors of the first type, performing an N-type implantation in the channel region at the same time as in the P-channel transistors of the first type.
    Type: Grant
    Filed: March 2, 2011
    Date of Patent: June 25, 2013
    Assignee: STMicroelectronics SA
    Inventors: Philippe Candelier, Elise Le Roux
  • Patent number: 8450119
    Abstract: An MTJ MRAM cell is formed by using a reactive ion etch (RIE) to pattern an MTJ stack on which there has been formed a bilayer Ta/TaN hard mask. The hard mask is formed by patterning a masking layer that has been formed by depositing a layer of TaN over a layer of Ta on the MTJ stack. After the stack is patterned, the TaN layer serves at least two advantageous purposes: 1) it protects the Ta layer from oxidation during the etching of the stack and 2) it serves as a surface having excellent adhesion properties for a subsequently deposited dielectric layer.
    Type: Grant
    Filed: March 17, 2006
    Date of Patent: May 28, 2013
    Assignee: MagIC Technologies, Inc.
    Inventors: Chyu-Jiuh Torng, Wei Cao, Terry Ko
  • Patent number: 8445350
    Abstract: According to an embodiment of a semiconductor device and a method of manufacturing the same, buried gates are formed in a semiconductor substrate including a cell region and a peripheral region, with the cell region and the peripheral region formed to have a step therebetween. Next, a spacer is formed in a region between the cell region and the peripheral region to block an oxidation path between a gate oxide layer and another insulating layer. Embodiments may reduce damage to active regions and prevent IDD failure because a gate pattern is formed on a guard region provided at a periphery of the cell region.
    Type: Grant
    Filed: January 10, 2012
    Date of Patent: May 21, 2013
    Assignee: Hynix Semiconductor, Inc.
    Inventor: Dong Hee Han
  • Patent number: 8441060
    Abstract: A nonvolatile memory element includes a first electrode (103) formed on a substrate (101), a resistance variable layer (108) and a second electrode (107), wherein the resistance variable layer has a multi-layer structure including at least three layers which are a first transition metal oxide layer (104), a second transition metal oxide layer (106) which is higher in oxygen concentration than the first transition metal oxide layer (104), and a transition metal oxynitride layer (105). The second transition metal oxide layer (106) is in contact with either one of the first electrode (103) and the second electrode (107). The transition metal oxynitride layer (105) is provided between the first transition metal oxide layer (104) and the second transition metal oxide layer (106).
    Type: Grant
    Filed: September 29, 2009
    Date of Patent: May 14, 2013
    Assignee: Panasonic Corporation
    Inventors: Takeki Ninomiya, Koji Arita, Takumi Mikawa, Satoru Fujii
  • Patent number: 8426301
    Abstract: Nonvolatile memory devices are provided and methods of manufacturing such devices. In the method, conductive layers and insulating layers are alternatingly stacked on a substrate. A first sub-active bar is formed which penetrates a first subset of the conductive layers and a first subset of the insulating layers. The first sub-active bar is electrically connected with the substrate. A second sub-active bar is formed which penetrates a second subset of the conductive layers and a second subset of the insulating layers. The second sub-active bar is electrically connected to the first sub-active bar. A width of a bottom portion of the second sub-active bar is less than a width of a top portion of the second sub-active bar.
    Type: Grant
    Filed: August 3, 2011
    Date of Patent: April 23, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-Yong Oh, Woonkyung Lee, Jin-Sung Lee, Sunil Shim, Hansoo Kim, Wonseok Cho, Jaehoon Jang, Jin-Soo Lim
  • Patent number: 8415218
    Abstract: A method of growing an epitaxial silicon layer is provided. The method comprising providing a substrate including an oxygen-terminated silicon surface and forming a first hydrogen-terminated silicon surface on the oxygen-terminated silicon surface. Additionally, the method includes forming a second hydrogen-terminated silicon surface on the first hydrogen-terminated silicon surface through atomic-layer deposition (ALD) epitaxy from SiH4 thermal cracking radical assisted by Ar flow and flash lamp annealing continuously. The second hydrogen-terminated silicon surface is capable of being added one or more layer of silicon through ALD epitaxy from SiH4 thermal cracking radical assisted by Ar flow and flash lamp annealing continuously. In one embodiment, the method is applied for making devices with thin-film transistor (TFT) floating gate memory cell structures which is capable for three-dimensional integration.
    Type: Grant
    Filed: October 27, 2008
    Date of Patent: April 9, 2013
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Fumitake Mieno
  • Patent number: 8395199
    Abstract: Systems and methods are disclosed to form a resistive random access memory (RRAM) by forming a first metal electrode layer; depositing an insulator above the metal electrode layer and etching the insulator to expose one or more metal portions; depositing a Pr1-XCaXMnO3 (PCMO) layer above the insulator and the metal portions, wherein X is between approximately 0.3 and approximately 0.5, to form one or more self-aligned RRAM cells above the first metal electrode; and depositing a second metal electrode layer above the PCMO layer.
    Type: Grant
    Filed: March 25, 2006
    Date of Patent: March 12, 2013
    Assignee: 4D-S Pty Ltd.
    Inventor: Makoto Nagashima
  • Patent number: 8338877
    Abstract: Nonvolatile memory devices and methods of forming the same are provided, the nonvolatile memory devices may include first regions and second regions which extend in a first direction and are alternately disposed in a semiconductor substrate along a second direction crossing the first direction. Buried doped lines are formed at the first regions respectively and extend in the first direction. The buried doped lines may be doped with a dopant of a first conductivity type. Bulk regions doped with a dopant of a second conductivity type and device isolation patterns are disposed along the second direction. The bulk regions and the device isolation patterns may be formed in the second regions. Word lines crossing the buried doped lines and the bulk regions are formed parallel to one another. Contact structures are connected to the buried doped lines and disposed between the device isolation patterns.
    Type: Grant
    Filed: October 13, 2009
    Date of Patent: December 25, 2012
    Assignee: Samsung Electronics Co. Ltd.
    Inventors: Yongsik Jeong, Jeonguk Han, Weonho Park, Byungsup Shim
  • Patent number: 8283717
    Abstract: Device isolation/insulation films each have a first height within a first area and a second height higher than the first height within a second area. At least the device isolation/insulation films adjacent to a contact diffusion region exist in the second area, and the device isolation/insulation films adjacent to memory transistors exist in the first area. The device isolation/insulation films are implanted with an impurity of a first conductivity type, and device formation regions each have a diffusion region of the first conductivity type, the diffusion region being formed by diffusion of the impurity of the first conductivity type from the device isolation/insulation films.
    Type: Grant
    Filed: September 20, 2010
    Date of Patent: October 9, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Junya Matsunami, Hiroyuki Kutsukake
  • Patent number: 8278695
    Abstract: A nonvolatile semiconductor memory device includes a substrate, and a plurality of memory strings, the memory string including a first selection transistor including a first pillar shaped semiconductor formed perpendicular to the substrate, a first gate insulating film formed around the first pillar shaped semiconductor, and a first gate electrode formed around the first gate insulating film, and a plurality of memory cells including a second pillar shaped semiconductor formed on the first pillar shaped semiconductor, the diameter of the first pillar shaped semiconductor being larger than the diameter of the second pillar shaped semiconductor at the part where the second pillar shaped semiconductor is connected to the first pillar shaped semiconductor, a first insulating film formed around the second pillar shaped semiconductor, a charge storage layer formed around the first insulating film, a second insulating film formed around the charge storage layer, and first to nth electrodes formed around the second i
    Type: Grant
    Filed: September 14, 2007
    Date of Patent: October 2, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masaru Kidoh, Ryota Katsumata, Hiroyasu Tanaka, Hideaki Aochi, Masaru Kito
  • Publication number: 20120223299
    Abstract: Embodiments include memory cells having an oxide material in contact with a metal material. In one embodiment, a memory cell includes titanium nitride, titanium oxynitride in contact with the titanium nitride and copper in contact with the titanium oxynitride. A plurality of such memory cells and respective access devices can be included in a memory array. The memory cell and access device are electrically connected between an access line and a data/sense line. An array can include a plurality of memory cells vertically stacked with respective access devices. Embodiments also include methods of forming memory cells and arrays and stacking memory arrays over one another.
    Type: Application
    Filed: March 4, 2011
    Publication date: September 6, 2012
    Inventor: Jun Liu
  • Patent number: 8258029
    Abstract: A non-volatile memory cell capable of storing two bits of information having a non-conducting charge trapping dielectric, such as silicon nitride, layered in association with at least one electrical dielectric layer, such as an oxide, with a P-type substrate and an N-type channel implanted in the well region of the substrate between two source/drain regions is disclosed. The N-type channel achieves an inversion layer without the application of bias voltage to the gate of the memory cell. A method that implants the N-type channel in the P-type substrate of the cell wherein the N-type channel lowers the un-programmed or programmed voltage threshold of the memory cell to a value lower than would exist without the N-type channel is disclosed. The N-type channel reduces the second bit effect such that the window of operation between the programmed and un-programmed voltage thresholds of the bits is widened.
    Type: Grant
    Filed: April 10, 2007
    Date of Patent: September 4, 2012
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Chao-I Wu, Tzu-Hsuan Hsu
  • Patent number: 8227873
    Abstract: According to one disclosed embodiment, an integrated one-time programmable (OTP) semiconductor device pair includes a split-thickness dielectric under an electrode and over an isolation region formed in a doped semiconductor substrate, where a reduced-thickness center portion of the dielectric forms, in conjunction with the isolation region, programming regions of the OTP semiconductor device pair, and where the thicker, outer portions of the dielectric form dielectrics for transistor structures. In one embodiment, the split-thickness dielectric comprises a gate dielectric. In one embodiment, multiple OTP semiconductor device pairs are formed in an array that minimizes the number of connections required to program and sense states of specific OTP cells.
    Type: Grant
    Filed: April 9, 2010
    Date of Patent: July 24, 2012
    Assignee: Broadcom Corporation
    Inventor: Douglas Smith
  • Patent number: 8222075
    Abstract: A plurality of bit lines s arranged crossing a plurality of first word lines. A first diode is arranged at each cross point of the first word lines and the bit lines. A cathode of the first diode is connected to one of the first word lines. A first variable resistance film configuring the first diode is provided between the anodes of the first diodes and the bit lines, and configures a first memory cell together with each of the first diodes, and further, is used in common to the first diodes.
    Type: Grant
    Filed: March 17, 2009
    Date of Patent: July 17, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Eiji Ito
  • Patent number: 8211755
    Abstract: A method for preventing arcing during deep via plasma etching is provided. The method comprises forming a first patterned set of parallel conductive lines over a substrate and forming a plurality of semiconductor pillars on the first patterned set of parallel conductive lines and extending therefrom, wherein a pillar comprises a first barrier layer, an antifuse layer, a diode, and a second barrier layer, wherein an electric current flows through the diode upon a breakdown of the antifuse layer. The method further comprises depositing a dielectric between the plurality of semiconductor pillars, and plasma etching a deep via recess through the dielectric and through the underlying layer after the steps of forming a plurality of semiconductor pillars and depositing a dielectric. An embodiment of the invention comprises a memory array device.
    Type: Grant
    Filed: May 5, 2010
    Date of Patent: July 3, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsiu-Lan Kuo, Kern-Huat Ang
  • Publication number: 20120163063
    Abstract: A complementary read-only memory (ROM) cell includes a transistor; and a bit line and a complementary bit line adjacent to the transistor; wherein a drain terminal of the transistor is connected to one of the bit line and the complementary bit line based on data programmed in the ROM cell.
    Type: Application
    Filed: June 24, 2011
    Publication date: June 28, 2012
    Applicant: STMicroelectronics Pvt Ltd.
    Inventor: Jitendra DASANI
  • Patent number: 8193573
    Abstract: A method of repairing a nonvolatile semiconductor memory device to eliminate defects includes monitoring a memory endurance indicator for a nonvolatile semiconductor memory device contained in a semiconductor package. It is determined whether that the memory endurance indicator exceeds a predefined limit. Finally, in response to determining that the memory endurance indicator exceeds the predefined limit, the device is annealed.
    Type: Grant
    Filed: September 4, 2008
    Date of Patent: June 5, 2012
    Assignee: Rambus Inc.
    Inventors: Gary B. Bronner, Ming Li, Donald R. Mullen, Frederick Ware, Kevin S. Donnelly
  • Patent number: 8187932
    Abstract: A non-volatile memory device contains a three dimensional stack of horizontal diodes located in a trench in an insulating material, a plurality of storage elements, a plurality of word lines extending substantially vertically, and a plurality of bit lines. Each of the plurality of bit lines has a first portion that extends up along at least one side of the trench and a second portion that extends substantially horizontally through the three dimensional stack of the horizontal diodes. Each of the horizontal diodes is a steering element of a respective non-volatile memory cell of the non-volatile memory device, and each of the plurality of storage elements is located adjacent to a respective steering element.
    Type: Grant
    Filed: October 15, 2010
    Date of Patent: May 29, 2012
    Assignee: SanDisk 3D LLC
    Inventors: Natalie Nguyen, Paul Wai Kie Poon, Steven J. Radigan, Michael Konevecki, Raghuveer S. Makala
  • Patent number: 8153485
    Abstract: A method for fabricating a memory is described. Word lines are provided in a first direction. Bit lines are provided in a second direction. A top electrode is formed connecting to a corresponding word line. A bottom electrode is formed connecting to a corresponding bit line. A resistive layer is formed on the bottom electrode. At least two separate L-shaped liners are formed, wherein each L-shaped liner has variable resistive materials on both ends of the L-shaped liner and each L-shaped liner is coupled between the top electrode and the resistive layer.
    Type: Grant
    Filed: June 20, 2011
    Date of Patent: April 10, 2012
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Erh-Kun Lai, Chia-Hua Ho, Kuang-Yeu Hsieh
  • Patent number: 8148769
    Abstract: A nonvolatile semiconductor memory device includes a plurality of memory strings, each of which has a plurality of electrically rewritable memory cells connected in series; and select transistors, one of which is connected to each of ends of each of the memory strings. Each of the memory strings is provided with a first semiconductor layer having a pair of columnar portions extending in a perpendicular direction with respect to a substrate, and a joining portion formed so as to join lower ends of the pair of columnar portions; a charge storage layer formed so as to surround a side surface of the columnar portions; and a first conductive layer formed so as to surround the side surface of the columnar portions and the charge storage layer, and configured to function as a control electrode of the memory cells.
    Type: Grant
    Filed: August 3, 2009
    Date of Patent: April 3, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masaru Kito, Yoshiaki Fukuzumi, Ryota Katsumata, Masaru Kidoh, Hiroyasu Tanaka, Megumi Ishiduki, Yosuke Komori, Hideaki Aochi
  • Patent number: 8143150
    Abstract: A method of fabricating a semiconductor device includes forming a well impurity region, a lower impurity region and an upper impurity region in a semiconductor substrate. The lower impurity region has a different conductivity type than a conductivity type of the well impurity region, the upper impurity region has a different conductivity type than the conductivity type of the lower impurity region, and the upper impurity region has a same conductivity type as the conductivity type of the well impurity region and has a higher impurity concentration than an impurity concentration of the well impurity region. The semiconductor substrate is etched to form lower semiconductor patterns, upper semiconductor patterns upwardly projecting from predetermined regions of the lower semiconductor patterns. An isolation layer filling the first and second spaces between the lower semiconductor patterns and between the upper semiconductor patterns, respectively is formed.
    Type: Grant
    Filed: January 17, 2011
    Date of Patent: March 27, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Hoon Jeong