Magnetic Nonvolatile Memory Structures, E.g., Mram (epo) Patents (Class 257/E21.665)
  • Patent number: 10573366
    Abstract: Spin torque transfer magnetic random access memory devices configured to be programmed unidirectionally and methods of programming such devices. The devices include memory cells having two pinned layers and a free layer therebetween. By utilizing two pinned layers, the spin torque effect on the free layer from each of the two pinned layers, respectively, allows the memory cells to be programmed with unidirectional currents.
    Type: Grant
    Filed: October 18, 2018
    Date of Patent: February 25, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Jun Liu, Gurtej Sandhu
  • Patent number: 10553786
    Abstract: This invention relates to structures comprising magnetic materials and conjugated molecules. The invention relates to magneto-resistive devices based on such structures. Structures and devices of the invention can be used as magnetic switches, magnetic sensors and in devices such in/as memory devices.
    Type: Grant
    Filed: August 27, 2015
    Date of Patent: February 4, 2020
    Assignee: YEDA RESEARCH AND DEVELOPMENT CO. LTD.
    Inventors: Oren Tal, David Rakhmilevich
  • Patent number: 10403813
    Abstract: Embodiments relate to magnetoresistive (xMR) sensors. In an embodiment, an xMR stack structure is configured to form two different xMR elements that can be coupled to form a locally differential Wheatstone bridge. The result is a highly sensitive magnetic sensor with small dimensions and robustness against thermal drift and sensor/encoder pitch mismatch that can be produced using standard processing equipment. Embodiments also relate to methods of forming and patterning the stack structure and sensors that provide information regarding direction in addition to speed.
    Type: Grant
    Filed: April 14, 2017
    Date of Patent: September 3, 2019
    Assignee: Infineon Technologies AG
    Inventor: Wolfgang Raberg
  • Patent number: 10395709
    Abstract: According to one embodiment, a magnetic memory device includes a conductive layer, a first magnetic layer, a first nonmagnetic layer, a second magnetic layer, a first conductive region, a first insulating region, and a controller. The conductive layer includes a first element. The conductive layer includes a first portion, a second portion, a third portion between the first portion and the second portion, and a fourth portion between the second portion and the third portion. The first conductive region includes a second element different from the first element. The first conductive region is provided between the second magnetic layer and the third portion. The first insulating region includes a first insulating substance. The first insulating substance is an insulating compound of the second element. The controller is electrically connected to the first portion and the second portion. The controller implements a first operation and a second operation.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: August 27, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mariko Shimizu, Yuichi Ohsawa, Hideyuki Sugiyama, Satoshi Shirotori, Altansargai Buyandalai, Yushi Kato
  • Patent number: 10381466
    Abstract: A spintronic device can include a bottom contact layer, a bottom magnetic layer disposed on the bottom contact layer, a nanoparticle layer disposed on the bottom magnetic layer, a top magnetic layer disposed on the nanoparticle layer, and a top contact layer disposed on the top magnetic layer. The spintronic device can include a bottom insulation layer disposed between the bottom magnetic layer and the nanoparticle layer, and a top insulation layer disposed between the nanoparticle layer and the top magnetic layer.
    Type: Grant
    Filed: October 12, 2018
    Date of Patent: August 13, 2019
    Assignee: The Florida International University Board of Trustees
    Inventors: Sakhrat Khizroev, Rakesh Guduru
  • Patent number: 10381078
    Abstract: A semiconductor memory includes a first memory cell array in a first region of a substrate and a second memory cell array in a second region of the substrate. The first memory cell array includes cell strings, and each cell string includes non-volatile memory cells stacked in a direction perpendicular to the substrate. The second memory cell array includes volatile memory cells, and each volatile memory cell includes a select transistor and a capacitor. The capacitor includes at least one contact electrically connected with the select transistor and having a second height corresponding to a first height of each cell string, and at least one second contact supplied with a ground voltage, having a third height corresponding to the first height of each cell string, adjacent to the at least one first contact, and electrically disconnected with the at least one first contact.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: August 13, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chanho Kim, Dong-Kil Yun, Pansuk Kwak, Hongsoo Jeon
  • Patent number: 10326073
    Abstract: The various implementations described herein include methods, devices, and systems for operating magnetic memory devices. In one aspect, a magnetic memory device includes: (1) a core; (2) a plurality of layers that surround the core in succession; (3) a first input terminal coupled to the core and configured to receive a first current, where: (a) the first current flows radially from the core through the plurality of layers; and (b) the radial flow of the first current imparts a torque on, at least, a magnetization of an inner layer of the plurality of layers; and (4) a second input terminal coupled to the core and configured to receive a second current, where: (i) the second current imparts a Spin Hall Effect (SHE) around a perimeter of the core; and (ii) the SHE contributes to the torque imparted on the magnetization of the inner layer by the first current.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: June 18, 2019
    Assignee: SPIN MEMORY, INC.
    Inventors: Michail Tzoufras, Marcin Gajek, Kadriye Deniz Bozdag, Eric Michael Ryan
  • Patent number: 10319783
    Abstract: A method is presented for forming a semiconductor structure. The method includes depositing a barrier layer, such as a tantalum nitride (TaN) layer, over a dielectric incorporating magnetic random access memory (MRAM) regions, forming magnetic tunnel junction (MTJ) stacks over portions of the TaN layer, patterning and encapsulating the MTJ stacks, forming spacers adjacent the MTJ stacks, and laterally etching sections of the TaN layer, after spacer formation, to form an electrode under the MTJ stacks. The electrode protects the MRAM regions. The electrode can be recessed from the spacers.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: June 11, 2019
    Assignee: International Business Machines Corporation
    Inventors: Benjamin D. Briggs, Michael Rizzolo, Theodorus E. Standaert
  • Patent number: 10312435
    Abstract: A method for manufacturing a magnetic random access memory array at a density greater than would be possible using photolithography. A hard mask material is deposited over a magnetic memory element material, and a chemical template layer such as brush or mat material is deposited over the hard mask. A mask structure is formed over the soluble polymer. The mask structure is configured with openings having a center to center spacing that is an integer multiple of a block copolymer material. The openings in the mask structure can be shrunk by depositing a spacer material. The chemical template layer is chemically patterned, such as by a quick plasma exposure and the mask is removed. A block copolymer material is then deposited over the chemical template and annealed to form block copolymer cylinders that are located over the patterned portions of the chemical template and between the patterned portions.
    Type: Grant
    Filed: January 9, 2018
    Date of Patent: June 4, 2019
    Assignee: SPIN MEMORY, INC.
    Inventors: Elizabeth A. Dobisz, Prachi Shrivastava
  • Patent number: 10276780
    Abstract: Semiconductor devices and semiconductor device control methods are described. A semiconductor device comprises a first electrode; a cell arranged on the first electrode and including a magnetic tunnel junction (MTJ) having a free magnetic layer and a pinned magnetic layer with a dielectric layer in between them; and a heating element to form a thermal gradient in the first electrode.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: April 30, 2019
    Assignee: Korea Advanced Institute of Science and Technology
    Inventors: Byong Guk Park, Dong Jun Kim, Chul Yeon Jeon
  • Patent number: 10217501
    Abstract: According to some aspects, a layered structure comprises a memory layer exhibiting magnetization perpendicular to a face of the memory layer, the memory layer configured to change a direction of the magnetization in response to application of a current thereto, a magnetic layer exhibiting magnetization parallel or antiparallel to the direction of the magnetization of the memory layer and comprising a plurality of ferromagnetic layers, one or more non-magnetic layers, and an antiferromagnetic material, wherein a first non-magnetic layer of the one or more non-magnetic layers is situated between a first ferromagnetic layer of the plurality of ferromagnetic layers and a second ferromagnetic layer of the plurality of ferromagnetic layers, and wherein the antiferromagnetic material contacts at least one of the first non-magnetic layer and the first ferromagnetic layer, and an intermediate layer formed from a non-magnetic material located between the memory layer and the magnetic layer.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: February 26, 2019
    Assignee: Sony Corporation
    Inventors: Kazutaka Yamane, Masanori Hosomi, Hiroyuki Ohmori, Kazuhiro Bessho, Yutaka Higo, Tetsuya Asayama, Hiroyuki Uchida
  • Patent number: 10164176
    Abstract: A method of manufacturing one or more interconnects to a magnetoresistive structure, the method comprising depositing a first conductive material (i) in a via which is formed through a first surface of a first dielectric layer and (ii) directly on the first surface of the first dielectric layer. The method further includes etching the first conductive material wherein, after etching the first conductive material, a portion of the first conductive material remains (i) in the via and (ii) directly on the first surface of the first dielectric layer. The method also includes partially filling the via by depositing a second conductive material (i) in the via and (ii) directly on the first conductive material remaining in the via, depositing a first electrode material (i) in the via and (ii) directly on the second conductive material which is in the via, and forming a magnetoresistive structure over the first electrode material.
    Type: Grant
    Filed: January 6, 2017
    Date of Patent: December 25, 2018
    Assignee: Everspin Technologies, Inc.
    Inventors: Kerry Joseph Nagel, Kenneth Smith, Moazzem Hossain, Sanjeev Aggarwal
  • Patent number: 10164168
    Abstract: Methods of forming memory cells, magnetic memory cell structures, and arrays of magnetic memory cell structures are disclosed. Embodiments of the methods include patterning a precursor structure to form a stepped structure including at least an upper discrete feature section and a lower feature section with a broader width, length, or both than the upper discrete feature section. The method uses patterning acts directed along a first axis, e.g., an x-axis, and then along a second axis, e.g., a y-axis, that is perpendicular to or about perpendicular to the first axis. The patterning acts may therefore allow for more uniformity between a plurality of formed, neighboring cell core structures, even at dimensions below about thirty nanometers. Magnetic memory structures and memory cell arrays are also disclosed.
    Type: Grant
    Filed: June 20, 2016
    Date of Patent: December 25, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Gurtej S. Sandhu, Witold Kula, Wayne I. Kinney
  • Patent number: 10127933
    Abstract: A system according to one embodiment includes a magnetic head having a plurality of sensors arranged to simultaneously read at least three immediately adjacent data tracks on a magnetic medium, wherein none of the sensors share more than one lead with any other of the sensors. Such embodiment may be implemented in a magnetic data storage system such as a disk drive system, which may include a magnetic head, a drive mechanism for passing a magnetic medium (e.g., hard disk) over the magnetic head, and a controller electrically coupled to the magnetic head.
    Type: Grant
    Filed: August 11, 2017
    Date of Patent: November 13, 2018
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Sharat Batra, Jonathan D. Coker, Travis R. Oenning
  • Patent number: 10109332
    Abstract: According to one embodiment, a magnetic memory device includes a conductive layer, a first magnetic layer, a first nonmagnetic layer, a second magnetic layer, a first conductive region, a first insulating region, and a controller. The conductive layer includes a first element. The conductive layer includes a first portion, a second portion, a third portion between the first portion and the second portion, and a fourth portion between the second portion and the third portion. The first conductive region includes a second element different from the first element. The first conductive region is provided between the second magnetic layer and the third portion. The first insulating region includes a first insulating substance. The first insulating substance is an insulating compound of the second element. The controller is electrically connected to the first portion and the second portion. The controller implements a first operation and a second operation.
    Type: Grant
    Filed: September 14, 2017
    Date of Patent: October 23, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mariko Shimizu, Yuichi Ohsawa, Hideyuki Sugiyama, Satoshi Shirotori, Altansargai Buyandalai, Yushi Kato
  • Patent number: 10109331
    Abstract: According to one embodiment, a magnetic storage device includes memory cells, wherein each of the memory cell includes: a wiring including a first ferromagnetic layer and a first nonmagnetic layer disposed on the first ferromagnetic layer; a magnetoresistive effect element including a second ferromagnetic layer disposed on the first nonmagnetic layer, a third ferromagnetic layer, and a second nonmagnetic layer disposed between the second and the third ferromagnetic layer; a first transistor having a first terminal connected to the first ferromagnetic layer, and a second terminal connected to a source line; and a second transistor having a first terminal connected to the third ferromagnetic layer, and a second terminal connected to a bit line.
    Type: Grant
    Filed: September 9, 2016
    Date of Patent: October 23, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Motoyuki Sato
  • Patent number: 10096653
    Abstract: Provided is a monolithic integration of resistive memory with complementary metal oxide semiconductor using integrated circuit foundry processes. A memory device is provided that includes a substrate comprising one or more complementary metal-oxide semiconductor devices, a first insulator layer formed on the substrate; and a monolithic stack. The monolithic stack includes multiple layers fabricated as part of a monolithic process over the first insulator layer. The multiple layers include a first metal layer, a second insulator layer, and a second metal layer. A resistive memory device structure is formed within the second insulator layer and within a thermal budget of the one or more complementary metal-oxide semiconductor devices. The resistive memory device structure is implemented as a pillar device or as a via device. Further, the first metal layer is coupled to the second metal layer.
    Type: Grant
    Filed: December 31, 2014
    Date of Patent: October 9, 2018
    Assignee: CROSSBAR, INC.
    Inventors: Sundar Narayanan, Steve Maxwell, Natividad Vasquez, Jr., Harry Yue Gee
  • Patent number: 10083863
    Abstract: A method of forming a semiconductor device includes forming a source/drain region on a substrate and forming a first interlayer dielectric (ILD) layer over the source/drain region. The method further includes forming a first conductive region within the first ILD layer, selectively removing a portion of the first conductive region to form a concave top surface of the first conductive region. The method also includes forming a second ILD layer over the first ILD layer and forming a second conductive region within the second ILD layer and on the concave top surface. The concave top surface provides a large contact area, and hence reduced contact resistance between the first and second conductive regions.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: September 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yun-Yu Hsieh, Jeng Chang Her, Cha-Hsin Chao, Yi-Wei Chiu, Li-Te Hsu, Ying Ting Hsia
  • Patent number: 10062449
    Abstract: A magnetic domain wall (MDW) motion device. The MDW motion device may include a ferromagnetic layer with perpendicular magnetic anisotropy and non-magnetic metal layers extending parallel to and in contact with the ferromagnetic layer. The ferromagnetic layer may include first ferromagnetic regions, which are arranged in an extension direction of the ferromagnetic layer, and second ferromagnetic regions, which are provided between an adjacent pair of the first ferromagnetic regions. The first and second ferromagnetic regions may have spin torque coefficients of opposite signs, and an MDW positioned near an interface between the first and second ferromagnetic regions may be moved by an in-plane current flowing through the non-magnetic metal layer.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: August 28, 2018
    Assignee: SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION
    Inventor: Sug Bong Choe
  • Patent number: 10008538
    Abstract: The present disclosure provides a semiconductor structure, including a logic region and a memory region adjacent to the logic region. The memory region includes a Nth metal layer, a bottom electrode over the Nth metal layer, a magnetic tunneling junction (MTJ) layer over the bottom electrode, a top electrode over the MTJ layer, and a (N+1)th metal layer over the top electrode. The top electrode includes material having an oxidation rate lower than that of Tantalum or Tantalum derivatives. N is an integer greater than or equal to 1.
    Type: Grant
    Filed: November 20, 2015
    Date of Patent: June 26, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Harry-Hak-Lay Chuang, Kuei-Hung Shen
  • Patent number: 9972771
    Abstract: MRAM devices and methods of forming the same are provided. One of the MRAM devices includes a dielectric layer, a resistance variable memory cell and a conductive layer. The dielectric layer is over a substrate and has an opening. The resistance variable memory cell is in the opening and includes a first electrode, a second electrode and a magnetic tunnel junction layer between the first electrode and the second electrode. The conductive layer fills a remaining portion of the opening and is electrically connected to one of the first electrode and the second electrode of the resistance variable memory cell.
    Type: Grant
    Filed: March 24, 2016
    Date of Patent: May 15, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Chieh Mo, Shih-Chi Kuo, Tsung-Hsien Lee, Wu-An Weng, Chung-Yu Lin
  • Patent number: 9923027
    Abstract: A memory cell array structure includes memory cells arranged in m rows and n columns on a substrate, and n columns of first and second well regions with different conductivity types alternatively arranged along the column direction. Each of the memory cells includes first and second diodes. The first diode formed of a first doped region in the same column is disposed in the first well region. The second diode formed of a second doped region in the same column is disposed in the second well region. A third doped region having the conductivity type of the first well region is disposed in the first well region and is connected to the reset line of the same column. A fourth doped region having the conductivity type of the second well region is disposed in the second well region and is connected to the bit line of the same column.
    Type: Grant
    Filed: June 16, 2017
    Date of Patent: March 20, 2018
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Shengfen Chiu, Heng Cao
  • Patent number: 9865321
    Abstract: We describe the manufacturing process for and structure of a CPP MTJ MRAM unit cell that utilizes transfer of spin angular momentum as a mechanism for changing the magnetic moment direction of a free layer. The cell is formed of a vertically or horizontally series connected sequence of N sub-cells, each sub-cell being an identical MTJ element. A statistical population of such multiple sub-cell unit cells has a variation of resistance that is less by a factor of N?1/2 than that of a population of single sub-cells. As a result, such unit cells have an improved read margin while not requiring an increase in the critical switching current.
    Type: Grant
    Filed: July 22, 2016
    Date of Patent: January 9, 2018
    Assignee: Headway Technologies, Inc.
    Inventor: Yimin Guo
  • Patent number: 9847475
    Abstract: Described is an apparatus which comprises: first, second, and third free magnetic layers; a first metal layer of first material coupled to the first and third free magnetic layers; and a second metal layer of second material different from the first material, the second metal layer coupled to the second and third free magnetic layers. Described is an STT majority gate device which comprises: a free magnetic layer in a ring; and first, second, third, and fourth free magnetic layers coupled to the free magnetic layer.
    Type: Grant
    Filed: March 25, 2014
    Date of Patent: December 19, 2017
    Assignee: Intel Corporation
    Inventors: Dmitri E. Nikonov, Sasikanth Manipatruni, II, Ian A. Young
  • Patent number: 9792971
    Abstract: A magnetic junction usable in magnetic devices is described. The magnetic junction includes a reference layer, a free layer, a nonmagnetic spacer layer between the reference and free layers, and a rare earth-transition metal (RE-TM) layer in the reference and/or free layers. The free layer is switchable between stable magnetic states when a write current is passed through the magnetic junction. If the RE-TM layer is in the free layer then the RE-TM layer is between hard and soft magnetic layers in the free layer. In this aspect, the RE-TM layer has a standby magnetic moment greater than a write magnetic moment. If the RE-TM layer is in the reference layer, then the magnetic junction includes a second RE-TM layer. In this aspect, a first saturation magnetization quantity of the RE-TM layer matches a second saturation magnetization quantity of the second RE-TM layer over an operating temperature range.
    Type: Grant
    Filed: June 4, 2015
    Date of Patent: October 17, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Matthew J. Carey, Dmytro Apalkov, Keith Chan
  • Patent number: 9773970
    Abstract: A magnetic field sensor including a first plurality and a second plurality of magnetoresistive sensors, wherein each magnetoresistive sensor of the first plurality and the second plurality of magnetoresistive sensors comprises: an electrode; a reference layer adjacent to the electrode, wherein the reference layer includes a synthetic antiferromagnetic structure; a magnetic sense element; and an intermediate layer between the reference layer and the magnetic sense element; and one or more conductors configured to electrically couple the magnetoresistive sensors of the first plurality and the second plurality in various configurations.
    Type: Grant
    Filed: February 11, 2016
    Date of Patent: September 26, 2017
    Assignee: EVERSPIN TECHNOLOGIES, INC.
    Inventors: Phillip Mather, Jon Slaughter, Nicholas Rizzo
  • Patent number: 9755640
    Abstract: A resistive input system is disclosed, which includes a resistor matrix. The resistor matrix includes M first traces, N second traces, and M*N resistors. First ends of the resistors of a same column are coupled to one of the M first traces, second ends of the resistors of a same row are coupled to one of the N second traces, M is integers greater than 1, and N is integers greater than and equal to 1. The M*N resistors include variable resistors. A measurement circuit measures variations of a first voltage level of each of the second traces while a power control circuit provides the first voltage to the one of the M first traces and the second voltage to the rest of the M first traces. At least one input point is determined according to the variation of the first voltage level of each of the second traces.
    Type: Grant
    Filed: August 13, 2015
    Date of Patent: September 5, 2017
    Assignee: UNIVERSAL CLEMENT CORPORATION
    Inventors: Yann-Cherng Chern, Chih-Sheng Hou, Chih-Hung Huang
  • Patent number: 9741416
    Abstract: Memory devices based on gate controlled ferromagnetism and spin-polarized current injection are provided. The device structure can include a two dimensional (2D) topological insulator (TI) having an active area body. One or a pair of ferromagnetic storage units are provided on top of the 2D TI with a dielectric and a gate thereon. A first contact can be at one end of the 2D TI and a second contact can be at the other end of the 2D TI, with the one or pair of ferromagnetic storage units on the 2D TI between the two contacts to facilitate 2D TI transport along a one-dimensional edge of the first and/or second lateral side. Application of biases via the gate and the first and second contacts enable read and write operations.
    Type: Grant
    Filed: September 12, 2016
    Date of Patent: August 22, 2017
    Assignee: Board of Regents, the University of Texas System
    Inventors: William G. Vandenberghe, Christopher L. Hinkle, Massimo V. Fischetti
  • Patent number: 9711169
    Abstract: According to embodiments of the present invention, a sensor array for reading data from a storage medium including a plurality of tracks is provided. The sensor array includes a first sensor, and a second sensor, wherein the first sensor and the second sensor are configured to obtain signals from adjacent tracks of the plurality of tracks of the storage medium, the signals being associated with data stored at the adjacent tracks. According to further embodiments of the present invention, a storage device and a method of reading data from a storage medium including a plurality of tracks are also provided.
    Type: Grant
    Filed: August 26, 2014
    Date of Patent: July 18, 2017
    Assignee: Marvell International LTD.
    Inventors: Guchang Han, Zhimin Yuan, Pantelis Sophoclis Alexopoulos
  • Patent number: 9685227
    Abstract: A method of reading a memory device that includes a memory cell that stores data of at least two bits includes determining whether a cell resistance level is no greater than a threshold resistance level. If the cell resistance level is smaller than or equal to the threshold resistance level, then the data is read based on a first factor that is inversely proportional to the cell resistance level. If the cell resistance level is greater than the threshold resistance level, then the data is read based on a second factor that is proportional to the cell resistance level.
    Type: Grant
    Filed: March 18, 2015
    Date of Patent: June 20, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-Kyu Lee, Yeong-Taek Lee, Dae-Seok Byeon, Hyun-Kook Park, Hyo-Jin Kwon
  • Patent number: 9685604
    Abstract: A magnetoresistive random-access memory (MRAM) cell includes a free layer having a variable magnetic polarity, wherein the free layer has a first width; a pin layer having a fixed magnetic polarity, wherein the pin layer has the first width; a barrier layer located between the pin layer and the free layer, wherein the barrier layer has a second width that is less than the first width; a top electrode layer located above the free layer, the pin layer, and the barrier layer; a bottom electrode layer located beneath the free layer, the pin layer, and the barrier layer; and a capping layer encapsulating a sidewall of the barrier layer.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: June 20, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Hang Huang, Shih-Chang Liu
  • Patent number: 9647201
    Abstract: The inventive concepts provide magnetic memory devices. The device includes a first magnetic pattern provided in one united body on a substrate and having a plurality of through-holes, a plurality of second magnetic patterns spaced apart from each other on the first magnetic pattern, a tunnel barrier between the first magnetic pattern and the second magnetic patterns, top electrodes disposed on the second magnetic patterns, respectively, and a plurality of plugs electrically connecting the top electrodes to the substrate through the through-holes, respectively.
    Type: Grant
    Filed: June 3, 2015
    Date of Patent: May 9, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jongchul Park, Kyung Rae Byun
  • Patent number: 9553259
    Abstract: A magnetic tunnel junction comprises a conductive first magnetic electrode comprising magnetic recording material. A conductive second magnetic electrode is spaced from the first electrode and comprises magnetic reference material. A non-magnetic tunnel insulator material is between the first and second electrodes. The magnetic recording material of the first electrode comprises a first crystalline magnetic region, in one embodiment comprising Co and Fe. In one embodiment, the first electrode comprises a second amorphous region comprising amorphous XN, where X is one or more of W, Mo, Cr, V, Nb, Ta, Al, and Ti. In one embodiment, the first electrode comprises a second region comprising Co, Fe, and N.
    Type: Grant
    Filed: January 19, 2016
    Date of Patent: January 24, 2017
    Assignee: Micron Technology, Inc.
    Inventor: Manzar Siddik
  • Patent number: 9553128
    Abstract: A technique relates to a linear magnetoresistive random access memory (MRAM) device. A linear magnetic tunnel junction structure includes a non-magnetic tunnel barrier on top of a free layer and a reference layer on top of the non-magnetic tunnel barrier, where the linear magnetic tunnel junction structure is in a line. Bottom contacts are separated from one another by a column space while the plurality of bottom contacts are self-aligned to the linear magnetic tunnel junction structure, such that the plurality of bottom contacts are in the line with and underneath the linear magnetic tunnel junction structure. The bottom contacts abut a bottom of the linear magnetic tunnel junction structure. MRAM devices are formed by having non-conducting parts of the free layer isolating individual interfaces between the bottom contacts and the free layer. The MRAM devices are formed in the line of the linear magnetic tunnel junction structure.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: January 24, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Anthony J. Annunziata, Michael C. Gaidis, Rohit Kilaru
  • Patent number: 9553257
    Abstract: A technique relates to a linear magnetoresistive random access memory (MRAM) device. A linear magnetic tunnel junction structure includes a non-magnetic tunnel barrier on top of a free layer and a reference layer on top of the non-magnetic tunnel barrier, where the linear magnetic tunnel junction structure is in a line. Bottom contacts are separated from one another by a column space while the plurality of bottom contacts are self-aligned to the linear magnetic tunnel junction structure, such that the plurality of bottom contacts are in the line with and underneath the linear magnetic tunnel junction structure. The bottom contacts abut a bottom of the linear magnetic tunnel junction structure. MRAM devices are formed by having non-conducting parts of the free layer isolating individual interfaces between the bottom contacts and the free layer. The MRAM devices are formed in the line of the linear magnetic tunnel junction structure.
    Type: Grant
    Filed: November 23, 2015
    Date of Patent: January 24, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Anthony J. Annunziata, Michael C. Gaidis, Rohit Kilaru
  • Patent number: 9542962
    Abstract: In one embodiment, a magnetic head includes a lower magnetic shield layer positioned at a media-facing surface, a pinned layer positioned above the lower magnetic shield layer at the media-facing surface, at least two MR elements extending in an element height direction by a first length positioned above the pinned layer and separated in a cross-track direction by an inner layer, bias layers extending in the element height direction by a second length positioned on outside edges of the MR elements and the pinned layer, and current paths positioned above and in electrical communication with the bias layers on either side of the inner layer, each current path extending in the element height direction away from the media-facing surface by a third length.
    Type: Grant
    Filed: January 23, 2015
    Date of Patent: January 10, 2017
    Assignee: HGST Netherlands B.V.
    Inventors: Hideki Mashima, Kenichi Meguro, Nobuo Yoshida, Toyoshige Noridomi, Tomohiro Saito, Kaori Suzuki
  • Patent number: 9537086
    Abstract: A technique relates to a linear magnetoresistive random access memory (MRAM) device. A linear magnetic tunnel junction structure includes a non-magnetic tunnel barrier on top of a reference layer and a free layer on top of the non-magnetic tunnel barrier, where the linear magnetic tunnel junction structure is in a line. Magnetoresistive random access memory (MRAM) devices are formed of the reference layer, the non-magnetic tunnel barrier, and the free layer, each of the MRAM devices are in the line. Self-aligned contacts are formed on top of the linear magnetic tunnel junction structure, and the self-aligned contacts individually define the MRAM devices. The self-aligned contacts are separated from one another in the line. Bottom conductive vias are underneath the linear magnetic tunnel junction structure. The bottom conductive vias abut the reference layer of the linear magnetic tunnel junction structure.
    Type: Grant
    Filed: November 24, 2015
    Date of Patent: January 3, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Anthony J. Annunziata, Rohit Kilaru
  • Patent number: 9530822
    Abstract: One embodiment of a nonvolatile memory cell comprises a substrate having a surface, a bidirectional current switch comprising a first electrode, a second electrode, and a semiconductor layer disposed between the first and second electrodes, and a magnetoresistive element having a direct contact with the bidirectional current switch and comprising a free ferromagnetic layer having a reversible magnetization direction, a pinned ferromagnetic layer having a fixed magnetization direction, and a tunnel barrier layer disposed between the free and pinned ferromagnetic layers, wherein the magnetization direction of the free ferromagnetic layer is reversed by a bidirectional spin polarized current running through the magnetoresitive element in a direction perpendicular to the substrate surface, and wherein a magnitude of the spin polarized current is controlled by the bidirectional current switch. Other embodiments are described and shown.
    Type: Grant
    Filed: April 28, 2014
    Date of Patent: December 27, 2016
    Inventor: Alexander Mikhailovich Shukh
  • Patent number: 9525125
    Abstract: A technique relates to a linear magnetoresistive random access memory (MRAM) device. A linear magnetic tunnel junction structure includes a non-magnetic tunnel barrier on top of a reference layer and a free layer on top of the non-magnetic tunnel barrier, where the linear magnetic tunnel junction structure is in a line. Magnetoresistive random access memory (MRAM) devices are formed of the reference layer, the non-magnetic tunnel barrier, and the free layer, each of the MRAM devices are in the line. Self-aligned contacts are formed on top of the linear magnetic tunnel junction structure, and the self-aligned contacts individually define the MRAM devices. The self-aligned contacts are separated from one another in the line. Bottom conductive vias are underneath the linear magnetic tunnel junction structure. The bottom conductive vias abut the reference layer of the linear magnetic tunnel junction structure.
    Type: Grant
    Filed: August 20, 2015
    Date of Patent: December 20, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Anthony J. Annunziata, Rohit Kilaru
  • Patent number: 9496375
    Abstract: To improve productivity of a transistor that includes an oxide semiconductor and has good electrical characteristics. In a top-gate transistor including a gate insulating film and a gate electrode over an oxide semiconductor film, a metal film is formed over the oxide semiconductor film, oxygen is added to the metal film to form a metal oxide film, and the metal oxide film is used as a gate insulating film. After an oxide insulating film is formed over the oxide semiconductor film, a metal film may be formed over the oxide insulating film. Oxygen is added to the metal film to form a metal oxide film and added also to the oxide semiconductor film or the oxide insulating film.
    Type: Grant
    Filed: August 21, 2015
    Date of Patent: November 15, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Atsuo Isobe, Kunio Hosoya
  • Patent number: 9490421
    Abstract: A method and system provide a magnetic junction usable in a magnetic device and which resides on a substrate. The magnetic junction includes a reference layer, a nonmagnetic spacer layer, and a free layer. The nonmagnetic spacer layer is between the reference layer and the free layer. The free layer, the nonmagnetic spacer layer and the reference layer form nonzero angle(s) with the substrate. The magnetic junction is configured such that the free layer is switchable between a plurality of stable magnetic states when a write current is passed through the magnetic junction.
    Type: Grant
    Filed: January 28, 2013
    Date of Patent: November 8, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dmytro Apalkov, Alexey Vasilyevitch Khvalkovskiy, Vladimir Nikitin, Steven M. Watts
  • Patent number: 9490000
    Abstract: A magnetic junction usable in magnetic devices is described. The magnetic junction includes at least one reference layer, at least one nonmagnetic spacer layer and a free layer. The nonmagnetic spacer layer(s) are between the reference layer(s) and the free layer. The free layer has a magnetic thermal stability coefficient having a plurality of magnetic thermal stability coefficient phases. A first phase magnetic thermal stability coefficient has a first slope below a first temperature. A second phase magnetic thermal stability coefficient has a second slope above the first temperature and below a second temperature greater than the first temperature. The first and second slopes are unequal at the first temperature. The magnetic thermal stability coefficient is zero only above the second temperature. The free layer is switchable between stable magnetic states when a write current passed through the magnetic junction.
    Type: Grant
    Filed: December 8, 2014
    Date of Patent: November 8, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dmytro Apalkov, Roman Chepulskyy
  • Patent number: 9490164
    Abstract: In one aspect, a method for forming a contact to a device is provided which includes the steps of: forming a conformal etch stop layer surrounding the device; forming a dielectric layer over and covering the device; forming a contact trench in the dielectric layer, wherein the contact trench is present over the device and extends down to, or beyond, the etch stop layer; exposing a contact region of the device within the contact trench by selectively removing a portion of the etch stop layer covering a top portion of the device; and filling the contact trench with a conductive material to form the contact to the device. Other methods for forming a contact to a device and also to BEOL wiring are provided as are device contact structures.
    Type: Grant
    Filed: June 23, 2015
    Date of Patent: November 8, 2016
    Assignee: International Business Machines Corporation
    Inventors: Sebastian U. Engelmann, Steve J. Holmes, Qinghuang Lin, Nathan P. Marchack, Eugene J. O'Sullivan
  • Patent number: 9484348
    Abstract: Source/drain contact structures with increased contact areas for a multiple fin-based complementary metal oxide semiconductor field effect transistor (CMOSFET) having unmerged epitaxial source/drain regions and methods for forming such source/drain contact structures are provided by forming wrap-around source/drain contact structures for both n-type FinFETs and p-type FinFETs. Each of first source/drain contact structures for the n-type FinFETs includes at least one first conductive plug encapsulating epitaxial first source/drain regions on one side of a gate structure, while each of second source/drain contact structures for the p-type FinFETs includes at least a contact metal layer portion encapsulating epitaxial second source/drain regions on one side of the gate structure, and a second conductive plug located over a top surface of the contact metal layer portion.
    Type: Grant
    Filed: October 3, 2015
    Date of Patent: November 1, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Veeraraghavan S. Basker, Kangguo Cheng, Ali Khakifirooz
  • Patent number: 9484208
    Abstract: The present invention discloses a preparation method of a germanium-based Schottky junction, comprising, cleaning a surface of N-type germanium-based substrate, then depositing a layer of CeO2 on the surface, and further depositing a layer of metal. The stability Ce—O—Ge bonds can be formed at the interface after rare earth oxides CeO2 are in contact with the germanium substrate, and this is beneficial to reduce the interface state density, improve the quality of the interface, and reduce the MIGS and suppress Fermi-level pinning. Meanwhile, the tunneling resistance introduced by CeO2 between the metal and the germanium substrate is smaller relative to the case of Si3N4, Al2O3, Ge3N4 or the like. In view of the excellent surface characteristics and small conduction band offset relative to the germanium substrate, interposing of the CeO2 dielectric layer is applicable to the preparation the germanium-based Schottky junction having a low resistivity.
    Type: Grant
    Filed: September 30, 2013
    Date of Patent: November 1, 2016
    Assignee: Peking University
    Inventors: Ru Huang, Meng Lin, Zhiqiang Li, Xia An, Ming Li, Quanxin Yun, Min Li, Pengqiang Liu, Xing Zhang
  • Patent number: 9478239
    Abstract: Implementations disclosed herein include a reader comprising a magnetically free layer and first barrier layer, wherein the barrier layer is in direct contact with a bottom shield in a down-track direction. Another implementation includes a device comprising a sensor stack comprising a free layer and a barrier layer; a synthetic antiferromagnetic shield layer comprising a reference layer and a pinned layer, wherein direction of magnetization of the reference layer forms an obtuse angle with direction of magnetization of the free layer in a quiescent state.
    Type: Grant
    Filed: June 27, 2013
    Date of Patent: October 25, 2016
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Victor Boris Sapozhnikov, Mohammed Sharia Ullah Patwari
  • Patent number: 9431601
    Abstract: Magnetic element including a first magnetic layer having a first magnetization; a second magnetic layer having a second magnetization; a tunnel barrier layer between the first and the second magnetic layers; and an antiferromagnetic layer exchanged coupling the second magnetic layer such that the second magnetization is pinned below a critical temperature of the antiferromagnetic layer, and can be freely varied when the antiferromagnetic layer is heated above that critical temperature. The magnetic element also includes an oxygen gettering layer between the second magnetic layer and the antiferromagnetic layer, or within the second magnetic layer. The magnetic element has reduced insertion of oxygen atoms in the antiferromagnetic layer and possibly reduced diffusion of manganese in the second magnetic layer resulting in an enhanced exchange bias and/or enhanced resistance to temperature cycles and improved life-time.
    Type: Grant
    Filed: November 19, 2013
    Date of Patent: August 30, 2016
    Assignee: CROCUS TECHNOLOGY SA
    Inventors: Sebastien Bandiera, Ioan Lucian Prejbeanu
  • Patent number: 9349772
    Abstract: A method of fabricating an integrated circuit includes depositing a bottom electrode layer, an MTJ layer, and a top electrode layer over a passivation layer and within a trench of the passivation layer and removing portions of the MTJ layer and the top electrode layer to form an MTJ/top electrode stack over the bottom electrode layer and at least partially within portions of the trench having being reopened by said removing. The method further includes forming a further passivation layer over the MTJ/top electrode stack, forming a further ILD layer of the further passivation layer, and reforming a top electrode layer over the ILD layer and over the MTJ/top electrode stack. Still further, the method includes removing portions of the bottom electrode layer, the further passivation layer, the further ILD layer, and the re-formed top electrode layer to form a bottom electrode/MTJ/top electrode stack.
    Type: Grant
    Filed: April 25, 2014
    Date of Patent: May 24, 2016
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Wanbing Yi, Yang Hong, Yi Jiang, Francis Poh, Tze Ho Simon Chan, Juan Boon Tan
  • Patent number: 9337415
    Abstract: A magnetic tunnel junction (MTJ) for use in a magnetoresistive random access memory (MRAM) has a CoFeB alloy free layer located between the MgO tunnel barrier layer and an upper MgO capping layer, and a CoFeB alloy enhancement layer between the MgO capping layer and a Ta cap. The CoFeB alloy free layer has high Fe content to induce perpendicular magnetic anisotropy (PMA) at the interfaces with the MgO layers. To avoid creating unnecessary PMA in the enhancement layer due to its interface with the MgO capping layer, the enhancement layer has low Fe content. After all of the layers have been deposited on the substrate, the structure is annealed to crystallize the MgO. The CoFeB alloy enhancement layer inhibits diffusion of Ta from the Ta cap layer into the MgO capping layer and creates good crystallinity of the MgO by providing CoFeB at the MgO interface.
    Type: Grant
    Filed: March 20, 2015
    Date of Patent: May 10, 2016
    Assignee: HGST Netherlands B.V.
    Inventors: Sangmun Oh, Zheng Gao, Kochan Ju
  • Patent number: 9299746
    Abstract: The present disclosure provides a memory cell that includes a resistive memory element disposed between a first conductor and a second conductor, the first conductor and the second conductor configured to activate the resistive memory element. The memory cell also includes a backward diode disposed in series with the memory element between the memory element and either the first conductor or the second conductor.
    Type: Grant
    Filed: October 12, 2011
    Date of Patent: March 29, 2016
    Assignee: Hewlett-Packard Enterprise Development LP
    Inventors: Gilberto M. Ribeiro, Janice H. Nickel