Abstract: The present disclosure may provide a semiconductor device with a low manufacturing degree of difficulty and an enhanced performance. The device may include conductive layers and insulating layers, alternately stacked, each of the insulating layers being thinner than each of the conductive layers; a channel layer passing through the conductive layers and the insulating layers; a data storage layer surrounding a side-wall of the channel layer; and first charge blocking patterns, each of the first charge blocking patterns interposed between the conductive layers and the insulating layers and between the data storage layer and the conductive layers.

Abstract: According to one embodiment, a semiconductor memory device includes a stacked body, a semiconductor pillar, an insulating film, and a charge storage film. The stacked body includes a plurality of electrode films stacked with an inter-layer insulating film provided between the electrode films. The semiconductor pillar pierces the stacked body. The insulating film is provided between the semiconductor pillar and the electrode films on an outer side of the semiconductor pillar with a gap interposed. The charge storage film is provided between the insulating film and the electrode films. The semiconductor pillar includes germanium. An upper end portion of the semiconductor pillar is supported by an interconnect provided above the stacked body.

Abstract: According to one embodiment, a semiconductor memory device includes a substrate, a first stacked body, a second stacked body, a memory film, a gate insulating film, and a channel body. The first stacked body has a plurality of electrode layers and a plurality of first insulating layers. The second stacked body has a selector gate and a second insulating layer. The memory film is provided on a sidewall of a first hole. The gate insulating film is provided on a sidewall of a second hole. The channel body is provided on an inner side of the memory film and on an inner side of the gate insulating film. A step part is provided between a side face of the selector gate and the second insulating layer. A region positioned near a top end of the selector gate of the channel body is silicided.

Abstract: Technology is described herein for manufacturing a three-dimensional 3D stacked memory structure having multiple layers of single crystal silicon or other semiconductor. The multiple layers of single crystal semiconductor are suitable for implementing multiple levels of high performance memory cells.

Abstract: Provided is a three dimensional semiconductor device. The device may include mold layers vertically and sequentially stacked, a conductive pattern between the stacked mold layers, a plugging pattern vertically penetrating the stacked mold layers, an intermediate pattern between the conductive pattern and the plugging pattern, and protective layer patterns between the mold layers and the plugging pattern, wherein the protective layer patterns are separated by the intermediate pattern.

Abstract: A nonvolatile semiconductor memory device includes: a substrate; a stacked body with a plurality of dielectric films and electrode films alternately stacked therein, the stacked body being provided on the substrate and having a step in its end portion for each of the electrode films; an interlayer dielectric film burying the end portion of the stacked body; a plurality of semiconductor pillars extending in the stacking direction of the stacked body and penetrating through a center portion of the stacked body; a charge storage layer provided between one of the electrode films and one of the semiconductor pillars; and a plug buried in the interlayer dielectric film and connected to a portion of each of the electrode films constituting the step, a portion of each of the dielectric films in the center portion having a larger thickness than a portion of each of the dielectric films in the end portion.

Abstract: Provided are a three dimensional semiconductor memory device and a method of fabricating the same. The method includes forming a stepwise structure by using mask patterns and a sacrificial mask pattern formed on the mask patterns as a consumable etch mask.

Abstract: The invention provides for polysilicon vias connecting conductive polysilicon layers formed at different heights. Polysilicon vias are advantageously used in a monolithic three dimensional memory array of charge storage transistors. Polysilicon vias according to the present invention can be used, for example, to connect the channel layer of a first device level of charge storage transistor memory cells to the channel layer of a second device layer of such cells formed above the first device level. Similarly, vias according to the present invention can be used to connect the wordline of a first device level of charge storage transistor memory cells to the channel layer of a second device layer of such cells.

Abstract: The invention provides for polysilicon vias connecting conductive polysilicon layers formed at different heights. Polysilicon vias are advantageously used in a monolithic three dimensional memory array of charge storage transistors. Polysilicon vias according to the present invention can be used, for example, to connect the channel layer of a first device level of charge storage transistor memory cells to the channel layer of a second device layer of such cells formed above the first device level. Similarly, vias according to the present invention can be used to connect the wordline of a first device level of charge storage transistor memory cells to the channel layer of a second device layer of such cells.

Abstract: Vertically stacked integrated circuits and methods of fabrication thereof are disclosed. Deep vias that provide vertical electrical connection for vertically stacked integrated circuits are formed early in the manufacturing process, before integrated circuits are bonded together to form a three dimensional integrated circuit (3D-IC).

Abstract: The present invention discloses a three-dimensional memory (3D-M) with polarized 3D-ROM (three-dimensional read-only memory) cells. Polarized 3D-ROM can ensure a larger unit array and therefore, a better integratibility. The present invention further discloses a 3D-M with seamless 3D-ROM cells. Seamless 3D-ROM can ensure a better manufacturing yield.