Rom Only (epo) Patents (Class 257/E21.667)
  • Patent number: 8999785
    Abstract: Flash-to-ROM conversion is performed by converting single transistor flash memory cells to single transistor ROM cells. An S-Flash memory cell is converted to a programmed ROM cell by introducing a threshold voltage implant into the channel region of the S-Flash memory cell. Alternately, an S-Flash memory cell is converted to a programmed ROM cell by introducing a threshold voltage implant into a substrate region in alignment with an edge of the gate electrode of the S-Flash memory cell. The width of the mask through which this threshold voltage implant is performed can be varied, such that the threshold voltage implant region can have different dopant concentrations, thereby allowing multiple bits to be represented by the programmed ROM cell. In another embodiment, a Y-flash memory cell is converted to a programmed ROM cell by adjusting the length of a floating gate extension region of the Y-Flash memory cell.
    Type: Grant
    Filed: September 27, 2011
    Date of Patent: April 7, 2015
    Assignee: Tower Semiconductor Ltd.
    Inventors: Itzhak Edrei, Yakov Roizin
  • Patent number: 8687432
    Abstract: This invention proposes a multi-bit resistive-switching memory cell and array thereof. Multiple conduction paths are formed on each memory cell and independent of each other, and each conduction path can be in a high-resistance or low-resistance state, so as to form a multi-bit resistive-switching memory cell. A memory cell array can be formed by arranging a plurality of multi-bit resistive-switching memory cells, and the memory cell array provides a simple, high density, high performance and cost-efficient proposal.
    Type: Grant
    Filed: January 17, 2012
    Date of Patent: April 1, 2014
    Assignee: National Chiao Tung University
    Inventors: Tuo-Hung Hou, Shih-Chieh Wu
  • Patent number: 8563403
    Abstract: A method includes forming a first integrated circuit (IC) device having a first substrate, an alignment via defined in the first substrate, a first wiring layer over the alignment via, and a first bonding layer over the first wiring layer; forming a second IC device having a second substrate, a second wiring layer over the second substrate, and a second bonding layer over the second wiring layer; bonding the first bonding layer of first IC device to the second bonding layer of second IC device; thinning a backside of the first IC device so as to expose the alignment via; and using the exposed alignment via to form a deep, through substrate via (TSV) that passes through the first IC device, through a bonding interface between the first IC device and second IC device, and landing on the second wiring layer of the second IC device.
    Type: Grant
    Filed: June 27, 2012
    Date of Patent: October 22, 2013
    Assignee: International Business Machines Corporation
    Inventors: Mukta G. Farooq, Spyridon Skordas, Richard P. Volant, Kevin R. Winstel
  • Patent number: 8415218
    Abstract: A method of growing an epitaxial silicon layer is provided. The method comprising providing a substrate including an oxygen-terminated silicon surface and forming a first hydrogen-terminated silicon surface on the oxygen-terminated silicon surface. Additionally, the method includes forming a second hydrogen-terminated silicon surface on the first hydrogen-terminated silicon surface through atomic-layer deposition (ALD) epitaxy from SiH4 thermal cracking radical assisted by Ar flow and flash lamp annealing continuously. The second hydrogen-terminated silicon surface is capable of being added one or more layer of silicon through ALD epitaxy from SiH4 thermal cracking radical assisted by Ar flow and flash lamp annealing continuously. In one embodiment, the method is applied for making devices with thin-film transistor (TFT) floating gate memory cell structures which is capable for three-dimensional integration.
    Type: Grant
    Filed: October 27, 2008
    Date of Patent: April 9, 2013
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Fumitake Mieno
  • Publication number: 20130075803
    Abstract: Flash-to-ROM conversion is performed by converting single transistor flash memory cells to single transistor ROM cells. An S-Flash memory cell is converted to a programmed ROM cell by introducing a threshold voltage implant into the channel region of the S-Flash memory cell. Alternately, an S-Flash memory cell is converted to a programmed ROM cell by introducing a threshold voltage implant into a substrate region in alignment with an edge of the gate electrode of the S-Flash memory cell. The width of the mask through which this threshold voltage implant is performed can be varied, such that the threshold voltage implant region can have different dopant concentrations, thereby allowing multiple bits to be represented by the programmed ROM cell. In another embodiment, a Y-flash memory cell is converted to a programmed ROM cell by adjusting the length of a floating gate extension region of the Y-Flash memory cell.
    Type: Application
    Filed: September 27, 2011
    Publication date: March 28, 2013
    Applicant: Tower Semiconductor Ltd.
    Inventors: Itzhak Edrei, Yakov Roizin
  • Patent number: 8293601
    Abstract: A non-volatile semiconductor storage device has a plurality of memory strings with a plurality of electrically rewritable memory cells connected in series. Each of the memory strings includes: a memory columnar semiconductor extending in a direction perpendicular to a substrate; a tunnel insulation layer contacting the memory columnar semiconductor; a charge accumulation layer contacting the tunnel insulation layer and accumulating charges; a block insulation layer contacting the charge accumulation layer; and a plurality of memory conductive layers contacting the block insulation layer. The lower portion of the charge accumulation layer is covered by the tunnel insulation layer and the block insulation layer.
    Type: Grant
    Filed: January 20, 2011
    Date of Patent: October 23, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masaru Kito, Ryota Katsumata, Yoshiaki Fukuzumi, Masaru Kidoh, Hiroyasu Tanaka, Hideaki Aochi, Yasuyuki Matsuoka
  • Patent number: 8212231
    Abstract: A resistive memory device and a fabricating method thereof are introduced herein. In resistive memory device, a plurality of bottom electrodes is disposed in active region of a substrate. Each of the bottom electrodes is disposed to correspond to each of the conductive channels; a patterned resistance switching material layer and the patterned top electrode layer are sequentially stacked on the bottom electrodes. An air dielectric layer exists between the patterned resistance switching material layer and the bottom electrodes. A plurality of patterned interconnections is disposed on the patterned top electrode.
    Type: Grant
    Filed: December 30, 2009
    Date of Patent: July 3, 2012
    Assignee: Industrial Technology Research Institute
    Inventor: Wei-Su Chen
  • Patent number: 8106463
    Abstract: A ROM memory cell has significantly less total area than previously known ROM memory cells. Instead of using only one layer in the manufacturing process to program the memory cells, at least two layers are used to program the memory cells. This flexibility allows the memory cell to be reduced in area, which in turn produces a ROM that is more area efficient and consequently lower in cost. As the bitline length and capacitance are reduced, the speed and power consumption are also improved.
    Type: Grant
    Filed: December 6, 2005
    Date of Patent: January 31, 2012
    Assignee: ARM, Inc.
    Inventors: Sudhir S. Moharir, Zhigeng Liu
  • Publication number: 20110317467
    Abstract: A semiconductor device includes a memory element including a stack structure stacking an insulator film and a metal film or a metal compound film; and a transistor including a gate structure having an identical stack structure as that of the memory element.
    Type: Application
    Filed: March 17, 2011
    Publication date: December 29, 2011
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventor: Jun Nagayama
  • Patent number: 7977749
    Abstract: A semiconductor device includes an active region defining at least four surfaces, the four surfaces including first, second, third, and fourth surfaces, a gate insulation layer formed around the four surfaces of the active region, and a gate electrode formed around the gate insulation layer and the four surfaces of the active region.
    Type: Grant
    Filed: December 28, 2009
    Date of Patent: July 12, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jun-Hee Cho
  • Patent number: 7977196
    Abstract: A semiconductor device includes an active region defining at least four surfaces, the four surfaces including first, second, third, and fourth surfaces, a gate insulation layer formed around the four surfaces of the active region, and a gate electrode formed around the gate insulation layer and the four surfaces of the active region.
    Type: Grant
    Filed: December 28, 2009
    Date of Patent: July 12, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jun-Hee Cho
  • Patent number: 7728320
    Abstract: A phase change memory (PCM) device includes a substrate, bottom electrodes disposed in the substrate, a first dielectric layer disposed on the substrate, second dielectric layers, third dielectric layers, cup-shaped thermal electrodes, top electrodes, and PC material spacers. In the PCM device, each cup-shaped thermal electrode contacts with each bottom electrode. Second and third dielectric layers are disposed over the substrate in different directions, wherein each of the second and third dielectric layers covers a portion of the area surrounded by each cup-shaped thermal electrode, and the third dielectric layers overlay the second dielectric layers. The top electrodes are disposed on the third dielectric layers, wherein a plurality of stacked structure composed of the third dielectric layers and the top electrodes are formed thereon.
    Type: Grant
    Filed: August 11, 2006
    Date of Patent: June 1, 2010
    Assignee: Industrial Technology Research Institute
    Inventor: Wei-Su Chen
  • Patent number: 7687377
    Abstract: In a method of fabricating a phase change memory (PCM) device, a substrate having bottom electrodes formed therein is provided. A first dielectric layer having cup-shaped thermal electrodes is formed over the substrate. Second dielectric layers are formed on the substrate. Stacked structures are formed on the substrate. A PC material film is formed over the substrate and covers the stacked structures and the second dielectric layers. The PC material film is anisotropically etched to form PC material spacers on sidewalls of the stacked structures, and each of the PC material spacers physically and electrically contacts each of the cup-shaped thermal electrodes and top electrodes. The PC material spacers include phase change material. The PC material spacers are over-etched to remove the PC material film on the sidewalls of the second dielectric layers.
    Type: Grant
    Filed: March 5, 2009
    Date of Patent: March 30, 2010
    Assignee: Industrial Technology Research Institute
    Inventor: Wei-Su Chen
  • Patent number: 7655569
    Abstract: The invention prevents a wiring layer in a memory region from being exposed to prevent a change in wire resistance and degradation of reliability. A SiO2 film as an etching stopper film which transmits ultraviolet light is formed on pad electrodes and an interlayer insulation film. Then, the SiO2 film on the pad electrodes is etched selectively and the SiO2 film in an EPROM region is left. A silicon nitride film and a polyimide film are then formed on the SiO2 film and on the pad electrodes where the SiO2 film is removed, as a protection film which does not transmit ultraviolet light. The silicon nitride film and the polyimide film on the pad electrodes and in the EPROM region are then selectively removed by etching. Since the SiO2 film functions as an etching stopper at this time, the interlayer insulation film under the SiO2 film is prevented from being etched and a control gate line metal layer is prevented from being exposed.
    Type: Grant
    Filed: January 28, 2008
    Date of Patent: February 2, 2010
    Assignees: Sanyo Electric Co., Ltd., Sanyo Semiconductor Co., Ltd.
    Inventors: Yuichi Inaba, Yutaka Yamada, Shigehiro Morikawa
  • Patent number: 7638387
    Abstract: A mask read-only memory (ROM) includes a dielectric layer formed on a substrate and a plurality of first conductive lines formed on the dielectric layer. A plurality of diodes are formed in the first conductive lines, and a plurality of final vias are formed for a first set of the diodes each representing a first type of memory cell, with no final via being formed for a second set of diodes each representing a second type of memory cell. Each of a plurality of second conductive lines is formed over a column of the diodes.
    Type: Grant
    Filed: June 27, 2007
    Date of Patent: December 29, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-Kyu Lee, Hee-Seog Jeon, Jeong-Uk Han, Young-Ho Kim, Myung-Jo Chun
  • Patent number: 7279418
    Abstract: The storage medium comprises an array of memory cells (3) which can be addressed by first (1) and second (2) conductors. Each memory cell (3) comprises one zone (10) of an active layer (8) which is initially electrically insulating and which can be made electrically conductive by means of localized plastic deformation (4), such as to selectively connect the first (1) and second (2) associated conductors. Binary information stored in the memory cell (3) is determined by the electrical conducting state of the corresponding zone (10) of the active layer (8). The active layer (8) can be formed using a charged resin. The medium production method comprises assembly of a blank storage medium having an active layer (8) which is in the initial insulating state, production of a stamping die having a stamping pattern that corresponds to the information to be stored, and stamping of the storage medium using the stamping die.
    Type: Grant
    Filed: December 2, 2004
    Date of Patent: October 9, 2007
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Bernard Bechevet, Pierre Gaud, Veronique Sousa