Charge Trapping Insulator Nonvolatile Memory Structures (epo) Patents (Class 257/E21.679)
  • Patent number: 10199392
    Abstract: A semiconductor material is patterned to define elongated fins insulated from an underlying substrate. A polysilicon semiconductor material is deposited over and in between the elongated fins, and is patterned to define elongated gates extending to perpendicularly cross over the elongated fins at a transistor channel. Sidewall spacers are formed on side walls of the elongated gates. Portions of the elongated fins located between the elongated gates are removed, along with the underlying insulation, to expose the underlying substrate. One or more semiconductor material layers are then epitaxially grown from the underlying substrate at locations between the elongated gates. The one or more semiconductor material layers may include an undoped epi-layer and an overlying doped epi-layer. The epitaxial material defines a source or drain of the transistor.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: February 5, 2019
    Assignee: STMICROELECTRONICS, INC.
    Inventors: Ronald K. Sampson, Nicolas Loubet
  • Patent number: 9947658
    Abstract: In a method for manufacturing a semiconductor device, a doped layer doped with a first dopant is formed in a substrate. A semiconductor layer is formed on the doped layer. A fin structure is formed by patterning at least the semiconductor layer and the doped layer such that the fin structure comprises a channel region including the semiconductor layer, and a well region including the doped layer. An isolation insulating layer is formed such that the channel region of the fin structure protrudes from the isolation insulating layer and the well region of the fin structure is embedded in the isolation insulating layer. A gate structure is formed over a part of the fin structure and the isolation insulating layer. The semiconductor layer is at least one of a doped silicon layer or a non-doped silicon layer.
    Type: Grant
    Filed: April 11, 2016
    Date of Patent: April 17, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Sheng Wu, Chen Hua Tsai, Hou-Yu Chen, Chia-Wei Soong, Chih-Pin Tsao
  • Patent number: 9947669
    Abstract: A dynamic random access memory (DRAM) includes a substrate, a plurality of isolation structures, a plurality of conductive structure sets, a plurality of bit-line structures, and a plurality of spacers. The substrate has a plurality of active areas. The isolation structures are located in the substrate and extending along a first direction. Each of the isolation structures is disposed between two adjacent active areas. The conductive structure sets are disposed in parallel along the first direction and on the substrate. The bit-line structures are disposed in parallel along a second direction and on the substrate. The bit-line structures penetrate through the conductive structure sets. The spacers are disposed in parallel along the second direction and on sidewalls of the bit-line structures, so as to electrically isolate the bit-line structures from the conductive structure sets.
    Type: Grant
    Filed: May 9, 2017
    Date of Patent: April 17, 2018
    Assignee: Winbond Electronics Corp.
    Inventors: Kazuaki Takesako, Yoshinori Tanaka
  • Patent number: 9935101
    Abstract: Fabrication of a semiconductor structure includes forming a set of two or more fins on a source/drain region formed on a substrate. A first mask layer and a second mask layer are formed on each fin. A spacer layer is formed on the source/drain region and between each fin, and a dielectric layer is formed on the spacer layer and along an exterior of each fin. A plurality of gate metal portions is created each having a thickness about equal to a target thickness. The first mask layer and an exposed portion of the dielectric layer are removed from each fin. An interlayer dielectric is deposited on the semiconductor structure. Portions of the interlayer dielectric and the gate metal are removed to a top of the second mask layer. The gate metal portions are each recessed to substantially the same depth.
    Type: Grant
    Filed: July 27, 2016
    Date of Patent: April 3, 2018
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Xin Miao, Wenyu Xu, Chen Zhang
  • Patent number: 9881921
    Abstract: A dual gate CMOS structure including a semiconductor substrate; a first channel structure including a first semiconductor material and a second channel structure including a second semiconductor material on the substrate. The first semiconductor material including SixGe1-x where x=0 to 1 and the second semiconductor material including a group III-V compound material. A first gate stack on the first channel structure includes: a first native oxide layer as an interface control layer, the first native oxide layer comprising an oxide of the first semiconductor material; a first high-k dielectric layer; a first metal gate layer. A second gate stack on the second channel structure includes a second high-k dielectric layer; a second metal gate layer. The interface between the second channel structure and the second high-k dielectric layer is free of any native oxides of the second semiconductor material.
    Type: Grant
    Filed: April 10, 2017
    Date of Patent: January 30, 2018
    Assignee: International Business Machines Corporation
    Inventors: Lukas Czornomaz, Veeresh Vidyadhar Deshpande, Vladimir Djara, Jean Fompeyrine
  • Patent number: 9853166
    Abstract: A semiconductor device including a plurality of suspended nanowires and a gate structure that is present on a channel region portion of the plurality of suspended nanowires. The gate structure includes a uniform length extending from an upper surface of the gate structure to the base of the gate structure. A dielectric spacer having a graded composition is present in direct contact with the gate structure. The dielectric spacer having a uniform length extending from an upper surface of the gate structure to the base of the gate structure. Source and drain regions are present on source and drain region portions of the plurality of suspended nanowires.
    Type: Grant
    Filed: July 25, 2014
    Date of Patent: December 26, 2017
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek
  • Patent number: 9741803
    Abstract: A charge trap memory device is provided. In one embodiment, the charge trap memory device includes a semiconductor material structure having a vertical channel extending from a first diffusion region formed in a semiconducting material to a second diffusion region formed over the first diffusion region, the vertical channel electrically connecting the first diffusion region to the second diffusion region. A tunnel dielectric layer is disposed on the vertical channel, a multi-layer charge-trapping region including a first deuterated layer disposed on the tunnel dielectric layer, a first nitride layer disposed on the first deuterated layer, and a second nitride layer comprising a deuterium-free trap-dense, oxygen-lean nitride disposed on the first nitride layer. The second nitride layer includes a majority of charge traps distributed in the multi-layer charge-trapping region.
    Type: Grant
    Filed: June 22, 2016
    Date of Patent: August 22, 2017
    Assignee: Cypress Semiconductor Corporation
    Inventors: Sagy Levy, Fredrick Jenne, Krishnaswamy Ramkumar
  • Patent number: 9704975
    Abstract: A non-volatile memory device includes a semiconductor substrate, a well region situated on the semiconductor substrate, a floating gate situated on the well region, a floating gate channel region, a control gate situated on both sides of the floating gate, a control gate channel region, and an ion implantation area for regulating a program threshold voltage integrally formed between an area underneath of the floating gate and the control gate and a foreside of the well region, wherein a doping concentration of the ion implantation area for regulating a program threshold voltage is greater than a doping concentration of the well region. Therefore, the non-volatile memory device of examples integrally forms an ion implantation area for regulating a program threshold voltage irrespective of a channel region of a floating gate and a control gate so as to guarantee durability of a non-volatile memory device.
    Type: Grant
    Filed: September 11, 2015
    Date of Patent: July 11, 2017
    Assignee: Magnachip Semiconductor, Ltd.
    Inventors: Doo Yeol Ryu, Jeong Ho Cho, Kyung Ho Lee
  • Patent number: 9583502
    Abstract: After forming a first film over the main surface of a semiconductor substrate, the first film is patterned, thereby forming a control gate electrode for a non-volatile memory, a dummy gate electrode, and a first film pattern. Subsequently, a memory gate electrode for the non-volatile memory adjacent to the control gate electrode is formed. Then, the first film pattern is patterned thereby forming a gate electrode and a dummy gate electrode.
    Type: Grant
    Filed: October 2, 2015
    Date of Patent: February 28, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Hiroshi Nishikizawa, Takuro Homma, Hiraku Chakihara, Mitsuhiro Noguchi
  • Patent number: 9570581
    Abstract: A stack gate structure for a non-volatile memory array has a semiconductor substrate having a plurality of substantially parallel spaced apart active regions, with each active region having an axis in a first direction. A first insulating material is between each stack gate structure in the second direction perpendicular to the first direction. Each stack gate structure has a second insulating material over the active region, a charge holding gate over the second insulating material, a third insulating material over the charge holding gate, and a first portion of a control gate over the third insulating material. A second portion of the control gate is over the first portion of the control gate and over the first insulating material adjacent thereto and extending in the second direction. A fourth insulating material is over the second portion of the control gate.
    Type: Grant
    Filed: April 5, 2016
    Date of Patent: February 14, 2017
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Willem-Jan Toren, Xian Liu, Gerhard Metzger-Brueckl, Nhan Do, Stephan Wege, Nadia Miridi, Chieng-Sheng Su, Cecile Bernardi, Liz Cuevas, Florence Guyot, Yueh-Hsin Chen, Henry Om'mani, Mandana Tadayoni
  • Patent number: 9553088
    Abstract: A method for fabricating a semiconductor device comprises forming active regions on a semiconductor substrate, forming a gate stack over the active regions and regions adjacent to the active regions, depositing a layer of conductive material over the active regions and the substrate, patterning a first mask over the conductive material, etching to remove exposed portions of the conductive material and form conductive contacts, patterning a second mask over portions of the gate stacks and conductive contacts, and etching to remove exposed portions of the gate stack.
    Type: Grant
    Filed: September 24, 2015
    Date of Patent: January 24, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Veeraraghavan S. Basker, Kangguo Cheng, Theodorus Standaert, Junli Wang
  • Patent number: 9536880
    Abstract: Methods of fabricating devices (e.g., FDSOI devices) having multiple threshold voltages are described. One method includes providing a first fixed charge region proximate to an interface of an insulating (e.g., buried oxide (BOX) layer) and a semiconductor substrate for a first device. The first charge region has a first configuration of fixed charges. The method also includes providing a second fixed charge region proximate to the interface of the insulating layer and the semiconductor substrate for the second device. The second charge region has a second configuration of fixed charges that is different than the first configuration.
    Type: Grant
    Filed: May 5, 2015
    Date of Patent: January 3, 2017
    Assignee: BROADCOM CORPORATION
    Inventors: Qintao Zhang, Aimin Xing
  • Patent number: 9466497
    Abstract: The invention provides a method for fabricating a silicon-oxide-nitride-oxide-silicon (SONOS) non-volatile memory cell, comprising: (S1) forming a pad oxide pattern on a silicon substrate having a recess exposing a tunnel region of the silicon substrate; (S2) forming a bottom oxide layer, a nitride layer, a top oxide layer covering the recess and the pad oxide pattern to form a first ONO structure; (S3) forming a photoresist on the first ONO structure covering the recess and a peripheral region of the pad oxide pattern; (S4) removing a part of the first ONO structure exposed by the photoresist to form an U-shaped ONO structure; (S5) trimming the photoresist to exposed a part of the U-shaped ONO structure above the recess; (S6) removing the part of the U-shaped ONO structure; (S7) removing the photoresist; (S8) removing the pad oxide pattern and the top oxide layer; and (S9) forming a gate structure.
    Type: Grant
    Filed: January 12, 2016
    Date of Patent: October 11, 2016
    Assignee: UNITED MICROELECTRONICS CORPORATION
    Inventors: Kuo-Lung Li, Ping-Chia Shih, Hsiang-Chen Lee, Yu-Chun Chang, Chia-Wen Wang, Meng-Chun Chen, Chih-Yang Hsu
  • Patent number: 9412443
    Abstract: According to one embodiment, a processor system includes a variable capacity memory. The memory includes a memory cell array including basic units, each of the basic units including one cell transistor and one variable resistance element, a mode selector switching between first and second modes, a read/write of one bit executed in 2n basic units (n is an integer) among the basic units in the first mode, the read/write of the one bit executed in 2m basic units (m is an integer, m?n) among the basic units in the second mode, and a control circuit which controls the switching between the first and second modes.
    Type: Grant
    Filed: March 12, 2014
    Date of Patent: August 9, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hiroki Noguchi, Shinobu Fujita, Keiko Abe
  • Patent number: 9330922
    Abstract: A stack gate structure for a non-volatile memory array has a semiconductor substrate having a plurality of substantially parallel spaced apart active regions, with each active region having an axis in a first direction. A first insulating material is between each stack gate structure in the second direction perpendicular to the first direction. Each stack gate structure has a second insulating material over the active region, a charge holding gate over the second insulating material, a third insulating material over the charge holding gate, and a first portion of a control gate over the third insulating material. A second portion of the control gate is over the first portion of the control gate and over the first insulating material adjacent thereto and extending in the second direction. A fourth insulating material is over the second portion of the control gate.
    Type: Grant
    Filed: March 7, 2012
    Date of Patent: May 3, 2016
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Willem-Jan Toren, Xian Liu, Gerhard Metzger-Brueckl, Nhan Do, Stephan Wege, Nadia Miridi, Chien-Sheng Su, Cecile Bernardi, Liz Cuevas, Florence Guyot, Yueh-Hsin Chen, Henry Om'mani, Mandana Tadayoni
  • Patent number: 9312139
    Abstract: A semiconductor element and a manufacturing method of the same are provided. The semiconductor element includes a substrate, a plurality of doping strips, a memory material layer, a plurality of conductive damascene structures, and a dielectric structure. The doping strips are formed in the substrate. The memory material layer is formed on the substrate, and the memory material layer comprises a memory area located on two sides of the doping strips. The conductive damascene structures are formed on the memory material layer. The dielectric structure is formed on the doping strips and between the conductive damascene structures. The conductive damascene structures are extended in a direction perpendicular to a direction which the doping strips are extended in.
    Type: Grant
    Filed: May 10, 2013
    Date of Patent: April 12, 2016
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Ching-Hung Wang, Jyun-Siang Huang, Chien-Hung Liu, Chia-Wen Cheng, Ying-Tso Chen
  • Patent number: 8945997
    Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. An exemplary method for fabricating an integrated circuit having a split-gate nonvolatile memory device includes forming a charge storage structure overlying a semiconductor substrate and having a first sidewall and a second sidewall and forming an interior cavity. The method forms a control gate in the interior cavity. Further, the method forms a first select gate overlying the semiconductor substrate and adjacent the first sidewall. A first memory cell is formed by the control gate and the first select gate. The method also forms a second select gate overlying the semiconductor substrate and adjacent the second sidewall. A second memory cell is formed by the control gate and the second select gate.
    Type: Grant
    Filed: June 27, 2013
    Date of Patent: February 3, 2015
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Zufa Zhang, Khee Yong Lim, Elgin Quek
  • Patent number: 8916432
    Abstract: Methods of forming memory cells including non-volatile memory (NVM) and MOS transistors are described. In one embodiment the method includes: depositing and patterning a gate layer over a dielectric stack on a substrate to form a gate of a NVM transistor, the dielectric stack including a tunneling layer overlying a surface of the substrate, a charge-trapping layer overlying the tunneling layer and a blocking layer overlying the charge-trapping layer; forming a mask exposing source and drain (S/D) regions of the NVM transistor; etching the dielectric stack through the mask to thin the dielectric stack by removing the blocking layer and at least a first portion of the charge-trapping layer in S/D regions of the NVM transistor; and implanting dopants into S/D regions of the NVM transistor through the thinned dielectric stack to form a lightly-doped drain adjacent to the gate of the NVM transistor.
    Type: Grant
    Filed: June 16, 2014
    Date of Patent: December 23, 2014
    Assignee: Cypress Semiconductor Corporation
    Inventors: Krishnaswamy Ramkumar, Venkatraman Prabhakar
  • Patent number: 8895386
    Abstract: A method of forming a semiconductor structure is provided. A substrate having a cell area and a periphery area is provided. An oxide material layer and a first conductive material layer are sequentially formed on the substrate in the cell and periphery areas. A patterning step is performed to form first and second stacked structures on the substrate respectively in the cell and periphery areas. First and second spacers are formed respectively on sidewalls of the first and second stacked structures. At least two first doped regions are formed in the substrate beside the first stacked structure, and two second doped regions are formed in the substrate beside the second stacked structure. A dielectric layer and a second conductive layer are formed at least on the first stacked structure. The first stacked structure, the dielectric layer, and the second conductive layer in the cell area constitute a charge storage structure.
    Type: Grant
    Filed: October 1, 2012
    Date of Patent: November 25, 2014
    Assignee: Maxchip Electronics Corp.
    Inventors: Chen-Chiu Hsu, Tung-Ming Lai, Kai-An Hsueh, Ming-De Huang
  • Patent number: 8878278
    Abstract: A NAND device has at least a 3×3 array of vertical NAND strings in which the control gate electrodes are continuous in the array and do not have an air gap or a dielectric filled trench in the array. The NAND device is formed by first forming a lower select gate level having separated lower select gates, then forming plural memory device levels containing a plurality of NAND string portions, and then forming an upper select gate level over the memory device levels having separated upper select gates.
    Type: Grant
    Filed: January 30, 2013
    Date of Patent: November 4, 2014
    Assignee: Sandisk Technologies Inc.
    Inventors: Johann Alsmeier, Raghuveer S. Makala, Xiying Costa, Yanli Zhang
  • Patent number: 8872255
    Abstract: A semiconductor device includes a region in a semiconductor substrate having a top surface with a first charge storage layer on the top surface. A first conductive line is on the first charge storage layer. A second charge storage layer is on the top surface. A second conductive line is on the second charge storage layer. A third charge storage layer is on the top surface. A third conductive line is on the third charge storage layer. A fourth charge storage layer has a first side adjoining a first sidewall of the first conductive line and a second side adjoining a first sidewall of the second conductive line. A fifth charge storage layer has a first side adjoining a second sidewall of the second conductive line and a second side adjoining a first sidewall of the third conductive line. Source and drain regions are formed in the substrate on either side of the semiconductor device.
    Type: Grant
    Filed: January 21, 2014
    Date of Patent: October 28, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Mark D. Hall, Mehul D. Shroff
  • Patent number: 8815681
    Abstract: Nonvolatile memory devices and methods of forming the same are provided, the nonvolatile memory devices may include first regions and second regions which extend in a first direction and are alternately disposed in a semiconductor substrate along a second direction crossing the first direction. Buried doped lines are formed at the first regions respectively and extend in the first direction. The buried doped lines may be doped with a dopant of a first conductivity type. Bulk regions doped with a dopant of a second conductivity type and device isolation patterns are disposed along the second direction. The bulk regions and the device isolation patterns may be formed in the second regions. Word lines crossing the buried doped lines and the bulk regions are formed parallel to one another. Contact structures are connected to the buried doped lines and disposed between the device isolation patterns.
    Type: Grant
    Filed: November 16, 2012
    Date of Patent: August 26, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yongsik Jeong, Jeonguk Han, Weonho Park, Byungsup Shim
  • Patent number: 8809938
    Abstract: Three dimensional semiconductor memory devices are provided. The three dimensional semiconductor memory device includes a first stacked structure and a second stacked structure sequentially stacked on a substrate. The first stacked structure includes first insulating patterns and first gate patterns which are alternately and repeatedly stacked on a substrate, and the second stacked structure includes second insulating patterns and second gate patterns which are alternately and repeatedly stacked on the first stacked structure. A plurality of first vertical active patterns penetrate the first stacked structure, and a plurality of second vertical active patterns penetrate the second stacked structure. The number of the first vertical active patterns is greater than the number of the second vertical active patterns.
    Type: Grant
    Filed: September 9, 2011
    Date of Patent: August 19, 2014
    Assignee: Samsung Electronics Co., Ltd
    Inventors: Sung-Min Hwang, Hansoo Kim, Changseok Kang, Wonseok Cho, Jae-Joo Shim
  • Patent number: 8803216
    Abstract: A memory cell system including providing a substrate, forming a charge-storing stack having silicon-rich nitride on the substrate, and forming a gate on the charge-storing stack.
    Type: Grant
    Filed: March 20, 2006
    Date of Patent: August 12, 2014
    Assignees: Spansion, LLC, Advanced Micro Devices, Inc.
    Inventors: Meng Ding, Lei Xue, Mark Randolph, Chi Chang, Robert Bertram Ogle, Jr.
  • Patent number: 8779495
    Abstract: An integrated circuit includes a first SONOS memory cell and a second SONOS memory cell. The second memory cell is stacked on the first memory cell.
    Type: Grant
    Filed: April 19, 2007
    Date of Patent: July 15, 2014
    Assignee: Qimonda AG
    Inventors: Thomas Happ, Jan Boris Philipp
  • Patent number: 8779500
    Abstract: A memory device is provided, including a substrate, a conductive layer, a charge storage layer, a plurality of isolation structures, a plurality of first doped regions, and a plurality of second doped regions. The substrate has a plurality of trenches. The conductive layer is disposed on the substrate and fills the trenches. The charge storage layer is disposed between the substrate and the conductive layer. The isolation structures are disposed in the substrate between two adjacent trenches, respectively. The first doped regions are disposed in an upper portion of the substrate between each isolation structure and each trench, respectively. The second doped regions are disposed in the substrate under a bottom portion of the trenches, in which each isolation structure is disposed between two adjacent second doped regions.
    Type: Grant
    Filed: January 22, 2010
    Date of Patent: July 15, 2014
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Yu-Fong Huang, Miao-Chih Hsu, Kuan-Fu Chen, Tzung-Ting Han
  • Patent number: 8779502
    Abstract: According to one embodiment, a nonvolatile semiconductor memory includes first to n-th (n is a natural number not less than 2) semiconductor layers in a first direction and extend in a second direction, and the semiconductor layers having a stair case pattern in a first end of the second direction, a common semiconductor layer connected to the first to n-th semiconductor layers commonly in the first end of the second direction, first to n-th layer select transistors which are provided in order from the first electrode side between the first electrode and the first to n-th memory strings, and first to n-th impurity regions which make the i-th layer select transistor (i is one of 1 to n) a normally-on state in the first end of the second direction of the i-th semiconductor layer.
    Type: Grant
    Filed: December 12, 2011
    Date of Patent: July 15, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kiwamu Sakuma, Atsuhiro Kinoshita, Masahiro Kiyotoshi, Daisuke Hagishima, Koichi Muraoka
  • Patent number: 8772753
    Abstract: A nonvolatile semiconductor storage device includes a word line, a first electrode, a high resistance ion diffusion layer, a second electrode, and a bit line. The word line is made of a conductive material extending in a first direction. The first electrode is provided on the word line. The high resistance ion diffusion layer is provided on the first electrode. The second electrode is provided on the ion diffusion layer and configured to supply a metal into the ion diffusion layer upon application of a positive voltage relative to the first electrode. The bit line is provided on the second electrode and made of a conductive material extending in a second direction orthogonal to the first direction. The ion diffusion layer contains oxygen at a higher concentration on the word line side than on the bit line side.
    Type: Grant
    Filed: August 28, 2012
    Date of Patent: July 8, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Masanobu Baba
  • Patent number: 8772852
    Abstract: Provided is a nonvolatile memory device including a common source. The device includes a first active region crossing a second active region, a common source disposed in the second active region, and a source conductive line disposed on the common source in parallel to the common source. The source conductive line is electrically connected to the common source.
    Type: Grant
    Filed: December 4, 2008
    Date of Patent: July 8, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hong-Soo Kim, Keon-Soo Kim
  • Patent number: 8759896
    Abstract: There is provided a non-volatile semiconductor memory having a charge accumulation layer of a configuration where a metal oxide with a dielectric constant sufficiently higher than a silicon nitride, e.g., a Ti oxide, a Zr oxide, or a Hf oxide, is used as a base material and an appropriate amount of a high-valence substance whose valence is increased two levels or more (a VI-valence) is added to produce a trap level that enables entrance and exit of electrons with respect to the base material.
    Type: Grant
    Filed: October 31, 2012
    Date of Patent: June 24, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsuo Shimizu, Koichi Muraoka
  • Patent number: 8748972
    Abstract: Flash memory devices and methods for fabricating the same are provided. In accordance with an exemplary embodiment of the invention, a method for fabricating a memory device comprises the steps of fabricating a first gate stack and a second gate stack overlying a substrate. A trench is etched into the substrate between the first gate stack and the second gate stack and a first impurity doped region is formed within the substrate underlying the trench. The trench is filled at least partially with a conductive material.
    Type: Grant
    Filed: June 18, 2013
    Date of Patent: June 10, 2014
    Assignee: Spansion LLC
    Inventors: Ning Cheng, Fred Cheung, Ashot Melik-Martirosian, Kyunghoon Min, Michael Brennan, Hiroyuki Kinoshita
  • Patent number: 8748256
    Abstract: A method for forming an integrated circuit (IC) including a silicide block poly resistor (SIBLK poly resistor) includes forming a dielectric isolation region in a top semiconductor surface of a substrate. A polysilicon layer is formed including patterned resistor polysilicon on the dielectric isolation region and gate polysilicon on the top semiconductor surface. Implanting is performed using a first shared metal-oxide-semiconductor (MOS)/resistor polysilicon implant level for simultaneously implanting the patterned resistor polysilicon and gate polysilicon of a MOS transistor with at least a first dopant. Implanting is then performed using a second shared MOS/resistor polysilicon implant level for simultaneously implanting the patterned resistor polysilicon, gate polysilicon and source and drain regions of the MOS transistor with at least a second dopant. A metal silicide is formed on a first and second portion of a top surface of the patterned resistor polysilicon to form the SIBLK poly resistor.
    Type: Grant
    Filed: February 6, 2012
    Date of Patent: June 10, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Song Zhao, Gregory Charles Baldwin, Shashank S. Ekbote, Youn Sung Choi
  • Patent number: 8742481
    Abstract: Apparatuses, such as memory devices, memory cell strings, and electronic systems, and methods of forming such apparatuses are shown. One such apparatus includes a channel region that has a minority carrier lifetime that is lower at one or more end portions, than in a middle portion. Other apparatuses and methods are also disclosed.
    Type: Grant
    Filed: August 16, 2011
    Date of Patent: June 3, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Paolo Tessariol, Aurelio Giancarlo Mauri, Akira Goda, Yijie Zhao
  • Patent number: 8735945
    Abstract: A semiconductor device includes a transistor array including a plurality of transistors each having a gate electrode extended in a first direction, the plurality of transistors being arranged in a second direction intersecting the first direction, and a pad electrode arranged in the first direction of the transistor array and electrically connected to source regions of the plurality of transistors.
    Type: Grant
    Filed: September 2, 2011
    Date of Patent: May 27, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Masashi Shima, Kaoru Saigoh, Nobuhiro Misawa, Takao Sasaki
  • Patent number: 8723248
    Abstract: In one embodiment, there is provided a nonvolatile semiconductor storage device. The device includes: a plurality of nonvolatile memory cells. Each of the nonvolatile memory cells includes: a first semiconductor layer including a first source region, a first drain region, and a first channel region; a block insulating film formed on the first channel region; a charge storage layer formed on the block insulating film; a tunnel insulating film formed on the charge storage layer; a second semiconductor layer formed on the tunnel insulating film and including a second source region, a second drain region, and a second channel region. The second channel region is formed on the tunnel insulating film such that the tunnel insulating film is located between the second source region and the second drain region. A dopant impurity concentration of the first channel region is higher than that of the second channel region.
    Type: Grant
    Filed: February 24, 2012
    Date of Patent: May 13, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Naoki Yasuda, Jun Fujiki
  • Patent number: 8674414
    Abstract: Provided are three-dimensional nonvolatile memory devices and methods of fabricating the same. The memory devices include semiconductor pillars penetrating interlayer insulating layers and conductive layers alternately stacked on a substrate and electrically connected to the substrate and floating gates selectively interposed between the semiconductor pillars and the conductive layers. The floating gates are formed in recesses in the conductive layers.
    Type: Grant
    Filed: November 26, 2012
    Date of Patent: March 18, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byoungkeun Son, Hansoo Kim, Jinho Kim, Kihyun Kim
  • Patent number: 8669622
    Abstract: A non-volatile semiconductor device includes a memory cell in a first area of a substrate, a low voltage transistor in a second area of the substrate, and a high voltage transistor in a third area of the substrate. The memory cell includes a tunnel insulation layer formed on the substrate, a charge trapping layer pattern formed on the tunnel insulation layer in the first area of the substrate, a blocking layer pattern formed on the charge trapping layer pattern and a control gate formed on the blocking layer pattern. The control gate has a width substantially smaller than a width of the blocking layer pattern and the width of the control gate is substantially smaller than a width of the charge trapping layer pattern. In addition, an offset is formed between the control gate and the blocking layer pattern such that a spacer is not formed on a sidewall of the control gate.
    Type: Grant
    Filed: June 10, 2011
    Date of Patent: March 11, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hak-Sun Lee, Kyoung-Sub Shin
  • Patent number: 8669606
    Abstract: An embodiment of the invention includes a semiconductor device including a semiconductor substrate with a trench; a tunnel insulating film covering an inner surface of the trench; a trap layer in contact with the tunnel insulating film on an inner surface of an upper portion of the trench; a top insulating film in contact with the trap layer; a gate electrode embedded in the trench, and in contact with the tunnel insulating film at a lower portion of the trench and in contact with the top insulating film at the upper portion of the trench, in which the trap layer and the top insulating film, in between the lower portion of the trench and the upper portion of the trench, extend and protrude from both sides of the trench so as to be embedded in the gate electrode, and a method for manufacturing thereof.
    Type: Grant
    Filed: June 9, 2011
    Date of Patent: March 11, 2014
    Assignee: Spansion LLC
    Inventors: Fumiaki Toyama, Fumihiko Inoue
  • Patent number: 8653581
    Abstract: Memory devices having an increased effective channel length and/or improved TPD characteristics, and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line dielectrics between the memory cells. The memory cell contains a charge trapping dielectric stack, a poly gate, a pair of pocket implant regions, and a pair of bit lines. The bit line can be formed by an implant process at a higher energy level and/or a higher concentration of dopants without suffering device short channel roll off issues because spacers at bit line sidewalls constrain the implant in narrower implant regions.
    Type: Grant
    Filed: December 22, 2008
    Date of Patent: February 18, 2014
    Assignee: Spansion LLC
    Inventors: Ning Cheng, Huaqiang Wu, Hiro Kinoshita, Jihwan Choi, Angela Hui
  • Patent number: 8648404
    Abstract: A three-dimensional semiconductor device includes a semiconductor substrate, a plurality of conductive layers and insulating layers, and a plurality of contacts. The plurality of conductive layers and insulating layers are stacked alternately above the semiconductor substrate. The plurality of contacts extend in a stacking direction of the plurality of conductive layers and insulating layers. The plurality of conductive layers form a stepped portion having positions of ends of the plurality of conductive layers gradually shifted from an upper layer to a lower layer. The plurality of contacts are connected respectively to each of steps of the stepped portion. The stepped portion is formed such that, at least from an uppermost conductive layer to a certain conductive layer, the more upwardly the conductive layer is located, the broader a width of the step is.
    Type: Grant
    Filed: November 17, 2011
    Date of Patent: February 11, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Nikka Ko, Katsunori Yahashi
  • Patent number: 8633074
    Abstract: The present memory device includes a substrate, a tunneling layer over the substrate, a floating gate over the tunneling layer, a dielectric over the floating gate and including silicon oxynitride, and a control gate over the dielectric. A method for fabricating such a memory device is also provided, including various approaches for forming the silicon oxynitride.
    Type: Grant
    Filed: September 17, 2008
    Date of Patent: January 21, 2014
    Assignee: Spansion LLC
    Inventors: Minh Q. Tran, Minh-Van Ngo, Alexander H. Nickel, Jeong-Uk Huh
  • Patent number: 8629018
    Abstract: Some embodiments include NAND memory constructions. The constructions may contain semiconductor material pillars extending upwardly between dielectric regions, with individual pillars having a pair of opposing vertically-extending sides along a cross-section. First conductivity type regions may be along first sides of the pillars, and second conductivity type regions may be along second sides of the individual pillars; with the second conductivity type regions contacting interconnect lines. Vertical NAND strings may be over the pillars, and select devices may selectively couple the NAND strings with the interconnect lines. The select devices may have vertical channels directly against the semiconductor material pillars and directly against upper regions of the first and second conductivity type regions. Some embodiments include methods of forming NAND memory constructions.
    Type: Grant
    Filed: July 24, 2012
    Date of Patent: January 14, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Sanh D. Tang
  • Patent number: 8618603
    Abstract: A nonvolatile semiconductor memory device includes: a semiconductor member; a memory film provided on a surface of the semiconductor member and being capable of storing charge; and a plurality of control gate electrodes provided on the memory film, spaced from each other, and arranged along a direction parallel to the surface. Average dielectric constant of a material interposed between one of the control gate electrodes and a portion of the semiconductor member located immediately below the control gate electrode adjacent to the one control gate electrode is lower than average dielectric constant of a material interposed between the one control gate electrode and a portion of the semiconductor member located immediately below the one control gate electrode.
    Type: Grant
    Filed: July 11, 2012
    Date of Patent: December 31, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshio Ozawa, Fumiki Aiso
  • Patent number: 8603878
    Abstract: In a vertical-type memory device and a method of manufacturing the vertical-type memory device, the vertical memory device includes an insulation layer pattern of a linear shape provided on a substrate, pillar-shaped single-crystalline semiconductor patterns provided on both sidewalls of the insulation layer pattern and transistors provided on a sidewall of each of the single-crystalline semiconductor patterns. The transistors are arranged in a vertical direction of the single-crystalline semiconductor pattern, and thus the memory device may be highly integrated.
    Type: Grant
    Filed: November 9, 2012
    Date of Patent: December 10, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-Hoon Son, Jong-Wook Lee, Jong-Hyuk Kang
  • Patent number: 8598644
    Abstract: A nonvolatile semiconductor storage device including a first transistor comprising a first gate electrode including a charge storage layer, an interelectrode insulating film, and a control electrode layer; a second transistor comprising a second gate electrode including a lower electrode, an upper electrode, and an upper silicide portion above the upper electrode; and a third transistor comprising a third gate electrode including a lower electrode, an upper electrode, and an upper silicide portion above the upper electrode; wherein the lower electrodes of the second and the third gate electrodes have a first side and a second side taken along a length direction of the second and the third gate electrodes, the lower electrodes of the second and the third gate electrodes including a lower silicide portion in which at least the first side of the lower electrodes are partially silicided.
    Type: Grant
    Filed: August 20, 2012
    Date of Patent: December 3, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Wataru Sakamoto
  • Patent number: 8592275
    Abstract: An object of the present invention is to provide a semiconductor device having a nonvolatile memory cell of a high operation speed and a high rewrite cycle and a nonvolatile memory cell of high reliability. In a split gate type nonvolatile memory in which memory gate electrodes are formed in the shape of sidewalls of control gate electrodes, it is possible to produce a memory chip having a memory of a high operation speed and a high rewrite cycle and a memory of high reliability at a low cost by jointly loading memory cells having different memory gate lengths in an identical chip.
    Type: Grant
    Filed: May 7, 2013
    Date of Patent: November 26, 2013
    Assignee: Renesas Electronics Corporation
    Inventor: Yoshiyuki Kawashima
  • Patent number: 8552489
    Abstract: A mold stack including alternating insulation layers and sacrificial layers is formed on a substrate. Vertical channel regions extending through the insulation layers and sacrificial layers of the mold stack are formed. Gate electrodes are formed between adjacent ones of the insulation layers and surrounding the vertical channel regions. The gate electrodes have a greater thickness at a first location near sidewalls of the insulation layers than at a second location further away from the sidewalls of the insulation layers.
    Type: Grant
    Filed: November 29, 2012
    Date of Patent: October 8, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Daehong Eom, Kyunghyun Kim, Kwangsu Kim, Jun-Youl Yang, Se-Ho Cha
  • Patent number: 8546867
    Abstract: A technique capable of improving the reliability of a non-volatile memory semiconductor device is provided and, in particular, a technique capable of supplying electricity without fail to a memory gate electrode of split gate transistor is provided. One end of an electricity supply line ESL is arranged over a terminal end TE1 and the other end thereof is arranged over a terminal end TE2, and further, the central portion of the electricity supply line ESL is arranged over a dummy part DMY. That is, the terminal end TE1, the terminal end TE2, and the dummy part DMY have substantially the same height, and therefore, most of the electricity supply line ESL arranged from over the terminal end TE1 to over the terminal end TE2 via the dummy part DMY is formed so as to have the same height.
    Type: Grant
    Filed: December 31, 2012
    Date of Patent: October 1, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Hiraku Chakihara, Tsutomu Okazaki
  • Patent number: 8541821
    Abstract: The invention provides a method of forming an electron memory storage device and the resulting device. The device comprises a gate structure which, in form, comprises a first gate insulating layer formed over a semiconductor substrate, a self-forming electron trapping layer of noble metal nano-crystals formed over the first gate insulating layer, a second gate insulating layer formed over the electron trapping layer, a gate electrode formed over the second gate insulating layer, and source and drain regions formed on opposite sides of the gate structure.
    Type: Grant
    Filed: September 16, 2011
    Date of Patent: September 24, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Shubneesh Batra, Gurtej Sandhu
  • Patent number: 8530307
    Abstract: There is provided a semiconductor device including bit lines (14) formed in a semiconductor substrate (10), insulating film lines (18) located on the bit lines (14) to successively run in a length direction of the bit lines (14), gate electrodes (16) located above the semiconductor substrate (10) between the bit lines (14), and word lines (20) located on the gate electrodes (18) to run in a width direction of the bit lines (14), a trench region (22) formed between the bit lines (14) and the between word lines (20) in the semiconductor substrate, and there is also provided a fabrication method therefor. According to the present invention, it is possible to provide a semiconductor device where elements can be isolated between the word lines (14) and memory cells can be miniaturized, and to provide a fabrication method therefor.
    Type: Grant
    Filed: December 21, 2010
    Date of Patent: September 10, 2013
    Assignee: Spansion LLC
    Inventor: Masaya Hosaka