Abstract: Exposed are a semiconductor device and method of fabricating the same. The device includes an insulation film that is disposed between an active pattern and a substrate, which provides various improvements. This structure enhances the efficiency of high integration and offers an advanced structure for semiconductor devices.

Abstract: The semiconductor device comprises a silicon substrate 14 having a step formed in the surface which makes the surface in a flash memory cell region 10 lower than the surface in a peripheral circuit region 12; a device isolation region 20a formed in a trench 18 in the flash memory cell region 10; a device isolation region 20c formed in a trench 24 deeper than the trench 18 in the peripheral circuit region 12; a flash memory cell 46 including a floating gate 32 and a control gate 40 formed on the device region defined by the device isolation region 20a; and transistors 62, 66 formed on the device regions defined by the device isolation region 20c.

Abstract: A method is provided for fabricating a semiconductor device having a gate electrode overlying a gate insulator. The method, in accordance with one embodiment, comprises depositing a layer of spin on glass overlying the gate electrode, the layer of spin on glass comprising a substantially UV opaque material. The layer of spin on glass is heated to a temperature less than about 450° C., and all subsequent process steps in the fabrication of the device are limited to temperatures less than about 450° C.

Abstract: A semiconductor device having a first semiconductor region and second semiconductor region including impurities formed on an insulating layer formed on a semiconductor substrate, an insulator formed between the first semiconductor region and the second semiconductor region, a first impurity diffusion control film formed on the first semiconductor region and a second impurity diffusion control film formed on the second semiconductor region, a channel layer formed on the first impurity diffusion control film and second impurity diffusion film to cross at right angles with a direction where the first semiconductor region and the second semiconductor region are extended, a gate insulating film formed on the channel layer and a gate electrode formed on the gate insulating layer.

Abstract: A vertical channel transistor structure is provided. The structure includes a substrate, a channel, a cap layer, a charge trapping layer, a source and a drain. The channel is formed in a fin-shaped structure protruding from the substrate. The cap layer is deposited on the fin-shaped structure. The cap layer and the fin-shaped structure have substantially the same width. The charge trapping layer is deposited on the cap layer and on two vertical surfaces of the fin-shaped structure. The gate is deposited on the charge trapping layer and on two vertical surfaces of the fin-shaped structure. The source and the drain are respectively positioned on two sides of the fin-shaped structure and opposite the gate.

Abstract: A semiconductor process and apparatus are disclosed for forming a split-gate thin film storage NVM device (10) by forming a select gate structure (3) on a first dielectric layer (2) over a substrate (1); forming a control gate structure (6) on a second dielectric layer (5) having embedded nanocrystals (15, 16) so that the control gate (6) is adjacent to the select gate structure (3) but separated therefrom by a gap (8); forming a floating doped region (4) in the substrate (1) below the gap (8) formed between the select gate structure and control gate structure; and forming source/drain regions (11, 12) in the substrate to define a channel region that includes the floating doped region (4).

Abstract: A method of manufacturing a nonvolatile semiconductor memory includes: forming an insulator structure on a semiconductor substrate in a first region; forming a first gate insulating film on the semiconductor substrate outside the first region; blanket depositing a first gate material film and etching-back the first gate material film to form a first gate electrode on the first gate insulating film lateral to the insulator structure; removing the insulator structure; blanket forming a second gate insulating film; blanket depositing a second gate material film and etching-back the second gate material film to form a second gate electrode on the second gate insulating film in the first region; and silicidation of upper surfaces of the first and second gate electrodes. Any one of the first and second gate insulating films is a charge trapping film.

Abstract: A semiconductor device includes: source/drain regions formed in a semiconductor substrate; a trapping film for storing information by accumulating charges, the trapping film being formed in a region on the semiconductor substrate which includes a region on a channel region between the source/drain regions; and gate electrodes formed on the trapping film. A silicon nitride film containing carbon is formed by low pressure CVD using an organic material so as to cover the gate electrodes and a part of the trapping film which is located between adjacent gate electrodes.

Abstract: Manufacturing of a charge trap type memory device can include forming a tunnel insulating layer on a substrate. A charge-trapping layer can be formed on the tunnel insulating layer. A blocking layer can be formed on the charge-trapping layer. Gate electrodes can be formed on the blocking layer and divided by a trench. A portion of the charge-trapping layer aligned with the trench may be converted into a charge-blocking pattern with a vertical side profile by an anisotropic oxidation process.

Abstract: Nanocrystals are formed over an insulating layer by depositing a semiconductor layer over the insulating layer. The semiconductor layer is annealed to form a plurality of globules from the semiconductor layer. The globules are annealed using oxygen. Semiconductor material is deposited on the plurality of globules to add semiconductor material to the globules. After depositing the semiconductor material, the globules are annealed to form the nanocrystals. The nanocrystals can then be used in a storage layer of a non-volatile memory cell, especially a split-gate non-volatile memory cell having a select gate over the nanocrystals and a control gate adjacent to the select gate.

Abstract: A semiconductor device includes: a stacked body with a plurality of conductive layers and a plurality of dielectric layers alternately stacked therein, the stacked body including a staircase structure having the plurality of conductive layers processed into a staircase shape; an interlayer dielectric layer covering the staircase structure; and a contact electrode provided inside a contact hole penetrating through the interlayer dielectric layer, the contact hole penetrating through one of the staircase-shaped conductive layers, the contact electrode being in contact with a sidewall portion of the one of the staircase-shaped conductive layers exposed into the contact hole.

Abstract: An embodiment of a semiconductor device includes a substrate including a cell region and a peripheral region; a cell gate pattern on the cell region; and a peripheral gate pattern on the peripheral region, wherein a first cell insulation layer, a second cell insulation layer, and a third cell insulation layer may be between the substrate and the cell gate pattern, a first peripheral insulation layer, a second peripheral insulation layer, and a third peripheral insulation layer may be between the substrate and the peripheral gate pattern, and the second cell insulation layer and the third cell insulation layer include the same material as the respective second peripheral insulation layer and third peripheral insulation layer.

Abstract: A nonvolatile semiconductor memory device includes bit line diffusion layers extending along the X direction in an upper portion of a semiconductor substrate; and gate structures extending along the Y direction on the semiconductor substrate and each including a charge trapping film and a gate electrode. The nonvolatile semiconductor memory device further includes a first interlayer insulating film in which first contacts respectively connected to the bit line diffusion layers are formed; and second contacts that penetrate through a UV blocking film and a second interlayer insulating film formed on the first interlayer insulating film and have bottom faces respectively in contact with the first contacts and top faces respectively in contact with metal interconnections.

Abstract: Methods of forming a non-volatile memory device may include forming a tunnel insulating layer on a semiconductor substrate and forming a charge-trap layer on the tunnel insulating layer. A trench may then be formed extending through the tunnel insulating layer and the charge-trap layer and into the semiconductor substrate so that portions of the charge-trap layer and the tunnel insulating layers remain on opposite sides of the trench. A device isolation layer may be formed in the trench, and a blocking insulating layer may be formed on the device isolation layer and on remaining portions of the charge-trap layer. A gate electrode may be formed on the blocking insulating layer, and the blocking insulating layer and remaining portions of the charge-trap layer may be patterned to provide a blocking insulating pattern and a charge-trap pattern between the gate electrode and the semiconductor substrate.

Abstract: Dual storage node memory devices and methods for fabricating dual storage node memory devices have been provided. In accordance with an exemplary embodiment, a method includes the steps of etching a plurality of trenches in a semiconductor substrate and forming a layered structure within the trenches. The layered structure includes a tunnel dielectric layer and a charge storage layer. Bit lines are formed within the semiconductor substrate and a layer of conductive material is deposited overlying the layered structure.

Abstract: A memory string comprises: a first semiconductor layer having a plurality of columnar portions extending in a perpendicular direction with respect to a substrate, and joining portions joining lower ends of the plurality of columnar portions; a charge storage layer surrounding a side surface of the first semiconductor layer; and a first conductive layer surrounding a side surface of the charge storage layer and functioning as a control electrode of memory cells. A select transistor comprises: a second semiconductor layer extending upwardly from an upper surface of the columnar portions; an insulating layer surrounding a side surface of the second semiconductor layer; a second conductive layer surrounding a side surface of the insulating layer and functioning as a control electrode of the select transistors; and a third semiconductor layer formed on an upper surface of the second semiconductor layer and including silicon germanium.

Abstract: A plurality of a first conductive layers are provided at a certain interval L in a vertical direction, with a dielectric sandwiched therebetween. The certain interval L is set so that the first dielectric has an equivalent oxide thickness DEOT that satisfies the following relation (1). Dsio2<DEOT<Dk??(1) Dsio2 denotes a thickness of the dielectric when the dielectric is composed of silicon oxide with a minimum thickness that can withstand a maximum voltage to be applied to the first conductive layers. Dk denotes such an equivalent oxide thickness of a first dielectric that provides the resistance value Rsio2. The resistance value Rsio2 being defined as a resistance value of the first semiconductor layer for each of the first conductive layers when the dielectric is composed of silicon oxide and has a film thickness of Dsio2.

Abstract: A method of forming a contact on a semiconductor device is provided. First, a substrate is provided. A plurality of gate structures defined by a plurality of word lines in a first direction, and a plurality of diffusion regions covered by a first dielectric layer in a second direction are provided over the substrate. The gate structures located underneath the word lines and isolated by the diffusion regions. Then, an etching stop layer is formed. The etching stop layer and the first dielectric layer have different etching selectivity. A second dielectric layer is formed over the substrate. Furthermore, a plurality of contact holes to the diffusion regions between the word lines are formed by using the etching stop layer as a self-aligned mask.

Abstract: A step is provided between a substrate surface of a select gate and a substrate surface of a memory gate. When the substrate surface of the select gate is lower than the substrate surface of the memory gate, electrons in a channel upon writing obliquely flow in the step portion. Even if the electrons obtain the energy required for passing a barrier during the oblique flow, the electron injection does not occur because electrons are away from the substrate surface. The injection can occur only on a drain region side from a position where the electrons reach the substrate surface. As a result, the injection of the electrons into a gap region is suppressed, so that the electron distribution comes close to the hole distribution. Therefore, variation in a threshold value upon information retention is suppressed, and information-retaining characteristics of a memory cell are improved.

Abstract: Non-volatile memory devices and arrays are described that facilitate the use of band-gap engineered gate stacks with asymmetric tunnel barriers in floating gate memory cells in NOR or NAND memory architectures that allow for direct tunneling programming and erase with electrons and holes, while maintaining high charge blocking barriers and deep carrier trapping sites for good charge retention. The direct tunneling program and erase capability reduces damage to the gate stack and the crystal lattice from high energy carriers, reducing write fatigue and leakage issues and enhancing device lifespan. Memory cells of the present invention also allow multiple bit storage in a single memory cell, and allow for programming and erase with reduced voltages. A positive voltage erase process via hole tunneling is also provided.

Abstract: A flash memory device and a method of manufacturing a flash memory device. A flash memory device may include an isolation layer and/or an active area over a semiconductor substrate, a memory gate formed over an active area, a control gate formed over a semiconductor substrate including a memory gate, and/or a common source line contact formed over a semiconductor substrate including a control gate. A flash memory device may include a source plate having substantially the same interval as an interval of an active area of a bit line. A source plate may include an active area in which a common source line contact may be formed. A common source line contact may include a long butting contact extending in a direction traversing an active area.

Abstract: The cell comprises a substrate having a drain region and a source region. An oxynitride layer is formed over the substrate. An embedded trap layer is formed over the oxynitride layer. An injector layer is formed over the embedded trap layer. A high dielectric constant layer is formed over the injector layer. A polysilicon control gate formed over the high dielectric constant layer. The cell can be formed in a planar architecture or a two element, split channel, three-dimensional device. The planar cell is formed with the high dielectric constant layer and the control gate being formed over and substantially around three sides of the embedded trap layer. The split channel device has a source line in the substrate under each trench and a bit line on either side of the trench.

Abstract: An object of the present invention is to provide a nonvolatile semiconductor storage device with a superior charge holding characteristic in which highly-efficient writing is possible at low voltage, and to provide a manufacturing method thereof. The nonvolatile semiconductor storage device includes a semiconductor film having a pair of impurity regions formed apart from each other and a channel formation region provided between the impurity regions; and a first insulating film, a charge accumulating layer, a second insulating film, and a conductive film functioning as a gate electrode layer which are provided over the channel formation region. In the nonvolatile semiconductor storage device, a second barrier formed by the first insulating film against a charge of the charge accumulating layer is higher in energy than a first barrier formed by the first insulating film against a charge of the semiconductor film.

Abstract: A flash memory device may include a device isolation layer and an active area formed over a semiconductor substrate, a memory gate formed over the active area, and a control gate formed over the semiconductor substrate including the memory gate, wherein the active area, where a source contact is to be formed, has the same interval spacing as a bit line, and a common source line area, where the source contact is to be formed, has an impurity area connecting neighboring active areas.

Abstract: A method for manufacturing a non-volatile memory device having a charge trap layer comprises in one embodiment: forming a first dielectric layer over a semiconductor substrate; forming a second dielectric layer having a higher dielectric constant than that of the first dielectric layer over the first dielectric layer; forming a nitride buffer layer for preventing an interfacial reaction over the second dielectric layer; forming a third dielectric layer by supplying a radical oxidation source onto the nitride buffer layer to oxidize the nitride buffer layer, thereby forming a tunneling layer comprising the first, second, and third dielectric layers; and forming a charge trap layer, a shielding layer, and a control gate electrode layer over the tunneling layer.

Abstract: Techniques are provided for fabricating memory with metal nanodots as charge-storing elements. In an example approach, a coupling layer such as an amino functional silane group is provided on a gate oxide layer on a substrate. The substrate is dip coated in a colloidal solution having metal nanodots, causing the nanodots to attach to sites in the coupling layer. The coupling layer is then dissolved such as by rinsing or nitrogen blow drying, leaving the nanodots on the gate oxide layer. The nanodots react with the coupling layer and become negatively charged and arranged in a uniform monolayer, repelling a deposition of an additional monolayer of nanodots. In a configuration using a control gate over a high-k dielectric floating gate which includes the nanodots, the control gates may be separated by etching while the floating gate dielectric extends uninterrupted since the nanodots are electrically isolated from one another.

Abstract: A nonvolatile semiconductor memory device includes a semiconductor layer as a channel, a conductive layer which is formed on a surface of the semiconductor layer with a first insulating layer and a second insulating layer interposed therebetween and functions as a control gate electrode; and a plurality of first charge storage layers formed between the first insulating layer and the second insulating layer. The plurality of first charge storage layers are formed in isolation from one another along a surface of the first insulating layer. The first insulating layer is formed so as to protrude towards the semiconductor layer at a position where each of the first charge storage layers is formed.

Abstract: In a method of fabricating a semiconductor device, an additive gas is mixed with an etching gas to reduce a fluorine ratio of the etching gas. The etching gas having a reduced fluorine rate is utilized in the process for etching a nitride layer formed on an oxide layer to prevent the oxide layer formed below the nitride layer from being etched along with the nitride layer. The method comprises primarily etching an exposed charge storage layer using an etching gas; and secondarily etching the charge storage layer using the etching gas under a condition that a ratio of fluorine contained in the etching gas utilized in the secondary etching step is less than a ratio of fluorine contained in the etching gas utilized in the primary etching step. Thus, the tunnel insulating layer formed below the charge storage layer is not damaged when the charge storage layer is patterned.

Abstract: In an example embodiment, a semiconductor substrate has a plurality of active regions separated by a plurality of trenches. A gate insulation film fills at least a portion of the trenches, and a conductive gate film is formed over the gate insulation film. In an example embodiment, the gate insulation film, may include a tunneling insulation film, a charge storage film, and a blocking insulation film. The example embodiment may also include field isolation films, which partially fill the trenches of the semiconductor substrate, such that the upper surfaces of the active regions or the substrate are higher than the upper surfaces of the field isolation films.

Abstract: A nonvolatile semiconductor memory device includes a first stacked body on a silicon substrate, and a second stacked body is provided thereon. The first stacked body includes a plurality of insulating films alternately stacked with a plurality of electrode films, and a first portion of a through-hole extending in a stacking direction is formed. The second stacked body includes a plurality of insulating films alternately stacked with a plurality of electrode films, and a second portion of the through-hole is formed. A memory film is formed on an inner face of the through-hole, and a silicon pillar is buried in an interior of the through-hole. A central axis of the second portion of the through-hole is shifted from a central axis of the first portion, and a lower end of the second portion is positioned lower than an upper portion of the first portion.

Abstract: A reduction of a resistance of a bit line of a memory cell array and a reduction of a forming area of the memory cell array are planed. Respective bit lines running at right angles to a word line are composed of a diffusion bit line formed in a semiconductor substrate and a linear metal bit line on an upper side of the diffusion bit line. The diffusion bit line is formed in a linear pattern on a lower side of the metal bit line in the same manner, and the metal bit line is connected with the diffusion bit line between the word lines. An interlayer insulating film is formed on the memory cell array, and the metal bit line is formed with being buried in it.

Abstract: Methods of forming charge-trapping dielectric layer structures in semiconductor memory devices which comprise: (a) providing a semiconductor substrate; (b) forming an oxide layer on at least a portion of the substrate; (c) forming two or more source/drain regions in the substrate below the oxide layer; (d) re-oxidizing the oxide layer; (e) forming a charge-trapping dielectric layer on the oxide layer; and (f) forming an insulating layer on the charge-trapping dielectric layer; as well as methods which comprise: (a) providing a semiconductor substrate; (b) forming an oxide layer on at least a portion of the substrate in a dry atmosphere; (c) forming two or more source/drain regions in the substrate below the oxide layer; (d) forming a charge-trapping dielectric layer on the oxide layer; (e) forming an insulating layer on the charge-trapping dielectric layer; and (f) annealing the insulating layer in an atmosphere having a hydrogen content of less than about 0.01% are described.

Abstract: A method includes forming a first layer of gate material over a semiconductor substrate; forming a hard mask layer over the first layer; forming an opening; forming a charge storage layer over the hard mask layer and within the opening; forming a second layer of gate material over the charge storage layer; removing a portion of the second layer and a portion of the charge storage layer which overlie the hard mask layer, wherein a second portion of the second layer remains within the opening; forming a patterned masking layer over the hard mask layer and over the second portion, wherein the patterned masking layer defines both a first and second bitcell; and forming the first and second bitcell using the patterned masking layer, wherein each of the first and second bitcell comprises a select gate made from the first layer and a control gate made from the second layer.

Abstract: A non-volatile memory device (e.g., a split gate type device) and a method of manufacturing the same are disclosed. The memory device includes an active region on a semiconductor substrate, a pair of floating gates above the active region, a charge storage insulation layer between each floating gate and the active region, a pair of wordlines over the active region and partially overlapping the floating gates, respectively, and a gate insulation film between each wordline and the active region. The method may prevent or reduce the incidence of conductive stringers on the active region between the floating gates, to thereby improve reliability of the memory devices and avoid the active region resistance from being increased due to the stringer.

Abstract: A memory cell array includes a number of memory cells, each of the memory cells including a source and a drain region defined by corresponding bitlines within a semiconductor substrate. Each of the bitlines has a doped semiconductor region as well as a conductive region in direct electrical contact with the doped semiconductor region.

Abstract: A nonvolatile memory device and a method of forming the nonvolatile memory device, the method including forming a tunnel insulating layer on a substrate, wherein forming the tunnel insulating layer includes forming a multi-element insulating layer by a process including sequentially supplying a first element source, a second element source, and a third element source to the substrate, forming a charge storage layer on the tunnel insulating layer, forming a blocking insulating layer on the charge storage layer, and forming a control gate electrode on the blocking insulating layer.

Abstract: Mask sets, layout design, and methods for forming contacts in devices are described. In one embodiment, a method of manufacturing a semiconductor device includes a exposing a first photo resist layer using a first light beam thereby forming first features. The first exposure is performed by the first light beam passing through a first dipole illuminator and then a first mask. A dipole axis of the first dipole illuminator is oriented in a first direction. After exposing the first photo resist layer, forming second features using a second exposure with a second light beam. The second exposure is performed by the second light beam passing through a second dipole illuminator and then a second mask. A dipole axis of the second dipole illuminator is oriented in a second direction. The first direction and the second direction are not perpendicular. The first and the second features comprise a pattern for forming contact holes.

Abstract: A non-volatile semiconductor memory device with good write/erase characteristics is provided. A selection gate is formed on a p-type well of a semiconductor substrate via a gate insulator, and a memory gate is formed on the p-type well via a laminated film composed of a silicon oxide film, a silicon nitride film, and a silicon oxide film. The memory gate is adjacent to the selection gate via the laminated film. In the regions on both sides of the selection gate and the memory gate in the p-type well, n-type impurity diffusion layers serving as the source and drain are formed. The region controlled by the selection gate and the region controlled by the memory gate located in the channel region between said impurity diffusion layers have the different charge densities of the impurity from each other.

Abstract: A method for fabricating a nonvolatile charge trap memory device is described. The method includes first forming a tunnel dielectric layer on a substrate in a first process chamber of a single-wafer cluster tool. A charge-trapping layer is then formed on the tunnel dielectric layer in a second process chamber of the single-wafer cluster tool. A top dielectric layer is then formed on the charge-trapping layer in the second or in a third process chamber of the single-wafer cluster tool.

Abstract: A method of forming at least a portion of a dual bit memory core array upon a semiconductor substrate, the method comprising performing front end processing, performing a first bitline implant, or pocket implants, or both into the first bitline spacings to establish buried first bitlines within the substrate, depositing a layer of the spacer material over the charge trapping dielectric and the polysilicon layer features, forming a sidewall spacer adjacent to the charge trapping dielectric and the polysilicon layer features to define second bitline spacings between adjacent memory cells, performing a deep arsenic implant into the second bitline spacings to establish a second bitline within the structure that is deeper than the first bit line, removing the sidewall spacers and performing back end processing.

Abstract: Provided is a method for fabricating a nonvolatile memory device capable of improving charge retention characteristics. The method for fabricating a nonvolatile memory device includes forming a charge trapping layer with a memory region and a charge blocking region on a semiconductor substrate, and trapping charges in the charge blocking region of the charge trapping layer.

Abstract: Methods are provided for fabricating a split charge storage node semiconductor memory device. In accordance with one embodiment the method comprises the steps of forming a gate insulator layer having a first physical thickness and a first effective oxide thickness on a semiconductor substrate and forming a control gate electrode having a first edge and a second edge overlying the gate insulator layer. The gate insulator layer is etched to form first and second undercut regions at the edges of the control gate electrode, the first and second undercut region each exposing a portion of the semiconductor substrate and an underside portion of the control gate electrode. First and second charge storage nodes are formed in the undercut regions, each of the charge storage nodes comprising an oxide-storage material-oxide structure having a physical thickness substantially equal to the first physical thickness and an effective oxide thickness less than the first effective oxide thickness.

Abstract: A method for fabricating a nonvolatile charge trap memory device is described. The method includes forming a first oxide layer on a surface of a substrate. The first oxide layer is exposed to a first decoupled plasma nitridation process having a first bias. Subsequently, a charge-trapping layer is formed on the first oxide layer. The charge-trapping layer is exposed to an oxidation process and then to a second decoupled plasma nitridation process having a second, different, bias.

Abstract: A semiconductor memory device includes a plurality of memory cell transistors each having a gate electrode section including a charge accumulation layer formed on a semiconductor substrate via a gate insulating film, a first insulating film formed using a material with a higher dielectric constant than the gate insulating film, a control gate, an impurity diffusion layer functioning as a source or a drain, and a plurality of barrier films formed on a side surface of the gate electrode section so as to cover a side surface of at least the first insulating film and formed between the first insulating film and the control gate. The device further includes a plurality of second insulating films formed on the semiconductor substrate and each formed between the gate electrode sections of adjacent ones of the plurality of memory cell transistors.

Abstract: To improve characteristics of a semiconductor device having a nonvolatile memory. There is provided a semiconductor device having a nonvolatile memory cell that performs memory operations by transferring a charge to/from a charge storage film, wherein the nonvolatile memory cell includes a p well formed in a principal plane of a silicon substrate, and a memory gate electrode formed over the principal plane across the charge storage film, and wherein a memory channel region located beneath the charge storage film of the principal plane of the silicon substrate contains fluorine.

Abstract: A semiconductor memory device and method of fabricating a semiconductor memory device, wherein a tunnel insulating layer, a first charge trap layer and an isolation mask layer are sequentially stacked over a semiconductor substrate in which a cell region and a peri region are defined. The isolation mask layer, the first charge trap layer, the tunnel insulating layer and the semiconductor substrate are etched to thereby form trenches. An isolation layer is formed within each trench. The first charge trap layer is exposed by removing the isolation mask layer formed in the cell region. A second charge trap layer is formed on the exposed first charge trap layer and the isolation layer. A blocking layer and a control gate are formed over the semiconductor substrate in which the second charge trap layer is formed.

Abstract: A method of forming a memory transistor includes providing a substrate comprising semiconductive material and forming spaced-apart source/drain structures. At least one of the source/drain structures forms a Schottky contact to the semiconductive material. The method also includes forming a memory gate between the spaced-apart source/drain structures and forming a control gate disposed operatively over the memory gate.

Abstract: A field-enhanced (FE) charge trapping-DRAM (TDRAM) device is described which is suitable for DRAM applications, and for additional applications with lower power requirements. In some embodiments, the FE-TDRAM device comprises a charge trapping FinFET structure including an upside-down U-shaped volatile programmable structure and an upside-down U-shaped dielectric structure overlying the volatile programmable structure.

Abstract: A memory array comprising vertical memory cells does not require any isolation layers between cells. Thus, a very compact, high density memory array can be achieved. Each memory cell in the memory array is configured to store 4 bits of data per cell. Multi level charge techniques can be used to increase the number of bit per cell and achieve further increased density for the memory array.

Abstract: A method of manufacturing a non-volatile memory device includes the steps of: defining an active region on a semiconductor substrate; forming a charge storage layer on the active region; forming a first conductive pattern on the charge storage layer, wherein the first conductive pattern has a bottom portion larger in width than a top portion thereof, the first conductive pattern further having a sloping sidewall connecting the top and bottom portions; forming an oxide layer on the sidewall of the first conductive pattern; forming a conformal second conductive layer on the first conductive pattern and on the active region around the first conductive pattern; and patterning the first conductive pattern and the second conductive layer to form a pair of first electrodes and a pair of second electrodes, respectively.