Abstract: A method of forming solder bumps on a substrate is disclosed. The method includes forming a plurality of contact points on the substrate. The method further includes depositing a layer of surface finish material on the plurality of contact points. Furthermore, the method includes disposing a plurality of solder balls on the layer of surface finish material. Each solder ball of the plurality of solder balls has conductive material including a solder alloy and Phosphorus. Thereafter, the method includes applying a solder reflow process to the plurality of solder balls to configure a plurality of solder bumps on the substrate layer. The concentration of the Phosphorus in the solder material is based on target performance characteristic of the substrate having the plurality of solder bumps.

Abstract: A printed circuit board and a flip chip package using the same are designed to minimize thermal stress due to different thermal coefficients present in areas having metal lines and solder resist versus other areas on the printed circuit board. The printed circuit board includes an insulation layer; a first metal line formed on one surface of the insulation layer and having at one end thereof a bump land and a projection which integrally extends from the bump land; a second metal line formed on the other surface of the insulation layer and having at one end thereof a ball land; a via metal line formed through the insulation layer to connect the first and second metal lines to each other; and solder resists formed on the upper and lower surfaces of the insulation layer to expose the bump land and the ball land.

Abstract: A method for electrically coupling an anti-tamper mesh to an electronic module or device using wire bonding equipment and a device made from the method. Stud bumps or free air ball bonds are electrically coupled to conductive mesh pads of an anti-tamper mesh. Respective module pads have a conductive epoxy disposed thereon for the receiving of the stud bumps or free air ball bonds, each of which are aligned and bonded together to electrically couple the anti-tamper mesh to predetermined module pads.

Abstract: A semiconductor device, includes a semiconductor substrate; and a solder bump part, which is formed on the semiconductor substrate and in which no grain boundary extends equal to or over ? of a diameter dimension of said solder bump part from an outer circumferential surface between an end of a connection part with the semiconductor substrate and a lateral portion.

Abstract: A memory module has an array of connections. The array of connections is arranged in rows and columns such that there are first and second outer columns. Connections in the first and second outer columns can be interchanged to optimize double-side module placement on a substrate. Other embodiments are also disclosed and claimed.

Abstract: A semiconductor device 100 has such a structure that a semiconductor chip 110 is flip-chip mounted on a wiring board 120. The wiring board 120 has a multilayer structure in which a plurality of wiring layers and a plurality of insulating layers are arranged, and has a structure in which insulating layers of a first layer 122, a second layer 124, a third layer 126 and a fourth layer 128 are provided. The first layer 122 has a first insulating layer 121 and a second insulating layer 123. A protruded portion 132 which is protruded in a radial direction (a circumferential direction) from an outer periphery at one surface side of a first electrode pad 130 is formed on a whole periphery over a boundary surface between the first insulating layer 121 and the second insulating layer 123.

Abstract: Systems and methods are disclosed that enable forming semiconductor chip connections. In one embodiment, the semiconductor chip includes a body having a polyhedron shape with a pair of opposing sides; and a solder member extending along a side that extends between the pair of opposing sides of the polyhedron shape.

Abstract: In one embodiment, a collar structure includes a non-conductive layer that relieves stress around the perimeter of each of the solder balls that connect the semiconductor die to the semiconductor chip package substrate, and another non-conductive layer placed underneath to passivate the entire surface of the die.

Abstract: A back of a dielectric transparent handle substrate is coated with a blanket conductive film or a mesh of conductive wires. A semiconductor substrate is attached to the transparent handle substrate employing an adhesive layer. The semiconductor substrate is thinned in the bonded structure to form a stack of the transparent handle substrate and the semiconductor interposer. The thinned bonded structure may be loaded into a processing chamber and electrostatically chucked employing the blanket conductive film or the mesh of conductive wires. The semiconductor interposer may be bonded to a semiconductor chip or a packaging substrate employing C4 bonding or intermetallic alloy bonding. Illumination of ultraviolet radiation to the adhesive layer is enabled, for example, by removal of the blanket conductive film or through the mesh so that the transparent handle substrate may be detached. The semiconductor interposer may then be bonded to a packaging substrate or a semiconductor chip.

Abstract: Various methods and apparatus for joining stacked substrates to a circuit board are disclosed. In one aspect, a method of manufacturing is provided that includes coupling plural substrates to form a stack. At least one of the plural substrates is a semiconductor chip. Plural conductive vias are formed in a first of the plural substrates. Each of the plural conductive vias includes a first end positioned in the first substrate and a second end projecting out of the first substrate.

Abstract: A mounting structure and a mounting method which are capable of securely electrically connecting wiring on a board and a device to each other in the case where the device is mounted on the board, and are capable of forming a finer bump, and increasing the number of pins are provided. A device includes at least one projection having a structure in which a surface of at least a tip part of a projecting section made of an elastic body is coated with a conductive film.

Abstract: A semiconductor package includes a wiring substrate, a semiconductor chip, and a conductor plate in order to reduce a voltage drop at the central portion of a chip caused by wiring resistance from a peripheral connection pad disposed on the periphery of the chip. Central electrode pads for use in ground/power-supply are disposed on the central portion of the chip. The conductor plate for use in ground/power-supply is disposed on the chip such that an insulating layer is disposed therebetween. The central electrode pads on the chip and the conductor plate are connected together by wire bonding through an opening formed in the insulating layer and the conductor plate. An extraction portion of the conductor plate is connected to a power-supply wiring pad on the wiring substrate. Preferably, the conductor plate is composed of a multilayer structure, and each conductor plate is used in power-supply wiring or ground wiring.

Abstract: A microcircuit article of manufacture comprises an electrical conductor electrically connected to both a first microcircuit element at a site comprising a first connector site having a first connector site axis and a second microcircuit element at a site comprising a second connector site having a second connector site axis. The first microcircuit element and the second microcircuit element are separated by and operatively associated with a layer comprising a first electrical insulator, whereas the conductor and the first microcircuit element are separated by and operatively associated with a layer comprising a second electrical insulator. At least one of the first electrical insulator layer and the second electrical insulator layer comprise a polymeric electrical insulator. In another embodiment, both electrical insulator layers comprise polymeric insulator layers. The microcircuit includes a UBM and solder connection to a FBEOL via opening.

Abstract: The present invention relates to a package structure, a packaging substrate and a chip. The package structure includes: a chip including a plurality of electrode pads on a surface thereof; a packaging substrate including a plurality of first conductive pads on a surface thereof; and a plurality of connecting units through which the electrode pads electrically communicate with the first conductive pads, in which the chip or the packaging substrate further includes a first surface finish layer over the electrode pads or the first conductive pads, and the first surface finish layer includes a Ni—Pd alloy layer. Accordingly, the surface finish method applied in a package structure, a packaging substrate and a chip has advantages of simple manufacture, low cost and high reliability.

Abstract: A BGA semiconductor device includes a semiconductor package and a mounting board mounting thereon the semiconductor package, wherein an array of signal electrodes of the semiconductor package and an array of signal electrodes of the mounting board are coupled together via signal bumps. The BGA semiconductor device also includes a dummy bump, which reinforces the bending strength of the BGA semiconductor device and is broken by a shearing force caused by thermal expansion to alleviate the stress for the signal bumps.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a pillar ball; mounting an interposer having a first functional side and a second functional side over the pillar ball and a semiconductor chip; encapsulating the interposer, the pillar ball, and the semiconductor chip with an encapsulation; forming a via through the first functional side and the second functional side of the interposer, and through the encapsulation to expose a portion of the pillar ball; and filling the via with a pillar post.

Abstract: An embedded wafer level ball grid array (eWLB) is formed by embedding a semiconductor die in a molding compound. A trench is formed in the molding compound with a laser drill. A first layer of copper is deposited on the sidewall of the trench by physical vapor deposition. A second layer of copper is then formed on the first layer of copper by an electroless process. A third layer of copper is then formed on the second layer by electroplating.

Abstract: An embedded wafer level ball grid array (eWLB) is formed by embedding a semiconductor die in a molding compound. A trench is formed in the molding compound with a laser drill. A first layer of copper is deposited on the sidewall of the trench by physical vapor deposition. A second layer of copper is then formed on the first layer of copper by an electroless process. A third layer of copper is then formed on the second layer by electroplating.

Abstract: A chip package structure includes a silicon substrate, a sensing component, a metal circuit layer, a first insulating layer and a conductive metal layer. The silicon substrate has opposite first and second surfaces. The sensing component is disposed on the first surface. The metal circuit layer is disposed on the first surface and electrically connected to the sensing component. The first insulating layer covers the second surface and has a first through hole to expose a portion of the second surface. The conductive metal layer is disposed on the first insulating layer and includes first leads and a second lead. The first leads are electrically connected to the metal circuit layer. The second lead is filled in the first through hole to electrically connect to the silicon substrate and one of the first leads. A chip packaging process for fabricating the chip package structure is also provided.

Abstract: Methods for localized thinning of wafers used in semiconductor devices and the structures formed from such methods are described. The methods thin localized areas of the backside of the semiconductor wafer to form recesses with a bi-directional channel design that is repeated within the wafer (or die) so that no straight channel line crosses the wafer (or die). The bi-directional pattern design keeps the channels from being aligned with the crystal orientation of the wafer. The recesses are then filled by a solder ball drop process by dropping proper size solder balls into the recesses and then annealing the wafer to reflow the solder balls and flatten them out. The reflow process begins to fill in the recesses from the bottom up, thereby avoiding void formation and the resulting air traps in the reflowed solder material. Other embodiments are also described.

Abstract: An electrical interconnect including a first circuitry layer with a first surface and a second surface. At least a first dielectric layer is printed on the first surface of the first circuitry layer to include a plurality of first recesses. A conductive material is deposited in a plurality of the first recesses to form a plurality of first conductive pillars electrically coupled to, and extending generally perpendicular to, the first circuitry layer. At least a second dielectric layer is printed on the first dielectric layer to include a plurality of second recesses generally aligned with a plurality of the first conductive pillars. A conductive material is deposited in a plurality of the second recesses to form a plurality of second conductive pillars electrically coupled to, and extending parallel the first conductive pillars.

Abstract: A method of fabricating a bonding structure having compliant bumps includes first providing a first substrate and a second substrate. The first substrate includes first bonding pads. The second substrate is disposed on one side of the first substrate and includes second bonding pads and compliant bumps disposed thereon. The second bonding pads are opposite to the first bonding pads. Next, a non-conductive adhesive layer and ball-shaped spacers are formed between the first and the second substrates. Finally, the first substrate, the non-conductive adhesive layer, and the second substrate are compressed, such that the compliant bumps on the second bonding pads of the second substrate pass through the non-conductive adhesive layer and are electrically connected to the first bonding pads of the first substrate, respectively. The ball-shaped spacers are distributed in the non-conductive adhesive layer sandwiched between the first and the second substrates for maintaining the gap therebetween.

Abstract: A method includes performing a first die-saw on a package structure includes forming a first and a second metal lead extending into a trench of a package structure, wherein the first and the second metal leads contact the side edges of contact pads that are in devices in the package structure. The first and the second metal leads are interconnected through a connecting metal portion. A pre-cut is performed to cut the connecting metal portion to separate the first and the second metal leads, wherein remaining portions of the connecting metal portion have edges after the pre-cut. A dielectric coating is formed over the first and the second metal leads. A die-saw is performed to saw apart the package structure, so that the first and the second dies are separated into separate piece. In each of the resulting pieces, the edges of the remaining portions of the connecting metal portion are covered by remaining portions of the first dielectric coating.

Abstract: Flow diverting structures for preferentially impeding, redirecting or both impeding and redirecting the flow of flowable encapsulant material, such as molding compound, proximate a selected surface or surfaces of a semiconductor die or dice during encapsulation are disclosed. Flow diverting structures may be included in or associated with one or more portions of a lead frame, such as a paddle, tie bars, or lead fingers. Flow diverting structures may also be inserted into a mold in association with semiconductor dice carried on non-lead frame substrates, such as interposers and circuit boards, to preferentially impede, redirect or both impede and redirect the flow of molding compound flowing between and over the semiconductor dice.

Abstract: Disclosed are embodiments of a lower integrated circuit (IC) package structure for a package-on-package (PoP) assembly. The lower IC package structure includes an interposer having pads to mate with terminals of an upper IC package. An encapsulant material is disposed in the lower IC package, and this encapsulant may be disposed proximate one or more IC die. An upper IC package may be coupled with the lower IC package to form a PoP assembly. Such a PoP assembly may be disposed on a mainboard or other circuit board, and may form part of a computing system. Other embodiments are described and claimed.

Abstract: Miniaturization and high-performance of a semiconductor device are promoted, which has a package on package (POP) structure in which a plurality of semiconductor packages is stacked in a multistage manner. A testing conductive pad for determining the quality of a conduction state of a microcomputer chip and a memory chip is arranged outside a conductive pad for external input/output and thereby the route of a wire that couples the microcomputer chip and the memory chip to the testing conductive pad is reduced in length. Further, the wire that couples the microcomputer chip and the memory chip to the testing conductive pad is coupled to a pad in the outer row among conductive pads in two rows to be coupled to the microcomputer chip.

Abstract: An integrated circuit structure includes a semiconductor substrate, and an active device formed at a front surface of the semiconductor substrate. A bond pad is over the front surface of the semiconductor substrate. The bond pad has a first dimension in a first direction parallel to the front surface of the semiconductor substrate. A bump ball is over the bond pad, wherein the bump ball has a diameter in the first direction, and wherein an enclosure of the first dimension and the diameter is greater than about ?1 ?m.

Abstract: Solder bump connections and methods for fabricating solder bump connections. The method includes forming a layer stack containing first and second conductive layers, forming a dielectric passivation layer on a top surface of the second conductive layer, and forming a via opening extending through the dielectric passivation layer to the top surface of the second conductive layer. The method further includes forming a conductive plug in the via opening. The solder bump connection includes first and second conductive layers comprised of different conductors, a dielectric passivation layer on a top surface of the second conductive layer, a via opening extending through the dielectric passivation layer to the top surface of the second conductive layer, and a conductive plug in the via opening.

Abstract: Described herein are stackable semiconductor device packages and related stacked package assemblies and methods. In one embodiment, a manufacturing method includes: (1) providing a substrate including contact pads disposed adjacent to an upper surface of the substrate; (2) applying an electrically conductive material to form conductive bumps disposed adjacent to respective ones of the contact pads; (3) electrically connecting a semiconductor device to the upper surface of the substrate; (4) applying a molding material to form a molded structure covering the conductive bumps and the semiconductor device; (5) forming a set of cutting slits extending partially through the molded structure and the conductive bumps to form truncated conductive bumps; and (6) reflowing the truncated conductive bumps to form reflowed conductive bumps.

Abstract: A method for forming a stacked integrated circuit package of primary dies on a carrier die, includes forming electrically conductive pillars at connection pads defined on an active face of a carrier wafer incorporating carrier integrated circuits, the electrically conductive pillars providing electrical connections to said carrier integrated circuits; attaching primary dies to the active face of the carrier wafer, each supporting electrically conductive pillars at connection pads defined on an active face of the primary die; encapsulating the active face of the carrier wafer and the primary dies attached thereto in an insulating material; producing a wafer package by removing a thickness of the insulating layer sufficient to expose the electrically conductive pillars; and singulating the carrier wafer to form stacked integrated circuit packages, each package comprising at least one primary die on a carrier die.

Abstract: A tape for carrying at least a semiconductor package structure comprising a body, a carrying plate and a side wall is provided. The body has at least an opening. The carrying plate is capable of carrying the semiconductor package structure and has a plurality of containing portions. The side wall surrounds the carrying plate and connects between the body and the carrying plate. A side surface of the semiconductor package structure leans against the side wall and a plurality of solder balls disposed on a bottom surface of the semiconductor package structure are contained in the containing portion. Accordingly, the solder balls may be protected from being damaged by the carrying plate.

Abstract: A semiconductor package includes a package substrate including a first wiring embedded in the package substrate, a second wiring embedded in the package substrate, the second wiring electrically insulated from the first wiring, and a capacitor embedded in the package substrate, the capacitor including a first electrode electrically connected to the first wiring and a second electrode electrically connected to the second wiring. At least a first semiconductor chip is disposed on the package substrate. A plurality of connection terminals are disposed between the package substrate and the first semiconductor chip and contact the package substrate, and form at least a first group of at least two connection terminals formed continuously adjacent to each other and electrically connected to the first wiring, and at least a second group of at least two connection terminals formed continuously adjacent to each other and electrically connected to the second wiring.

Abstract: A a printed circuit board (PCB) for a semiconductor package and a semiconductor package having the same, which may improve adhesion of a PCB with an encapsulant. The semiconductor package includes a PCB for a semiconductor package including a resin through hole disposed in a central portion thereof and at least one resin fixing hole disposed in an outermost edge thereof, a semiconductor chip connected to first connection pads disposed on a first surface of the PCB by bumps, an upper encapsulant configured to hermetically seal the first surface of the PCB and the semiconductor chip, and a lower encapsulant protrusion configured to extend to a second surface of the PCB through the resin through hole and the resin fixing hole disposed in the first surface of the PCB.

Abstract: A flip chip interconnect has a tapering interconnect structure, and the area of contact of the interconnect structure with the site on the substrate metallization is less than the area of contact of the interconnect structure with the die pad. Also, a bond-on-lead or bond-on-narrow pad or bond on a small area of a contact pad interconnection includes such tapering flip chip interconnects. Also, methods for making the interconnect structure include providing a die having interconnect pads, providing a substrate having interconnect sites on a patterned conductive layer, providing a bump on a die pad, providing a fusible electrically conductive material either at the interconnect site or on the bump, mating the bump to the interconnect site, and heating to melt the fusible material.

Abstract: Wafer level chip packages including risers having sloped sidewalls and methods of fabricating such chip packages are disclosed. The inventive wafer level chip packages may advantageously be used in various microelectronic assemblies.

Abstract: A structure and a method of manufacturing a Pb-free Controlled Collapse Chip Connection (C4) with a Ball Limiting Metallurgy (BLM) structure for semiconductor chip packaging that reduce chip-level cracking during the Back End of Line (BEOL) processes of chip-join cool-down. An edge of the BLM structure that is subject to tensile stress during chip-join cool down is protected from undercut of a metal seed layer, caused by wet etch of the chip to remove metal layers from the chip's surface and solder reflow, by an electroplated barrier layer, which covers a corresponding edge of the metal seed layer.

Abstract: A ball grid array semiconductor device has a wiring substrate (2), a semiconductor chip (6) disposed on one surface side of the wiring substrate, and a bump arrangement (5) as external terminals disposed on a surface side, opposite to the one surface side, of the wiring substrate. The semiconductor chip is mounted so that the center of the semiconductor chip is shifted from the center of the semiconductor device by one pitch or more of the bump arrangement, and the bump arrangement has a reinforcing structure (5-2) for a bump array located at a position farthest from the center of the semiconductor device in a shift direction of the semiconductor chip.

Abstract: A stacked semiconductor package includes a substrate and a plurality of semiconductor dice stacked on the substrate. Each semiconductor die includes a recess, and a discrete component contained in the recess encapsulated in a die attach polymer. The stacked semiconductor package also includes interconnects electrically connecting the semiconductor dice and discrete components, and an encapsulant encapsulating the dice and the interconnects.

Abstract: Provided is a semiconductor device having a substrate, a semiconductor chip flip-chip mounted on the substrate, and a stacked film provided in a gap between the substrate and the semiconductor chip. The stacked film is composed of a protective film covering the surface of the substrate, and an underfill film formed between the solder resist film and the semiconductor chip. The protective film is roughened on the contact surface brought into contacting said underfill film.

Abstract: High-speed memory systems that consume a reduced amount of board space, have a low height or profile, or both. This reduction in board space and height may result in shorter signal paths from a board to a memory device, thereby improving the high-speed performance of the high-speed memory system. One example may provide a space-efficient memory system that consumes a reduced amount of board space. Space efficiency may gained by arraying memory devices on an interposer that mates with a socket attached to a board. Another example may provide a memory system that has a reduced height or profile. This reduced height may be achieved by employing a socket that accepts an interposer in a lateral or rotational direction.

Abstract: An integrated circuit (IC) device includes a substrate having a top surface including active circuitry including a plurality of I/O nodes, and a plurality of die pads coupled to the plurality of I/O nodes. A first dielectric layer including first dielectric vias is over the plurality of die pads. A redirect layer (RDL) including a plurality of RDL capture pads is coupled to the plurality of die pads over the first dielectric vias. A second dielectric layer including second dielectric vias is over the plurality of RDL capture pads. At least one of the second dielectric vias is a crack arrest via that has a via shape that includes an apex that faces away from a neutral stress point of the IC die and is oriented along a line from the neutral stress point to the crack arrest via to face in a range of ±30 degrees from the line. Under bump metallization (UBM) pads are coupled to the plurality of RDL capture pads over the second dielectric vias, and metal bonding connectors are on the UBM pads.

Abstract: A chip design (1) comprising an external supply connection (VBAT), an internal supply connection (VDD), an integrated circuit (2) that is coupled to the internal supply connection (VDD) for voltage supply, and a fuse (3) that electrically connects the internal supply connection (VBAT) and is arranged within the chip design (1).

Abstract: A semiconductor device includes: stacked semiconductor chips having respective input/output pads on surfaces thereof; a lower resin body molding the lower semiconductor chip and having a surface coplanar with the lower chip; an upper resin body molding the upper chip and coupled with the first resin body; wirings connected to input/output pads of the lower or upper chip and extending horizontally; external connection metal posts formed on the wirings and having tops exposed from the second resin body; and ball-shaped external connection terminals connected to the tops of the external connection metal posts.

Abstract: Some embodiments herein relate to a transmitter. The transmitter includes an integrated circuit (IC) package including a first antenna configured to radiate a first electromagnetic signal therefrom. A printed circuit board (PCB) substrate includes a waveguide configured to receive the first electromagnetic signal and to generate a waveguide signal based thereon. A second antenna can be electrically coupled to the waveguide and can radiate a second electromagnetic signal that corresponds to the waveguide signal. Other devices and methods are also disclosed.

Abstract: A BGA semiconductor device includes a semiconductor package and a mounting board mounting thereon the semiconductor package, wherein an array of signal electrodes of the semiconductor package and an array of signal electrodes of the mounting board are coupled together via signal bumps. The BGA semiconductor device also includes a dummy bump, which reinforces the bending strength of the BGA semiconductor device and is broken by a shearing force caused by thermal expansion to alleviate the stress for the signal bumps.

Abstract: A laser release and glass chip removal process for a integrated circuit module avoiding carrier edge cracking is provided.

Abstract: Underfill flow guide structures and methods of using the same are provided with a module. In particular the underfill flow guide structures are integrated with a substrate and are configured to prevent air entrapment from occurring during capillary underfill processes.

Abstract: A substrate of a micro-BGA package is revealed, primarily comprising a substrate core, a first trace, and a second trace where the substrate core has a slot formed between a first board part and a second board part. The first trace is disposed on the first board part and has a suspended inner lead extended into the slot where the inner lead has an assumed broken point. The second trace is disposed on the second board part and is integrally connected to the inner lead at the assumed broken point. More particularly, a non-circular through hole is formed at the assumed broken point and has two symmetric V-notches away from each other and facing toward two opposing external sides of the inner lead so that the inner lead at two opposing external sides does not have the conventional V-notches cutting into the inner lead from outside. Moreover, the inner lead will not unexpectedly be broken and the inner lead can easily and accurately be broken at the assumed broken point during thermal compression processes.

Abstract: The present invention relates to a compound semiconductor substrate and a method for manufacturing the same. The present invention provides the manufacturing method which coats spherical balls on a substrate, forms a metal layer between the spherical balls, removes the spherical balls to form openings, and grows a compound semiconductor layer from the openings. According to the present invention, the manufacturing method can be simplified and grow a high quality compound semiconductor layer rapidly, simply and inexpensively, as compared with a conventional ELO (Epitaxial Lateral Overgrowth) method or a method for forming a compound semiconductor layer on a metal layer. And, the metal layer serves as one electrode of a light emitting device and a light reflecting film to provide a light emitting device having reduced power consumption and high light emitting efficiency.

Abstract: A semiconductor device comprising a semiconductor pellet mounted on a pellet mounting area of the main surface of a base substrate, in which first electrode pads arranged on the back of the base substrate are electrically connected to bonding pads arranged on the main surface of the semiconductor pellet. The base substrate is formed of a rigid substrate, and its first electrode pads are electrically connected to the second electrode pads arranged on its reverse side. The semiconductor pellet is mounted on the pellet mounting area of the main surface of the base substrate, with its main surface downward, and its bonding pads are connected electrically with the second electrode pads of the base substrate through bonding wires passing through slits formed in the base substrate.