Principal Metal Being Copper (epo) Patents (Class 257/E23.161)
  • Publication number: 20100044866
    Abstract: A first insulating film is provided between a lower interconnect and an upper interconnect. The lower interconnect and the upper interconnect are connected to each other by way of a via formed in the first insulating film. A dummy via or an insulating slit is formed on/in the upper interconnect near the via.
    Type: Application
    Filed: October 28, 2009
    Publication date: February 25, 2010
    Applicant: PANASONIC CORPORATION
    Inventor: Takeshi HARADA
  • Publication number: 20100038787
    Abstract: A semiconductor device has an interlayer insulating film that is formed on a semiconductor substrate and has a trench formed therein; a first diffusion barrier film formed on an inner surface of the trench; a Cu wiring layer buried in the trench with the first diffusion barrier film interposed between the Cu wiring layer and the inner surface of the trench; a second diffusion barrier film formed on top of the interlayer insulating film and the Cu wiring layer; an alloy layer primarily containing Cu formed at a first interface between the Cu wiring layer and the second diffusion barrier film; a first reaction layer that is formed at a second interface between the interlayer insulating film and the second diffusion barrier film; and a second reaction layer that is formed on the alloy layer and the first reaction layer.
    Type: Application
    Filed: July 30, 2009
    Publication date: February 18, 2010
    Inventor: Shinya ARAI
  • Publication number: 20100038789
    Abstract: A dielectric layer is patterned with at least one line trough and/or at least one via cavity. A metallic nitride liner is formed on the surfaces of the patterned dielectric layer. A metal liner is formed on the surface of the metallic nitride liner. A conformal copper nitride layer is formed directly on the metal liner by atomic layer deposition (ALD) or chemical vapor deposition (CVD). A Cu seed layer is formed directly on the conformal copper nitride layer. The at least one line trough and/or the at least one via cavity are filled with an electroplated material. The direct contact between the conformal copper nitride layer and the Cu seed layer provides enhanced adhesion strength. The conformal copper nitride layer may be annealed to covert an exposed outer portion into a contiguous Cu layer, which may be employed to reduce the thickness of the Cu seed layer.
    Type: Application
    Filed: August 13, 2008
    Publication date: February 18, 2010
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Tien-Jen Cheng, Zhengwen Li, Keith Kwong Hon Wong, Huilong Zhu
  • Publication number: 20100032837
    Abstract: A semiconductor device according to the present invention includes: a semiconductor substrate; a first copper interconnection provided on the semiconductor substrate; an insulating layer provided over the first copper interconnection and having a hole extending therethrough to the first copper interconnection; a barrier layer composed of a tantalum-containing material and covering at least a sidewall of the hole and a part of the first copper interconnection exposed in the hole; and a second copper interconnection provided in intimate contact with the barrier layer and electrically connected to the first copper interconnection via the barrier layer; wherein the barrier layer has a nitrogen concentration profile such that the concentration of nitrogen contained in the material varies to be lower in a boundary portion of the barrier layer adjacent to the first copper interconnection and in a boundary portion of the barrier layer adjacent to the second copper interconnection and higher in an intermediate portion
    Type: Application
    Filed: October 11, 2007
    Publication date: February 11, 2010
    Applicant: ROHM CO., LTD
    Inventors: Ryosuke Nakagawa, Takahisa Yamaha, Yuichi Nakao, Katsumi Sameshima, Satoshi Kageyama
  • Publication number: 20100025851
    Abstract: A semiconductor device and a method for manufacturing the same include forming a second copper-plated layer over a second IMD layer and inside a second aperture formed in the second IMD by an electroplating process that uses the exposed first copper-plated layer as a seed layer. With the method, the copper-plated layer may be more simply and rapidly formed and achieve superior gap filling characteristics.
    Type: Application
    Filed: July 29, 2009
    Publication date: February 4, 2010
    Inventor: Byung-Ho Lee
  • Publication number: 20100013098
    Abstract: A method of forming an interconnect structure, comprising forming a first interconnect layer (123) embedded in a first dielectric layer (118), forming a dielectric tantalum nitride barrier (150) by means of atomic layer deposition on the surface of the first interconnect (123), depositing a second dielectric layer (134) over the first interconnect (123) and the barrier (150) and etching a via (154) in the dielectric layer (134) to the barrier (150). The barrier (150) is then exposed to a treatment through the via (154) to change it from the dielectric phase to the conductive phase (180) and the via (154) is subsequently filled with conductive material (123).
    Type: Application
    Filed: November 24, 2005
    Publication date: January 21, 2010
    Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V.
    Inventor: Wim Besling
  • Publication number: 20100013100
    Abstract: An integrated circuit system with one or more copper interconnects is provided. The one or more copper interconnects are in conductive contact with a substrate. The integrated circuit system includes a first dielectric layer, a copper material filling a first via through the first dielectric layer, a second dielectric layer in contact with the first dielectric layer, and a diffusion barrier layer. The diffusion barrier layer at least partially fills a second via through the second dielectric layer. At least a first part of the diffusion barrier layer is in direct contact with the copper material, and at least a second part of the diffusion barrier layer is in direct contact with the second dielectric layer. The integrated circuit system further includes a gold material at least partially filling the second via. The gold material is conductively connected with the copper material through the diffusion barrier layer and conductively connected with a substrate.
    Type: Application
    Filed: October 27, 2008
    Publication date: January 21, 2010
    Applicant: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: De Yuan Xiao, Guo Qing Chen
  • Publication number: 20100007020
    Abstract: A semiconductor device includes: an insulating film including a porous insulating material and formed above a substrate; an interconnection wire including copper and buried in a groove formed at least in an obverse surface of the insulating film; and a barrier insulating film including an insulating material containing a nitrogen heterocyclic compound and formed over the insulating film and the interconnection wire.
    Type: Application
    Filed: June 30, 2009
    Publication date: January 14, 2010
    Applicant: FUJITSU MICROELECTRONICS LIMITED
    Inventor: Yukio Takigawa
  • Publication number: 20100007021
    Abstract: Semiconductor devices including a substrate and an uppermost insulating layer formed on the substrate and having pores is provided. A conductive wiring is provided in the uppermost insulating layer. Dummy vias are provided, each penetrating the uppermost insulating layer, being adjacent to the conductive wiring, and having a space therein. Related methods of fabricating semiconductor devices are also provided.
    Type: Application
    Filed: July 8, 2009
    Publication date: January 14, 2010
    Inventors: Jae-Ouk Choo, Il-Young Yoon, Tae-Hoon Lee, Kyoung-Woo Lee
  • Publication number: 20090321937
    Abstract: A semiconductor device includes an insulating film including oxygen formed over a semiconductor substrate, a recess formed in the insulating film, a refractory metal film formed on the inner wall of the recess, a metal film including copper, manganese, and nitrogen formed on the refractory metal film, and a copper film formed on the metal film to fill in the recess.
    Type: Application
    Filed: April 29, 2009
    Publication date: December 31, 2009
    Applicant: FUJITSU LIMITED
    Inventors: Masaki HANEDA, Noriyoshi SHIMIZU, Nobuyuki OHTSUKA, Yoshiyuki NAKAO, Michie SUNAYAMA, Takahiro TABIRA
  • Publication number: 20090315180
    Abstract: A multi-layer thick metallization structure for a microelectronic device includes a first barrier layer (111), a first metal layer (112) over the first barrier layer, a first passivation layer (113) over the first metal layer, a via structure (114) extending through the first passivation layer, a second barrier layer (115) over the first passivation layer and in the via structure, a second metal layer (116) over the second barrier layer, and a second passivation layer (117) over the second metal layer and the first passivation layer.
    Type: Application
    Filed: June 20, 2008
    Publication date: December 24, 2009
    Inventor: Kevin J. Lee
  • Publication number: 20090309221
    Abstract: A semiconductor device of this invention has a copper wiring layer, of which a layer, to which a composition including at least one substance selected from the group consisting of ammonia and organic bases is applied, and a silicon-containing insulating film are sequentially superimposed on the copper wiring layer. Accordingly, semiconductor devices having insulating layers which adheres well to the copper serving as the wiring material can be obtained.
    Type: Application
    Filed: August 20, 2009
    Publication date: December 17, 2009
    Applicant: FUJITSU LIMITED
    Inventors: Shiro Ozaki, Yoshihiro Nakata, Yasushi Kobayashi, Ei Yano
  • Publication number: 20090302475
    Abstract: A semiconductor device includes a first interlayer insulating film, and a plurality of first interconnects formed in the first interlayer insulating film. A void is selectively formed between adjacent ones of the plurality of first interconnects in the first interlayer insulating film, and a cap insulating film is formed in a region located over the void and between the interconnects. Respective widths of a lower end and an upper end of the void are substantially the same as a gap between the interconnects located adjacent to the void, and the lower end of the void is located lower than lower ends of the first interconnects located adjacent to the void.
    Type: Application
    Filed: August 12, 2009
    Publication date: December 10, 2009
    Inventors: Hayato Korogi, Takeshi Harada, Akira Ueki
  • Publication number: 20090302476
    Abstract: The invention generally relates to semiconductor devices, and more particularly to structures and methods for enhancing electromigration (EM) performance in interconnects. A method includes forming an interconnect, forming a cap on the interconnect, and forming a plurality of holes in the cap to improve electromigration performance of the interconnect.
    Type: Application
    Filed: June 4, 2008
    Publication date: December 10, 2009
    Inventor: Baozhen Li
  • Publication number: 20090294968
    Abstract: A structure for suppressing localized metal precipitate formation (LMPF) in semiconductor processing. For each metal wire that is exposed to the manufacturing environment and is electrically coupled to an N region, at least one P+ region is formed electrically coupled to the same metal wire. As a result, few excess electrons are available to combine with metal ions to form localized metal precipitate at the metal wire. A monitoring ramp terminal can be formed around and electrically disconnected from the metal wire. By applying a voltage difference to the metal wire and the monitoring ramp terminal and measuring the resulting current flowing through the metal wire and the monitoring ramp terminal, it can be determined whether localized metal precipitate is formed at the metal wire.
    Type: Application
    Filed: August 7, 2009
    Publication date: December 3, 2009
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jonathan D. Chapple-Sokol, Terence B. Hook, Baozhen Li, Thomas L. McDevitt, Christopher A. Ponsolle, Bette B. Reuter, Timothy D. Sullivan, Jeffrey S. Zimmerman
  • Publication number: 20090294959
    Abstract: A semiconductor package device, a semiconductor package structure, and fabrication methods thereof are provided, which mainly includes disposing a plurality of semiconductor chips on a wafer formed with TSVs (Through Silicon Vias) and electrically connecting the semiconductor chips to the TSVs; encapsulating the semiconductor chips with an encapsulant; and disposing a hard component on the encapsulant. The hard component ensures flatness of the wafer during a solder bump process and provides support to the wafer during a singulation process such that the wafer can firmly lie on a singulation carrier, thereby overcoming the drawbacks of the prior art, namely difficulty in mounting of solder bumps, and difficulty in cutting of the wafer.
    Type: Application
    Filed: December 4, 2008
    Publication date: December 3, 2009
    Applicant: Siliconware Precision Industries Co., Ltd.
    Inventors: Cheng-Chia Chiang, Chin-Huang Chang, Chien-Ping Huang, Chih-Ming Huang, Jung-Pin Huang
  • Patent number: 7605470
    Abstract: A method for fabricating a semiconductor device. The method includes providing a semiconductor substrate including a surface region. The method forms a first interlayer dielectric overlying the surface region and forms an interconnect layer overlying the first interlayer dielectric layer. The method also forms a low K dielectric layer overlying the interconnect layer, which has a predetermined shape. The method forms a copper interconnect layer overlying the low K dielectric layer. In a preferred embodiment, the low K dielectric layer maintains the predetermined shape using a dummy pattern structure provided within a portion of the low K dielectric layer to mechanically support and maintain the predetermined shape of the low K dielectric layer between the interconnect layer and the copper interconnect layer.
    Type: Grant
    Filed: December 15, 2006
    Date of Patent: October 20, 2009
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventor: Xian J. Ning
  • Patent number: 7605468
    Abstract: A method for forming conductive contacts and interconnects in a semiconductor structure, and the resulting conductive components are provided. In particular, the method is used to fabricate single or dual damascene copper contacts and interconnects in integrated circuits such as memory devices and microprocessor.
    Type: Grant
    Filed: August 29, 2006
    Date of Patent: October 20, 2009
    Assignee: MOSAID Technologies Incorporated
    Inventors: Kie Y Ahn, Leonard Forbes
  • Publication number: 20090256263
    Abstract: The present invention in one embodiment provides a method of forming an interconnect comprising, providing a interlevel dielectric layer atop a substrate, the interlevel dielectric layer including at least one tungsten (W) stud extending from an upper surface of the interlevel dielectric to the substrate; recessing an upper surface of the at least one tungsten (W) stud below the upper surface of the interlevel dielectric to provide at least one recessed tungsten (W) stud; forming a first low-k dielectric layer atop the upper surface of the interlevel dielectric layer and the at least one recessed tungsten (W) stud; forming a opening through the first low-k dielectric layer to expose an upper surface of the at least one recessed tungsten stud; and filling the opening with copper (Cu).
    Type: Application
    Filed: April 9, 2008
    Publication date: October 15, 2009
    Applicant: International Business Machines Corporation
    Inventors: Griselda Bonilla, Kaushik A. Kumar, Lawrence A. Clevenger, Stephan Grunow, Kevin S. Petrarca, Roger A. Quon
  • Publication number: 20090250821
    Abstract: Devices and methods for protecting the metal within a via in a semiconductor substrate from corrosion are provided. Specifically, embodiments of the present invention relate to disposing a corrosion resistant metal layer within a recess formed in a semiconductor substrate such that the metal subsequently deposited within the via will adhere to the corrosion resistant metal layer, then backgrinding the bottom surface of the semiconductor substrate to expose the corrosion resistant metal. For example, the metal deposited within the recess may be copper, while the corrosion resistant metal may be a noble metal such as palladium.
    Type: Application
    Filed: April 3, 2008
    Publication date: October 8, 2009
    Applicant: Micron Technologies, Inc.
    Inventor: Swarnal Borthakur
  • Patent number: 7598166
    Abstract: A semiconductor structure and methods for forming the same. The structure includes (a) a substrate; (b) a first device and a second device each being on the substrate; (c) a device cap dielectric layer on the first and second devices and the substrate, wherein the device cap dielectric layer comprises a device cap dielectric material; (d) a first dielectric layer on top of the device cap dielectric layer, wherein the first dielectric layer comprises a first dielectric material; (e) a second dielectric layer on top of the first dielectric layer; and (f) a first electrically conductive line and a second electrically conductive line each residing in the first and second dielectric layers. The first dielectric layer physically separates the first and second electrically conductive lines from the device cap dielectric layer. A dielectric constant of the first dielectric material is less than that of the device cap dielectric material.
    Type: Grant
    Filed: September 8, 2006
    Date of Patent: October 6, 2009
    Assignee: International Business Machines Corporation
    Inventors: Zhong-Xiang He, Ning Lu, Anthony Kendall Stamper
  • Publication number: 20090243106
    Abstract: Disclosed structures and methods inhibit atomic migration and related capacitive-resistive effects between a metallization layer and an insulator layer in a semiconductor structure. One exemplary structure includes an inhibiting layer between an insulator and a metallization layer. The insulator includes a polymer or an insulating oxide compound. And, the inhibiting layer has a compound formed from a reaction between the polymer or insulating oxide compound and a transition metal, a representative metal, or a metalloid.
    Type: Application
    Filed: May 18, 2009
    Publication date: October 1, 2009
    Inventor: Paul A. Farrar
  • Publication number: 20090236744
    Abstract: A semiconductor device having a copper interconnection with high electromigration resistance is provided. A semiconductor device of the present invention includes an interconnection layer formed by forming a groove or a hole in an insulating film formed on a substrate, forming a barrier layer on the resulting substrate, forming a copper seed layer on the barrier layer, forming a copper-plated layer by an electrolytic plating method by use of this copper seed layer, and removing the copper-plated layer and the copper seed layer on the surface, wherein the copper seed layer comprises a plurality of layers including a small grain layer and a large grain layer, having different crystal grain sizes from each other, and the small grain layer is in contact with the barrier layer.
    Type: Application
    Filed: February 23, 2006
    Publication date: September 24, 2009
    Inventor: Takao Kinoshita
  • Publication number: 20090236747
    Abstract: A multilevel interconnect structure in a semiconductor device comprises a first insulating layer (2) formed on a semiconductor wafer (1), a Cu interconnect layer (4) formed on the first insulating layer (2), a second insulating layer (6) formed on the Cu interconnect layer (4), and a metal oxide layer (5) formed at an interface between the Cu interconnect layer (4) and the second insulating layer (6). The metal oxide layer (5) is formed by immersion-plating a metal, such as Sn or Zn, on the Cu interconnect layer (4) and then heat-treating the plated layer in an oxidizing atmosphere.
    Type: Application
    Filed: March 19, 2009
    Publication date: September 24, 2009
    Applicants: SEMICONDUCTOR TECHNOLOGY ACADEMIC RESEARCH CENTER, NATIONAL UNIVERSITY CORPORATION TOHOKU UNIVERSITY
    Inventors: Junichi Koike, Yoshito Fujii, Jun Iijima, Noriyoshi Shimizu, Kazuyoshi Maekawa, Koji Arita, Ryotaro Yagi, Masaki Yoshimaru
  • Publication number: 20090218694
    Abstract: A semiconductor device having Cu wiring including a basic crystal structure which can reduce surface voids, and an inspecting technique for the semiconductor device. In the semiconductor device, surface voids can be reduced down to 1/10 or less of a current practical level by specifying a barrier layer and a seed layer and setting a proportion (frequency) of occupation of a coincidence site lattice (CSL) boundary having a grain boundary Sigma value 27 or less to all crystal grain boundaries of a Cu wiring to 60% or higher. Alternatively, a similar effect of surface void reduction can be obtained by specifying a barrier layer and a seed layer and setting a proportion (frequency) of occupation of a coincidence site lattice (CSL) boundary having a grain boundary Sigma value 3 to all crystal grain boundaries of a Cu wiring to 40% or higher.
    Type: Application
    Filed: February 20, 2009
    Publication date: September 3, 2009
    Inventors: Takahiko KATO, Hiroshi NAKANO, Haruo AKAHOSHI, Yuuji TAKADA, Yoshimi SUDO, Tetsuo FUJIWARA, Itaru KANNO, Tomoryo SHONO, Yukinori HIROSE
  • Publication number: 20090206485
    Abstract: An interconnect structure including a gouging feature at the bottom of one of the via openings and a method of forming the same are provided. In accordance with the present invention, the method of forming the interconnect structure does not disrupt the coverage of the deposited diffusion barrier in the overlying line opening, nor does it introduce damages caused by Ar sputtering into the dielectric material including the via and line openings. In accordance with the present invention, such an interconnect structure contains a diffusion barrier layer only within the via opening, but not in the overlying line opening. This feature enhances both mechanical strength and diffusion property around the via opening areas without decreasing volume fraction of conductor inside the line openings.
    Type: Application
    Filed: April 27, 2009
    Publication date: August 20, 2009
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chih-Chao Yang, Terry A. Spooner, Oscar van der Straten
  • Patent number: 7569937
    Abstract: By directly forming an underbump metallization layer on a copper-based contact region, the formation of any other terminal metals, such as aluminum and corresponding adhesion/barrier layers may be avoided. Consequently, the thermal and electrical behavior of the resulting bump structure may be improved, while process complexity may significantly be reduced.
    Type: Grant
    Filed: May 8, 2006
    Date of Patent: August 4, 2009
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Frank Kuechenmeister, Matthias Lehr, Gotthard Jungnickel
  • Publication number: 20090189282
    Abstract: A semiconductor device according to the present invention includes: a low dielectric layer made of a low dielectric material; a high dielectric layer formed on the low dielectric layer and made of a high dielectric material having a higher dielectric constant than the low dielectric material; a protective layer formed on the high dielectric layer and made of an insulating material differing from the low dielectric material and the high dielectric material; a groove formed by digging in from an upper surface of the protective layer to the low dielectric layer; a barrier film coated onto a bottom surface and side surfaces of the groove and made of a material having a barrier property with respect to diffusion of Cu; and a wiring formed on the barrier film, made of a metal material having Cu as a main component, and completely filling the groove.
    Type: Application
    Filed: January 9, 2009
    Publication date: July 30, 2009
    Applicant: ROHM CO., LTD.
    Inventors: Yoshihisa Takada, Satoshi Kageyama
  • Patent number: 7566975
    Abstract: A semiconductor device includes a semiconductor substrate, a copper-containing metal interconnect over the semiconductor substrate, and a copper-containing connection plug, and the metal interconnect includes metal elements other than copper, and a concentration of different metal elements in a connection portion between the metal interconnect and the connection plug is higher than a concentration of the different metal elements in a center portion of the metal interconnect, and higher than a concentration of different elements in upper face portion of the metal interconnect other than the connection portion.
    Type: Grant
    Filed: March 4, 2005
    Date of Patent: July 28, 2009
    Assignee: NEC Electronics Corporation
    Inventor: Koichi Motoyama
  • Publication number: 20090166869
    Abstract: Technologies related to forming metal lines of a semiconductor device are disclosed. A method of forming metal lines of a semiconductor device may include forming at least one interlayer insulating layer on a semiconductor substrate, forming via holes and trenches in the at least one interlayer insulating layer, forming an anti-diffusion film on the via holes and the trenches, depositing a seed Cu layer on the anti-diffusion film, after the seed Cu layer is deposited, depositing rhodium (Rh), and forming Cu line on the deposited Rh. The Rh improves an adhesive force between Cu layers and prevents oxide materials or a corrosion phenomenon from occurring on the seed Cu layer. Accordingly, occurrence of delamination in subsequent processes (for example, annealing and CMP) can be prevented or reduced.
    Type: Application
    Filed: October 20, 2008
    Publication date: July 2, 2009
    Applicant: DONGBU HITEK CO., LTD.
    Inventor: Sung Ho JANG
  • Publication number: 20090160061
    Abstract: The present disclosure provide an integrated circuit. The integrated circuit includes a through-silicon-via (TSV) trench configured in a semiconductor substrate; a conductive pad formed on the semiconductor substrate, the conductive pad being adjacent the TSV trench; a silicon nitride layer disposed over the conductive pad and in the TSV trench; a titanium layer disposed on the silicon nitride layer; a titanium nitride layer disposed on the titanium layer; and a copper layer disposed on the titanium nitride layer.
    Type: Application
    Filed: September 8, 2008
    Publication date: June 25, 2009
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuo-Ching Hsu, Chen-Shien Chen, Boe Su, Hon-Lin Huang
  • Patent number: 7550822
    Abstract: Methods of forming dual-damascene metal wiring patterns include forming a first metal wiring pattern (e.g., copper wiring pattern) on an integrated circuit substrate and forming an etch-stop layer on the first metal wiring pattern. These steps are followed by the steps of forming an electrically insulating layer on the etch-stop layer and forming an inter-metal dielectric layer on the electrically insulating layer. The inter-metal dielectric layer and the electrically insulating layer are selectively etched in sequence to define an opening therein that exposes a first portion of the etch-stop layer. This opening may include a trench and a via hole extending downward from a bottom of the trench. A first barrier metal layer is formed on a sidewall of the opening and directly on the first portion of the etch-stop layer. A portion of the first barrier metal layer is selectively removed from the first portion of the etch-stop layer.
    Type: Grant
    Filed: May 31, 2006
    Date of Patent: June 23, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Boung Ju Lee, Heon Jong Shin, Hee Sung Kang
  • Patent number: 7544614
    Abstract: A slit forming process with respect to a coated film, includes: forming a step pattern having an end part on a substrate; coating a liquid material for forming a coated film on the substrate in the manner of covering at least the end part of the step pattern; and forming the coated film by drying the coated liquid material, together with forming a slit at a position corresponding to the end part of the step pattern.
    Type: Grant
    Filed: January 3, 2006
    Date of Patent: June 9, 2009
    Assignee: Seiko Epson Corporation
    Inventor: Ichio Yudasaka
  • Publication number: 20090134518
    Abstract: A semiconductor device of the present invention is provided with a substrate; an insulating film made of a fluorine-containing carbon film and formed on the substrate; a copper wiring buried in the insulating film; and a barrier film formed between the insulating film and the copper wiring. The barrier film includes a first film made of titanium for suppressing a diffusion of fluorine, and a second film made of tantalum for suppressing a diffusion of copper and formed between the first film and the copper wiring.
    Type: Application
    Filed: June 6, 2007
    Publication date: May 28, 2009
    Applicant: TOKYO ELECTRON LIMITED
    Inventor: Masahiro Horigome
  • Publication number: 20090121358
    Abstract: A trench is formed in a low K dielectric (100) over a plurality of vias (120) also formed in the low K dielectric layer (100). The vias are separated by a distance of less than XV and the edge of the trench is greater than XTO from the edge ? of the via closest to the edge of the trench. The trench and vias are subsequently filled with copper (150, 160) to form the interconnect line.
    Type: Application
    Filed: May 12, 2008
    Publication date: May 14, 2009
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Rajesh Tiwari, Russell Fields, Scott A. Boddicker, Andrew Tae Kim
  • Publication number: 20090121356
    Abstract: The semiconductor device according to the present invention includes a first interlayer dielectric film, a plurality of copper damascene wires embedded in the first interlayer dielectric film at an interval from each other, and a diffusion preventing film stacked on the first interlayer dielectric film for preventing diffusion of copper contained in the copper damascene wires, while an air gap closed with the diffusion preventing film is formed between the copper damascene wires adjacent to each other by partially removing the first interlayer dielectric film from the space between these copper damascene wires.
    Type: Application
    Filed: November 12, 2008
    Publication date: May 14, 2009
    Applicant: ROHM CO., LTD.
    Inventor: Ryosuke NAKAGAWA
  • Patent number: 7531447
    Abstract: An integrated circuit includes copper lines, wherein the crystal structure of the copper has a greater than 30% <001 > crystal orientation and a less than 20% <111> crystal orientation.
    Type: Grant
    Filed: September 6, 2005
    Date of Patent: May 12, 2009
    Assignee: STMicroelectronics SA
    Inventors: Pierre Caubet, Magali Gregoire
  • Publication number: 20090096104
    Abstract: Example embodiments relate to semiconductor devices having a single body crack stop structure configured to reduce or prevent crack propagation and/or moisture penetration. A semiconductor substrate according to example embodiments may include an active region and a crack stop region surrounding the active region. Interlayer insulating layers may be sequentially stacked on the semiconductor substrate. The interlayer insulating layers may include first dual damascene patterns and a first opening. The first dual damascene patterns may be formed in the interlayer insulating layers so as to be perpendicular to the surface of the semiconductor substrate while exposing a first portion of the semiconductor substrate. The first opening may be formed in the crack stop region and may extend through the interlayer insulating layers to expose a second portion of the semiconductor substrate.
    Type: Application
    Filed: June 30, 2008
    Publication date: April 16, 2009
    Inventors: Kyoung-woo Lee, Hong-jae Shin
  • Publication number: 20090096103
    Abstract: A method for forming a barrier metal layer includes forming a metal compound film composed of a first metal and a second metal on sidewalls of a contact hole, and then selectively etching the metal compound film and then simultaneously forming a barrier metal layer and a first metal seed layer on sidewalls of the contact hole by performing a thermal treatment process on the metal compound film. Accordingly, the process time can be shortened because the sputtering process can be reduced by forming a barrier metal layer and a copper seed layer by reaction between the second metal material and an underlying insulating film by performing the thermal treatment process.
    Type: Application
    Filed: September 2, 2008
    Publication date: April 16, 2009
    Inventor: Kyung-Min Park
  • Patent number: 7504724
    Abstract: A semiconductor device comprises: a plurality of first wiring lines formed in a first layer with a first wiring width and a first wiring space; a plurality of second wiring lines formed in a second layer different from the above-described first layer with a second wiring width and a second wiring space larger than the above-described first wiring width and first wiring space; and a contact plug connecting the first wiring line and second wiring line. The above-described contact plug is formed over a plurality of adjacent ones of the above-described first wiring lines and has a pattern connecting the plurality of adjacent ones of the above-described first wiring lines and one of the above-described second wiring lines.
    Type: Grant
    Filed: January 11, 2006
    Date of Patent: March 17, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Takuya Futatsuyama
  • Publication number: 20090057905
    Abstract: A metal interconnection layout for a semiconductor device and a method of manufacturing the semiconductor device are disclosed. The semiconductor device can maintain a minimum design rule and secure a distance between via holes to inhibit a metal bridge phenomenon from being generated. The semiconductor device comprises a substrate, an interlayer dielectric, a first metal interconnection, and a second metal interconnection parallel to the first metal interconnection. The interlayer dielectric can be disposed on the substrate. The first metal interconnection is connected to the substrate or lower interconnect through at least one first via hole in the interlayer dielectric. The second metal interconnection is adjacent to the first metal interconnection and can be connected to the substrate or another lower interconnect through at least one second via hole in the interlayer dielectric.
    Type: Application
    Filed: August 27, 2008
    Publication date: March 5, 2009
    Inventor: Dong Yeal Keum
  • Publication number: 20090032952
    Abstract: Tantalum compounds of Formula I hereof are disclosed, having utility as precursors for forming tantalum-containing films such as barrier layers. The tantalum compounds of Formula I may be deposited by CVD or ALD for forming semiconductor device structures including a dielectric layer, a barrier layer on the dielectric layer, and a copper metallization on the barrier layer, wherein the barrier layer includes a Ta-containing layer and sufficient carbon so that the Ta-containing layer is amorphous. According to one embodiment, the semiconductor device structure is fabricated by depositing the Ta-containing barrier layer, via CVD or ALD, from a precursor including the tantalum compound of Formula I hereof at a temperature below about 400° C. in a reducing or inert atmosphere, e.g., a gas or plasma optionally containing a reducing agent.
    Type: Application
    Filed: January 12, 2008
    Publication date: February 5, 2009
    Applicant: ADVANCED TECHNOLOGY MATERIALS, INC.
    Inventors: Tianniu Chen, Chongying Xu, Jeffrey F. Roeder, Thomas H. Baum
  • Publication number: 20090035937
    Abstract: A semiconductor interconnect structure having reduced hillock formation and a method for forming the same are provided. The semiconductor interconnect structure includes a conductor formed in a dielectric layer. The conductor includes at least three sub-layers, wherein the ratio of the impurity concentrations in neighboring sub-layers is preferably greater than about two.
    Type: Application
    Filed: August 6, 2008
    Publication date: February 5, 2009
    Inventors: Chung-Hsien Chen, Chun-Chieh Lin, Minghsing Tsai, Shau-Lin Shue
  • Publication number: 20090026617
    Abstract: A semiconductor device having a copper line and a method of forming the same so as to prevent a bridge phenomenon between neighboring upper lines are described. The method may include the steps of forming a capping layer and an intermetal dielectric layer in a stacked configuration over a substrate in which lower lines are formed, forming trenches defining an upper metal line region on the intermetal dielectric layer, and forming a spacer on inner sidewalls of the trenches. A via may then be formed under the exposed first trench using a photolithography process and the spacer for alignment. After removing the spacer, a barrier metal film may be formed on inner walls of the trenches and the via, a copper metal line film may be gap-filled within the trenches and the via, and a surface of the semiconductor device may be polished.
    Type: Application
    Filed: July 8, 2008
    Publication date: January 29, 2009
    Applicant: DONGBU HITEK CO., LTD.
    Inventor: Jeong Ho PARK
  • Patent number: 7482693
    Abstract: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.
    Type: Grant
    Filed: August 21, 2007
    Date of Patent: January 27, 2009
    Inventor: Mou-Shiung Lin
  • Publication number: 20090020875
    Abstract: A semiconductor device is provided. The semiconductor device includes a substrate in which a first interlayer insulation layer having a first via hole and a first trench is formed. The semiconductor device also includes a first via plug and a first metal line respectively formed by filling the first via hole and the first trench with a first metal, a predetermined scratch being formed on the first metal line; and a second via plug a second metal line respectively formed by filling a second via hole and a second trench with a second metal, the second metal lines being separated.
    Type: Application
    Filed: August 27, 2008
    Publication date: January 22, 2009
    Inventor: Min Dae Hong
  • Publication number: 20090014879
    Abstract: In a method of forming a wiring structure for a semiconductor device, an insulation layer is formed on a semiconductor substrate on which a plurality of conductive structures is positioned. An upper surface of the insulation layer is planarized and spaces between the conductive structures are filled with the insulation layer. The insulation layer is partially removed from the substrate to form at least one opening through which the substrate is partially exposed. A residual metal layer is formed on a bottom and a lower portion of the sidewall of the at least one opening and a metal nitride layer is formed on the residual metal layer and an upper sidewall of the opening with a metal material. Accordingly, an upper portion of the barrier layer can be prevented from being removed in a planarization process for forming the metal plug.
    Type: Application
    Filed: July 10, 2008
    Publication date: January 15, 2009
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jin-Ho Park, Gil-Heyun Choi, Sang-Woo Lee, Ho-Ki Lee
  • Publication number: 20090014880
    Abstract: Interconnect structures possessing an organosilicate glass interlayer dielectric material with minimal stoichiometeric modification and optionally an intact organic adhesion promoter for use in semiconductor devices are provided herein. The interconnect structure is capable of delivering improved device performance, functionality and reliability owing to the reduced effective dielectric constant of the stack compared with that of those conventionally employed because of the use of a sacrificial polymeric material deposited onto the dielectric and optional organic adhesion promoter during the barrier open step done prior to ashing the patterning material. This sacrificial film protects the dielectric and optional organic adhesion promoter from modification/consumption during the subsequent ashing step during which the polymeric film is removed.
    Type: Application
    Filed: September 24, 2008
    Publication date: January 15, 2009
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Timothy J. Dalton, Nicholas C. Fuller, Satyanarayana V. Nitta
  • Publication number: 20090001584
    Abstract: A method of fabricating a semiconductor device that may include at least one of the following steps: Forming a lower metal wiring on and/or over a semiconductor substrate. Forming an interlayer insulating film having a damascene hole on and/or over the semiconductor substrate and the lower metal wiring. Forming an anti-diffusion film on and/or over the exposed lower metal wiring below the damascene hole and/or on side surfaces of the damascene hole. Selectively removing the anti-diffusion film formed on and/or over the exposed lower metal wiring at the bottom of the damascene hole using a plasma process that uses an inert gas.
    Type: Application
    Filed: June 20, 2008
    Publication date: January 1, 2009
    Inventor: Sang-Chul Kim
  • Publication number: 20090001587
    Abstract: Disclosed are a method and a system for processing a semiconductor structure of the type including a substrate, a dielectric layer, and a TaN—Ta liner on the dielectric layer. The method comprises the step of using XeF2 to remove at least a portion of the TaN—Ta liner completely to the dielectric layer. In the preferred embodiments, the present invention uses XeF2 selective gas phase etching as alternatives to Ta—TaN Chemical Mechanical Polishing (CMP) as a basic “liner removal process” and as a “selective cap plating base removal process.” In this first use, XeF2 is used to remove the metal liner, TaN—Ta, after copper CMP. In the second use, the XeF2 etch is used to selectively remove a plating base (TaN—Ta) that was used to form a metal cap layer over the copper conductor.
    Type: Application
    Filed: September 4, 2008
    Publication date: January 1, 2009
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: John Michael Cotte, Nils Deneke Hoivik, Christopher Vincent Jahnes, Robert Luke Wisnieff