Abstract: An interconnect structure is provided that has enhanced electromigration reliability without degrading circuit short yield, and improved technology extendibility. The inventive interconnect structure includes a dielectric material having a dielectric constant of about 3.0 or less. The dielectric material has at least one conductive material embedded therein. A noble metal cap is located directly on an upper surface of the at least one conductive region. The noble metal cap does not substantially extend onto an upper surface of the dielectric material that is adjacent to the at least one conductive region, and the noble cap material does not be deposited on the dielectric surface. A method fabricating such an interconnect structure utilizing a low temperature (about 300° C. or less) chemical deposition process is also provided.

Abstract: A dual damascene structure is disclosed. The dual damascene structure includes: a substrate comprising thereon a base dielectric layer and a lower wiring layer inlaid in the base dielectric layer; a dielectric layer on the substrate; a via opening in the dielectric layer, wherein the via opening misaligns with the lower wiring layer thus exposing a portion of the lower wiring layer and a portion of the base dielectric layer, wherein the via opening comprises a bottom including a recessed area; a barrier layer lining interior surface of the via opening and covers the exposed lower wiring layer and the base dielectric layer, wherein only the barrier layer fills the recessed area; and a copper layer filling the via opening on the barrier layer.

Abstract: Electronic devices and design structures of electronic devices containing metal silicide layers. The devices include: a thin silicide layer between two dielectric layers, at least one metal wire abutting a less than whole region of the silicide layer and in electrical contact with the silicide layer.

Abstract: A cap layer for a copper interconnect structure formed in a first dielectric layer is provided. In an embodiment, a conductive layer is located within a dielectric layer and a top surface of the conductive layer has either a recess, a convex surface, or is planar. An alloy layer overlies the conductive layer and is a silicide alloy having a first material from the conductive layer and a second material of germanium, arsenic, tungsten, or gallium.

Abstract: A semiconductor structure and design structure includes at least a first trench and a second trench having different depths arranged in a substrate, a capacitor arranged in the first trench, and a via arranged in the second trench.

Abstract: Some embodiments include methods for depositing copper-containing material utilizing physical vapor deposition of the copper-containing material while keeping a temperature of the deposited copper-containing material at greater than 100° C. Some embodiments include methods in which openings are lined with a metal-containing composition, copper-containing material is physical vapor deposited over the metal-containing composition while a temperature of the copper-containing material is no greater than about 0° C., and the copper-containing material is then annealed while the copper-containing material is at a temperature in a range of from about 180° C. to about 250° C. Some embodiments include methods in which openings are lined with a composition containing metal and nitrogen, and the lined openings are at least partially filled with copper-containing material.

Abstract: A system and method for forming post passivation metal structures is described. Metal interconnections and high quality electrical components, such as inductors, transformers, capacitors, or resistors are formed on a layer of passivation, or on a thick layer of polymer over a passivation layer.

Abstract: An interlayer insulating film containing oxygen and carbon is formed on a semiconductor substrate. A groove is formed in the interlayer insulating film. An auxiliary film containing predetermined first and second metallic elements is formed on a bottom surface and a sidewall of the formed groove. Then, an interconnect body layer containing copper is formed to fill the groove. By performing a thermal treatment, a first barrier film containing a compound of the first metallic element and an oxygen element of the interlayer insulating film, and a second barrier film containing a compound of the second metallic element and carbon element of the interlayer insulating film are formed on the interlayer insulating film on the bottom surface and the sidewall of the groove.

Abstract: Structures and methods of forming metallization layers on a semiconductor component are disclosed. The method includes etching a metal line trench using a metal line mask, and etching a via trench using a via mask after etching the metal line trench. The via trench is etched only in regions common to both the metal line mask and the via mask.

Abstract: The semiconductor device according to the present invention includes a first insulating layer made of a material containing Si and O, a groove shaped by digging down the first insulating layer, an embedded body, embedded in the groove, made of a metallic material mainly composed of Cu, a second insulating layer, stacked on the first insulating layer and the embedded body, made of a material containing Si and O, and a barrier film, formed between the embedded body and each of the first insulating layer and the second insulating layer, made of MnxSiyOz (x, y and z: numbers greater than zero).

Abstract: One aspect of the present invention is a method of processing a substrate. In one embodiment, the method comprises forming an electrical conductor on or in the substrate by providing a mixture comprising metal particles and an electroless deposition solution and electrolessly depositing a metal matrix and co-depositing the metal particles. In another embodiment, the method comprises forming an electrical conductor on or in the substrate by providing a mixture comprising metal particles and an electrochemical plating solution and electrochemically plating a metal matrix and co-depositing the metal particles. Another aspect of the present invention is a mixture for the formation of an electrical conductor on or in a substrate. Another aspect of the present invention is an electronic device.

Abstract: In accordance with an embodiment, a structure comprises a substrate having a first area and a second area; a through substrate via (TSV) in the substrate penetrating the first area of the substrate; an isolation layer over the second area of the substrate, the isolation layer having a recess; and a conductive material in the recess of the isolation layer, the isolation layer being disposed between the conductive material and the substrate in the recess.

Abstract: An integrated circuit structure includes a semiconductor substrate; an interconnect structure over the semiconductor substrate, wherein the interconnect structure comprises a top inter-metal dielectric (IMD); an opening penetrating the interconnect structure into the semiconductor substrate; a conductor in the opening; and an isolation layer having a vertical portion and a horizontal portion physically connected to each other. The vertical portion is on sidewalls of the opening. The horizontal portion is directly over the interconnect structure. The integrated circuit structure is free from passivation layers vertically between the top IMD and the horizontal portion of the isolation layer.

Abstract: It is an object of the present invention to provide a technology for forming an ULSI fine copper wiring by a simpler method. An electronic component in which a thin alloy film of tungsten and a noble metal used as a barrier-seed layer for an ULSI fine copper wiring is formed on a base material, wherein the thin alloy film has a composition comprising tungsten at a ratio equal to or greater than 50 at. % and the noble metal at a ratio of equal to or greater than 5 at. % and equal to or less than 50 at. %. The noble metal is preferably one or more kinds of metals selected from the group consisting of ruthenium, rhodium, and iridium.

Abstract: A semiconductor device and related method for fabricating the same include providing a stacked structure including an insulating base layer and lower and upper barrier layers with a conductive layer in between, etching the stacked structure to provide a plurality of conductive columns that each extend from the lower barrier layer, each of the conductive columns having an overlying upper barrier layer cap formed from the etched upper barrier layer, wherein the lower barrier layer is partially etched to provide a land region between each of the conductive lines, forming a liner layer over the etched stacked structure exposing the land region, and etching the liner layer and removing the exposed land region to form a plurality of conductive lines.

Abstract: A three-dimensional interconnect includes a first substrate bonded to a second substrate, the first substrate including a device layer and a bulk semiconductor layer, a metal pad disposed on the second substrate, an electrically insulating layer disposed between the first and second substrates. The structure has a via-hole extending through the device layer, the bulk semi-conductor layer and the electrically insulating layer to the metal pad on the second substrate. The structure has a dielectric coating on a sidewall of the via-hole, and a plasma-treated region of the metal pad disposed on the second substrate. The structure includes a via metal monolithically extending from the plasma-treated region of the metal pad through the via-hole and electrically interconnecting the device layer of the first substrate to the metal pad of the second substrate.

Abstract: A semiconductor device includes a wiring, a stack of first, second, and third films, and a contact plug. The stack of first, second, and third films is located over the wiring. The first, second, and third films are stacked in this order. The stack has an opening. The first film is made of the same material as the third film. The contact plug is in the opening. The contact plug is in contact with the wiring.

Abstract: Partial air gap formation for providing interconnect isolation in integrated circuits is described. One embodiment is an integrated circuit (“IC”) structure includes a substrate having two adjacent interconnect features formed thereon; caps formed over and aligned with each of the interconnect features; sidewalls formed on opposing sides of each of the interconnect features and a gap formed between the interconnect features; and a dielectric material layer disposed over the substrate to cover the caps and the gap.

Abstract: A semiconductor device includes an insulating film including oxygen formed over a semiconductor substrate, a recess formed in the insulating film, a refractory metal film formed on the inner wall of the recess, a metal film including copper, manganese, and nitrogen formed on the refractory metal film, and a copper film formed on the metal film to fill in the recess.

Abstract: A method for fabricating an integrated circuit (IC) chip includes forming a metal trace having a thickness of between 5 ?m and 27 ?m over a semiconductor substrate, and forming a passivation layer on the metal trace, wherein the passivation layer includes a layer of silicon nitride on the metal trace and a layer of silicon oxide on the layer of silicon nitride, or includes a layer of silicon oxynitride on the metal trace and a layer of silicon oxide on the layer of silicon oxynitride.

Abstract: A Cu—Fe—P alloy sheet that is provided with the high strength and with the improved resistance of peel off of oxidation film, in order to deal with problems such as package cracks and peeling, is provided. A copper alloy sheet for electric and electronic parts according to the present invention is a copper alloy sheet containing Fe: 0.01 to 0.50 mass % and P: 0.01 to 0.15 mass %, respectively, with the remainder of Cu and inevitable impurities. A centerline average roughness Ra is 0.2 ?m or less and a maximum height Rmax is 1.5 ?m or less, and Kurtosis (degree peakedness) Rku of roughness curve is 5.0 or less, in measurement of the surface roughness of the copper alloy sheet in accordance with JIS B0601.

Abstract: Incompatible materials, such as copper and nitrided barrier layers, may be adhered more effectively to one another. In one embodiment, a precursor of copper is deposited on the nitrided barrier. The precursor is then converted, through the application of energy, to copper which could not have been as effectively adhered to the barrier in the first place.

Abstract: Interconnect structures having self-aligned dielectric caps are provided. At least one metallization level is formed on a substrate. A dielectric cap is selectively deposited on the metallization level.

Abstract: The invention provides a semiconductor chip comprising an interconnecting structure over said passivation layer. The interconnecting structure comprises a first contact pad connected to a second contact pad exposed by an opening in a passivation layer.

Abstract: In processes after a TSV is formed, occasionally, cracks appear in an insulation film after the insulation film that is a film for preventing Cu from diffusing is formed and the exposed Cu discolors at a succeeding process of pattern forming such as etching or asking. It is estimated that the problems occur because the volume of Cu expands by heat history at the process of forming a diffusion preventive film. When such film cracking occurs, various problems such as the destruction of the function of a Cu diffusion preventive film and conduction fault with upper wiring caused by the oxidation of Cu at the upper part of a TSV are induced.

Abstract: A method of manufacturing a semiconductor device has forming, in a dielectric film, a first opening and a second opening located in the first opening, forming a first metal film containing a first metal over a whole surface, etching the first metal film at a bottom of the second opening using a sputtering process and forming a second metal film containing a second metal over the whole surface, and burying a conductive material in the second opening and the first opening.

Abstract: The substrate with through silicon plugs (or vias) described above removes the need for conductive bumps. The process flow is very simple and cost efficient. The structures described combines the separate TSV, redistribution layer, and conductive bump structures into a single structure. By combining the separate structures, a low resistance electrical connection with high heat dissipation capability is created. In addition, the substrate with through silicon plugs (or vias, or trenches) also allows multiple chips to be packaged together. A through silicon trench can surround the one or more chips to provide protection against copper diffusing to neighboring devices during manufacturing. In addition, multiple chips with similar or different functions can be integrated on the TSV substrate. Through silicon plugs with different patterns can be used under a semiconductor chip(s) to improve heat dissipation and to resolve manufacturing concerns.

Abstract: A multi-layered metal interconnection includes a diffusion barrier directly formed on a conductive layer, an etching stop layer directly formed on the diffusion barrier, at least one dielectric layer formed over the etch stop layer, at least one of a via formed in the at least one dielectric layer and a trench formed in the at least one dielectric layer.

Abstract: In a method of forming a wiring structure for a semiconductor device, an insulation layer is formed on a semiconductor substrate on which a plurality of conductive structures is positioned. An upper surface of the insulation layer is planarized and spaces between the conductive structures are filled with the insulation layer. The insulation layer is partially removed from the substrate to form at least one opening through which the substrate is partially exposed. A residual metal layer is formed on a bottom and a lower portion of the sidewall of the at least one opening and a metal nitride layer is formed on the residual metal layer and an upper sidewall of the opening with a metal material. Accordingly, an upper portion of the barrier layer can be prevented from being removed in a planarization process for forming the metal plug.

Abstract: An interconnect structure is provided, including a layer of dielectric material having at least one opening and a first barrier layer on sidewalls defining the opening. A ruthenium-containing second barrier layer overlays the first barrier layer, the second barrier layer having a ruthenium zone, a ruthenium oxide zone, and a ruthenium-rich zone. The ruthenium zone is interposed between the first barrier layer and the ruthenium oxide zone. The ruthenium oxide zone is interposed between the ruthenium zone and the ruthenium-rich zone.

Abstract: According to one embodiment, a semiconductor device includes a first contact, a second contact, and an intermediate interconnection. The first contact is made of a first conductive material. The second contact is made of a second conductive material. A lower end portion of the second contact is connected to an upper end portion of the first contact. The intermediate interconnection is made of a third conductive material and isolated from the first contact and the second contact. A lower face of the intermediate interconnection is positioned higher than a lower face of the first contact. An upper face of the intermediate interconnection is positioned lower than an upper face of the second contact. A diffusion coefficient of the first conductive material with respect to the second conductive material is lower than a diffusion coefficient of the third conductive material with respect to the second conductive material.

Abstract: A method is provided for fabricating a microelectronic element having an air gap in a dielectric layer thereof. A dielectric cap layer can be formed which has a first portion overlying surfaces of metal lines, the first portion extending a first height above a height of a surface of the dielectric layer and a second portion overlying the dielectric layer surface and extending a second height above the height of the surface of the dielectric layer, the second height being greater than the first height. After forming the cap layer, a mask can be formed over the cap layer. The mask can have a multiplicity of randomly disposed holes. Each hole may expose a surface of only the second portion of the cap layer which has the greater height. The mask may fully cover a surface of the first portion of the cap layer having the lower height. Subsequently, an etchant can be directed towards the first and second portions of the cap layer to form holes in the cap layer aligned with the holes in the mask.

Abstract: A semiconductor device includes an interlayer dielectric film, a passivation film, made of an insulating material, formed on the interlayer dielectric film, an uppermost wire, made of a material mainly composed of copper, formed between the surface of the interlayer dielectric film and the passivation film, and a wire covering film, made of a material mainly composed of aluminum, interposed between the passivation film and the surface of the uppermost wire for covering the surface of the uppermost wire.

Abstract: A semiconductor device according to the present invention includes a semiconductor substrate, and an interlayer dielectric film, formed on the semiconductor substrate, having a multilayer structure of a compressive stress film and a tensile stress film.

Abstract: Incompatible materials, such as copper and nitrided barrier layers, may be adhered more effectively to one another. In one embodiment, a precursor of copper is deposited on the nitrided barrier. The precursor is then converted, through the application of energy, to copper which could not have been as effectively adhered to the barrier in the first place.

Abstract: Provided is a film-forming method for performing a film-forming process on a surface of a target substrate to be processed in an evacuable processing chamber, a recessed portion being formed on the surface of the target substrate. The method includes a transition metal-containing film processing process in which a transition metal-containing film is formed by a heat treatment by using a source gas containing a transition metal; and a metal film forming process in which a metal film containing an element of the group VIII of the periodic table is formed.

Abstract: Provided is a high-purity copper or high-purity copper alloy sputtering target of which the purity is 6N or higher and in which the content of the respective components of P, S, O and C is 1 ppm or less, wherein the number of nonmetal inclusions having a particle size of 0.5 ?m or more and 20 ?m or less is 30,000 inclusions/g or less. As a result of using high-purity copper or high-purity copper alloy from which harmful inclusions of P, S, C and O system have been reduced as the raw material and controlling the existence form of nonmetal inclusions, the present invention addresses a reduction in the percent defect of wirings of semiconductor device formed by sputtering a high-purity copper target so as to ensure favorable repeatability.

Abstract: The present invention provides a semiconductor device with a metal-to-contact overlay structure. The semiconductor device includes a substrate, a dielectric layer on the substrate, a contact coupled to the substrate in the dielectric layer, a first conductive region on the contact in the dielectric layer, a dielectric sidewall on the contact in the dielectric layer, the dielectric sidewall surrounding the first conductive region, and a second conductive region on the first conductive region on the dielectric layer.

Abstract: A method for manufacturing a semiconductor device includes providing a substrate including pattern formed over the substrate and a first insulating layer formed over the pattern. A diffusion barrier layer is formed over the first insulation layer. A second insulating layer is formed over the diffusion barrier layer. The second insulating layer, the diffusion layer, and the first insulating layer are patterned to form a trench exposing the pattern. A metal layer is formed over the second insulating layer and within the trench to define a metal interconnection pattern coupling the pattern within the trench, the metal particles from the metal layer diffuse into the second insulating layer. The second insulation layer and the metal particles that have been diffused therein are removed.

Abstract: A method for plating copper onto a semiconductor integrated circuit device substrate by forming an initial metal deposit in the feature which has a profile comprising metal on the bottom of the feature and a segment of the sidewalls having essentially no metal thereon, electrolessly depositing copper onto the initial metal deposit to fill the feature with copper. A method for plating copper onto a semiconductor integrated circuit device substrate by forming a deposit comprising a copper wettable metal in the feature, forming a copper-based deposit on the top-field surface, and depositing copper onto the deposit comprising the copper wettable metal to fill the feature with copper.

Abstract: The present invention provides a semiconductor device, including a silicon-containing material, a conductive layer deposited on the silicon-containing material, and a diffusion barrier layer interposed between the silicon-containing material and the conductive layer, wherein the diffusion barrier layer contains a rare earth scandate. The present invention further provides a damascene structure containing the rare earth scandate as diffusion barrier.

Abstract: Methods and an apparatus are described for an integrated circuit within which an electroless Cu plated layer having an oxygen content is formed on the top of a seed layer comprising Cu and Mn. The integrated circuit is then exposed to a sufficient high temperature to cause the self-formation of a MnSiOx barrier layer.

Abstract: In a semiconductor device, capacitance between copper interconnections is decreased and the insulation breakdown is improved simultaneously, and a countermeasure is taken for misalignment via by a manufacturing method including the steps of forming an interconnection containing copper as a main ingredient in an insulative film above a substrate, forming insulative films and a barrier insulative film for a reservoir pattern, forming an insulative film capable of suppressing or preventing copper from diffusing on the upper surface and on the lateral surface of the interconnection and above the insulative film and the insulative film, forming insulative films of low dielectric constant, in which the insulative film is formed such that the deposition rate above the opposing lateral surfaces of the interconnections is larger than the deposition rate therebelow to form an air gap between the adjacent interconnections and, finally, planarizing the insulative film by interlayer CMP.

Abstract: An integrated circuit structure having improved resistivity and a method for forming the same are provided. The integrated circuit structure includes a dielectric layer, an opening in the dielectric layer, an oxide-based barrier layer directly on sidewalls of the opening, and conductive materials filling the remaining portion of the opening.

Abstract: Disclosed is an improved integrated circuit wiring structure configured to prevent migration of wiring metal ions (e.g., copper (Cu+) ions in the case of a copper interconnect scheme) onto the surface of an interlayer dielectric material at an interface between the interlayer dielectric material and an insulating cap layer. Specifically, the top surfaces of wires and the top surface of a dielectric layer within which the wires sit are not co-planar. Thus, the interfaces between the wires and an insulating cap layer and between the dielectric layer and the same insulating cap layer are also not co-planar. Such a configuration physically prevents migration of wiring metal ions from the top surface of the wires onto the top surface of the dielectric layer at the interface between the dielectric layer and cap layer and, thereby prevents time dependent dielectric breakdown (TDDB) and eventual device failure. Also disclosed herein are embodiments of a method of a forming such an integrated circuit wiring structure.

Abstract: A process to produce an airgap on a substrate having a dielectric layer comprises defining lines by lithography where airgaps are required. The lines' dimensions are shrunk by a trimming process (isotropic etching). The tone of the patterns is reversed by applying a planarizing layer which is etched down to the top of the patterns. The photoresist is removed, leading to sub-lithographic trenches which are transferred into a cap layer and eventually into the dielectric between two metal lines. The exposed dielectric is eventually damaged, and is etched out, leading to airgaps between metal lines. The gap is sealed by the pinch-off occurring during the deposition of the subsequent dielectric.

Abstract: A semiconductor substrate has a front surface and a back surface, and a TSV structure is formed to extend through the semiconductor substrate. The TSV structure includes a metal layer, a metal seed layer surrounding the metal layer, a barrier layer surrounding the metal seed layer, and a block layer formed in a portion sandwiched between the metal layer and the metal seed layer. The block layer includes magnesium (Mg), iron (Fe), cobalt (Co), nickel (Ni), titanium (Ti), chromium (Cr), tantalum (Ta), tungsten (W), cadmium (Cd), or combinations thereof.

Abstract: A method for capping lines includes forming a metal film layer on a copper line by a selective deposition process, the copper line disposed in a dielectric substrate, wherein the depositing also results in the deposition of stray metal material on the surface of the dielectric substrate, and etching with an isotropic etching process to remove a portion of the metal film layer and the stray metal material on the surface of the dielectric substrate, wherein the metal film layer is deposited at an initial thickness sufficient to leave a metal film layer cap remaining on the copper line following the removal of the stray metal material.

Abstract: A copper interconnect includes a copper layer formed in a dielectric layer. A glue layer is formed between the copper layer and the dielectric layer. A barrier layer is formed at the boundary between the glue layer and the dielectric layer. The barrier layer is a metal oxide.

Abstract: An integrated circuit structure having improved resistivity and a method for forming the same are provided. The integrated circuit structure includes a dielectric layer, an opening in the dielectric layer, an oxide-based barrier layer directly on sidewalls of the opening, and conductive materials filling the remaining portion of the opening.