Abstract: The method of manufacturing a semiconductor device includes forming an insulating film of a silicon compound-group insulation film; forming an opening in the insulation film, applying an active energy beam in an atmosphere containing hydrocarbon gas to form a barrier layer of a crystalline SiC, and forming an interconnection structure of copper in the opening with the barrier layer formed in.

Abstract: A copper wiring of a semiconductor device is which is resistant to unwanted diffusion of copper from away from the copper wiring is presented. The copper wiring includes an interlayer dielectric, a self-assembly monolayer, a plurality of catalyst particles, a metal layer, and a copper layer. The interlayer dielectric on the semiconductor substrate has a wiring forming region. The self-assembly monolayer is the wiring forming region. The plurality of catalyst particles are adsorbed onto the surface of the self-assembly monolayer. The metal layer is formed on the self-assembly monolayer which has the adsorbed catalyst particles such that the metal layer serves as both a seed layer and as a diffusion barrier. The copper layer substantially fills in the wiring forming region.

Abstract: The semiconductor device includes a first interconnect layer insulating film, first copper interconnects that are embedded in the first interconnect layer insulating film, and an interlayer insulating film that is formed on the first copper interconnects and the first interconnect layer insulating film. The semiconductor device includes a second interconnect layer insulating film that is formed on the interlayer insulating film and second copper interconnects that are embedded in the second interconnect layer insulating film. The first and second interconnect layer insulating films include first and second low dielectric constant films, respectively. The interlayer insulating film has higher mechanical strength than the first and second interconnect layer insulating films.

Abstract: An integrated circuit includes a substrate. A surface region of the substrate includes a contact pad region. A passivation layer stack includes at least one passivation layer. The passivation layer stack is formed over the surface region and adjacent to the contact pad region. An upper portion of the passivation layer stack is removed in, in a portion of the passivation layer stack proximate the contact pad region.

Abstract: A three-dimensional (3D) chip stack structure and method of fabricating the structure thereof are provided. The 3D chip stack structure includes a plurality of vertically stacked chips which are interconnected and bonded together, wherein each of the vertically stacked chips include one or more IC device strata. The 3D chip stack structure further includes an air channel interconnect network embedded within the chip stack structure, and wherein the air channel interconnect network is formed in between at least two wafers bonded to each other of the vertically stacked wafers and in between at least two bonded wafers of the vertically stacked wafers at a bonding interface thereof.

Abstract: The present disclosure relates to methods and solutions for growing metal charge-transfer salts on a metal surface, such as a metal layer at the bottom of a via hole. The method makes use of a solution comprising a salt additive. The temperature during growth is in the range of ?100° C. to +100° C. The method allows controlled growth of the metal charge transfer salt inside via hole while limiting growth outside the via hole. The method further limits corrosion of the metallic connections at the bottom of the via hole.

Abstract: An integrated circuit structure includes a semiconductor substrate; a metallization layer over the semiconductor substrate; a first dielectric layer between the semiconductor substrate and the metallization layer; a second dielectric layer between the semiconductor substrate and the metallization layer, wherein the second dielectric layer is over the first dielectric layer; and a contact plug with an upper portion substantially in the second dielectric layer and a lower portion substantially in the first dielectric layer. The contact plug is electrically connected to a metal line in the metallization layer. The contact plug is discontinuous at an interface between the upper portion and the lower portion.

Abstract: The invention relates to a circuit arrangement with an electronic circuit on a printed circuit board and an electrically screening housing surrounding the circuit board, wherein there are on said circuit board a HF plug-and-socket connector connected to the electronic circuit with an outer conductor part and an inner conductor part, wherein the HF plug-and-socket connector penetrates through an opening in the housing. The outer conductor part of the HF plug-and-socket connector is electrically isolated from the housing, and wherein a tunnel-like screening sleeve surrounds the outer conductor part both axially and circumferentially at least partially, the sleeve being connected electrically to the housing and capacitively to the outer conductor part of the HF plug-and-socket connector.

Abstract: By forming an aluminum nitride layer by a self-limiting process sequence, the interface characteristics of a copper-based metallization layer may be significantly enhanced while nevertheless maintaining the overall permittivity of the layer stack at a lower level.

Abstract: According to an exemplary embodiment, a semiconductor die including at least one deep silicon via is provided. The deep silicon via comprises a deep silicon via opening that extends through at least one pre-metal dielectric layer of the semiconductor die, at least one epitaxial layer of the semiconductor die, and partially into a conductive substrate of the semiconductor die. The deep silicon via further comprises a conductive plug situated in the deep silicon via opening and forming an electrical contact with the conductive substrate. The deep silicon via may include a sidewall dielectric layer and a bottom conductive layer. A method for making a deep silicon via is also disclosed. The deep silicon via is used to, for example, provide a ground connection for power transistors in the semiconductor die.

Abstract: The invention concerns a method of forming a copper portion surrounded by an insulating material in an integrated circuit structure, the insulating material being a first oxide, the method having steps including forming a composite material over a region of the insulating material where the copper portion is to be formed, the composite material having first and second materials, annealing such that the second material reacts with the insulating material to form a second oxide that provides a diffusion barrier to copper; and depositing a copper layer over the composite material by electrochemical deposition to form the copper portion.

Abstract: A copper interconnect includes a copper layer formed in a dielectric layer, having a first portion and a second portion. A first barrier layer is formed between the first portion of the copper layer and the dielectric layer. A second barrier layer is formed at the boundary between the second portion of the copper layer and the dielectric layer. The first barrier layer is a dielectric layer, and the second barrier layer is a metal oxide layer.

Abstract: A method of manufacturing a semiconductor device includes forming a plurality of dummy line patterns arranged at a first pitch on an underlying region, forming first mask patterns having predetermined mask portions formed on long sides of the dummy line patterns, each of the first mask patterns having a closed-loop shape and surrounding each of the dummy line patterns, removing the dummy line patterns, forming a second mask pattern having a first pattern portion which covers end portions of the first mask patterns and inter-end portions each located between adjacent ones of the end portions, etching the underlying region using the first mask patterns and the second mask pattern as a mask to form trenches each located between adjacent ones of the predetermined mask portions, and filling the trenches with a predetermined material.

Abstract: It is an object of the present invention to provide a technology for forming an ULSI fine copper wiring by a simpler method. An electronic component in which a thin alloy film of tungsten and a noble metal used as a barrier-seed layer for an ULSI fine copper wiring is formed on a base material, wherein the thin alloy film has a composition comprising tungsten at a ratio equal to or greater than 50 at. % and the noble metal at a ratio of equal to or greater than 5 at. % and equal to or less than 50 at. %. The noble metal is preferably one or more kinds of metals selected from the group consisting of ruthenium, rhodium, and iridium.

Abstract: The present invention provides a flip-chip package substrate and a method for fabricating a flip-chip package substrate comprising a circuit build-up structure, which comprises at least a dielectric layer and at least a circuit layer, wherein each dielectric layer comprises a first surface and a second surface, plural vias are formed in the first surface, the circuit layer is formed on the first surface and in the vias to electrically connect to another circuit layer disposed under the dielectric layer; a metal layer embedded in the exposed second surface of the circuit build-up structure without protruding the exposed second surface and connected to the circuit layer; and two solder masks disposed on the exposed first surface and the exposed second surface of the circuit build-up structure, wherein the solder masks have plural openings to separately expose part of the circuit layer and the metal layer functioning as conductive pads.

Abstract: A semiconductor device in which the resistance of a copper wiring to electromigration is increased. The copper wiring is formed so that copper grains will be comparatively large in a central portion of the copper wiring and so that copper grains will be comparatively small in an upper portion and a lower portion of the metal wiring. The copper wiring having this structure is formed by a damascene method. This structure can be formed by controlling electric current density at electroplating time. With the copper wiring having this structure, it is easier for an electric current to run through the central portion than to run through the upper portion. As a result, the diffusion of copper atoms in the upper portion is suppressed and therefore the diffusion of copper atoms from an interface between the copper wiring and a cap film is suppressed.

Abstract: To provide a semiconductor device having a structure in which a barrier metal film containing nitrogen is formed in a connection surface between a copper alloy wiring and a via, in which the electric resistance between the copper alloy wiring and the via can be prevented from rising, and the electric resistance can be prevented from varying. A semiconductor device according to the present invention comprises a first copper alloy wiring, a via and a first barrier metal film. The first copper alloy wiring is formed in an interlayer insulation film and contains a predetermined additive element in a main component Cu. The via is formed in an interlayer insulation film and electrically connected to the upper surface of the first copper alloy wiring. The first barrier metal film is formed so as to be in contact with the first copper alloy wiring in the connection part between the first copper alloy wiring and the via and contains nitrogen.

Abstract: A method for forming an interconnect structure for copper metallization and an interconnect structure containing a metal nitride diffusion barrier are described. The method includes providing a substrate having a micro-feature opening formed within a dielectric material and forming a metal nitride diffusion barrier containing ruthenium, nitrogen, and a nitride-forming metal over the surfaces of the micro-feature. The nitride-forming metal is selected from Groups IVB, VB, VIB, and VIIB of the Periodic Table, and the metal nitride diffusion barrier is formed by exposing the substrate to a precursor of the nitride-forming metal, a nitrogen precursor, and a ruthenium precursor.

Abstract: A method of activating a metal structure on an intermediate semiconductor device structure toward metal plating. The method comprises providing an intermediate semiconductor device structure comprising at least one first metal structure and at least one second metal structure on a semiconductor substrate. The at least one first metal structure comprises at least one aluminum structure, at least one copper structure, or at least one structure comprising a mixture of aluminum and copper and the at least one second metal structure comprises at least one tungsten structure. One of the at least one first metal structure and the at least one second metal structure is activated toward metal plating without activating the other of the at least one first metal structure and the at least one second metal structure. An intermediate semiconductor device structure is also disclosed.

Abstract: An interconnection structure includes a lower layer metal wire in a first inter-metal dielectric layer on a substrate; a second inter-metal dielectric layer on the first inter-metal dielectric layer and covering the lower layer metal wire; an upper layer metal wire on the second inter-metal dielectric layer; and a via interconnection structure in the second inter-metal dielectric layer for interconnecting the upper layer metal wire with the lower layer metal wire, wherein the via interconnection structure comprises a tungsten stud on the lower layer metal wire, and an aluminum plug stacked on the tungsten stud.

Abstract: A through-silicon via (TSV) structure and process for forming the same are disclosed. A semiconductor substrate has a front surface and a back surface, and a TSV structure is formed to extend through the semiconductor substrate. The TSV structure includes a metal layer, a metal seed layer surrounding the metal layer, a barrier layer surrounding the metal seed layer, and a metal silicide layer formed in a portion sandwiched between the metal layer and the metal seed layer.

Abstract: A method of fabricating a copper interconnect on a substrate is disclosed in which the interconnect and substrate are subjected to a low temperature anneal subsequent to polarization of the interconnect and prior to deposition of an overlying dielectric layer. The low temperature anneal inhibits the formation of hillocks in the copper material during subsequent high temperature deposition of the dielectric layer. Hillocks can protrude through passivation layer, thus causing shorts within the connections of the semiconductor devices formed on the substrate. In one example, the interconnect and substrate are annealed at a temperature of about 200° C. for a period of about 180 seconds in a forming gas environment comprising hydrogen (5 parts per hundred) and nitrogen (95 parts per hundred).

Abstract: Provided are a wire structure, a method for fabricating a wire, a thin film transistor (TFT) substrate, and a method for fabricating a TFT substrate. The wire structure includes a barrier layer formed on a substrate and including copper nitride and a copper conductive layer formed on the barrier layer and including copper or a copper alloy.

Abstract: It is an object of the present invention to prevent an influence of voltage drop due to wiring resistance, trouble in writing of a signal into a pixel, and trouble in gray scales, and provide a display device with higher definition, represented by an EL display device and a liquid crystal display device. In the present invention, a wiring including Cu is provided as an electrode or a wiring used for the display device represented by the EL display device and the liquid crystal display device. Besides, sputtering is performed with a mask to form the wiring including Cu. With such structure, it is possible to reduce the voltage drop and a deadened signal.

Abstract: A plastic package includes a plurality of terminal members each having an outer terminal, an inner terminal, and a connecting part connecting the outer and the inner terminal; a semiconductor device provided with terminal pads connected to the inner terminals with bond wires; and a resin molding sealing the terminal members, the semiconductor device and the bond wires therein. The inner terminals of the terminal members are thinner than the outer terminals and have contact surfaces. The upper, the lower and the outer side surfaces of the outer terminals, and the lower surfaces of the semiconductor device are exposed outside. The inner terminals, the bond wires, the semiconductor device and the resin molding are included in the thickness of the outer terminals.

Abstract: A semiconductor device of improved stress-migration resistance and reliability includes an insulating film having formed therein a lower interconnection consisting of a barrier metal film and a copper-silver alloy film, on which is then formed an interlayer insulating film. In the interlayer insulating film is formed an upper interconnection consisting of a barrier metal film and a copper-silver alloy film. The lower and the upper interconnections are made of a copper-silver alloy which contains silver in an amount more than a solid solution limit of silver to copper.

Abstract: An interconnecting structure production method includes providing a substrate, forming a semiconductor layer on the substrate, forming a doped semiconductor layer on the semiconductor layer, the doped semiconductor layer containing a dopant, forming an oxide layer in a surface of the doped semiconductor layer by heating the surface of the doped semiconductor layer in atmosphere of an oxidizing gas with a water molecule contained therein, forming an alloy layer on the oxide layer, and forming an interconnecting layer on the alloy layer.

Abstract: A semiconductor structure and methods of forming the same are provided. The semiconductor structure includes a semiconductor substrate; a first dielectric layer over the semiconductor substrate; a conductive wiring in the first dielectric layer; and a copper germanide nitride layer over the conductive wiring.

Abstract: A dual damascene process is disclosed. A substrate having a base dielectric layer, a lower wiring layer inlaid in the base dielectric layer, and a cap layer capping the lower wiring layer is provided. A dielectric layer is deposited on the cap layer. A silicon oxide layer is deposited on the dielectric layer. A metal hard mask is formed on the silicon oxide layer. A trench opening is etched into the metal hard mask. A partial via feature is etched into the dielectric layer within the trench opening. The trench opening and the partial via feature are etch transferred into the dielectric layer, thereby forming a dual damascene opening, which exposes a portion of the cap layer. A liner removal step is performed to selectively remove the exposed cap layer from the dual damascene opening by employing CF4/NF3 plasma.

Abstract: A plurality of metal interconnects incorporating a Group II element alloy for protecting the metal interconnects and methods to form and incorporate the Group II element alloy are described. In one embodiment, a Group II element alloy is used as a seed layer, or a portion thereof, which decreases the line resistance and increases the mechanical strength of a metal interconnect. In another embodiment, a Group II element alloy is used to form a barrier layer, which, in addition to decreasing the line resistance and increasing the mechanical integrity, also increases the chemical integrity of a metal interconnect.

Abstract: A system and a method for protecting through-silicon vias (TSVs) is disclosed. An embodiment comprises forming an opening in a substrate. A liner is formed in the opening and a barrier layer comprising carbon or fluorine is formed along the sidewalls and bottom of the opening. A seed layer is formed over the barrier layer, and the TSV opening is filled with a conductive filler. Another embodiment includes a barrier layer formed using atomic layer deposition.

Abstract: Incompatible materials, such as copper and nitrided barrier layers, may be adhered more effectively to one another. In one embodiment, a precursor of copper is deposited on the nitrided barrier. The precursor is then converted, through the application of energy, to copper which could not have been as effectively adhered to the barrier in the first place.

Abstract: An integrated circuit (IC) may include a substrate, a first dielectric layer adjacent the substrate, and at least one trench in the first dielectric layer. The IC may also include a metal liner within the at least one trench, and a first conductive region including copper within the at least one trench. A cap layer including metal may be provided on the first conductive region. A second dielectric layer may be over the first conductive region and the cap layer. A dielectric etch stop and diffusion barrier layer may be over the second dielectric layer, and a via may be over the first conductive region and through the second dielectric layer and the cap layer. A diffusion barrier layer may be on sidewalls of the via, and an alloy seed layer including copper and at least one of tantalum, molybdenum, chromium, and tungsten may be over the diffusion barrier.

Abstract: In a semiconductor device, an insulating interlayer having a groove is formed on an insulating underlayer. A silicon-diffused metal layer including no metal silicide is buried in the groove. A metal diffusion barrier layer is formed on the silicon-diffused metal layer and the insulating interlayer.

Abstract: Described is a method and apparatus for forming interconnects with a metal-metal oxide electromigration barrier and etch-stop. In one embodiment of the invention, the method includes depositing a metal layer on the top of a planarized interconnect layer, the interconnect layer having an interlayer dielectric (ILD) with a top that is planar with the top of an electrically conductive interconnect. In one embodiment of the invention, the method includes reacting the metal layer with the ILD to form a metal oxide layer on the top of the ILD. At the same time, the metal layer will not be significantly oxidized by the electrically conductive interconnect, thus forming a metal barrier on the electrically conductive interconnect to improve electromigration performance. The metal barrier and metal oxide layer together comprise a protective layer. A second ILD may be subsequently formed on the protective layer, and the protective layer may act an etch-stop during a subsequent etch of the second ILD.

Abstract: A porous silica precursor composition is herein provided and the precursor composition comprises an organic silane represented by the following chemical formula 1: R1m(R2—O)4?mSi (in the formula, R1 and R2 may be the same or different and each represent an alkyl group, and m is an integer ranging from 0 to 3); water; an alcohol; and a quaternary ammonium compound represented by the following chemical formula 2: R3N(R4)3X (in the formula, R3 and R4 may be the same or different and each represent an alkyl group and X represents a halogen atom). The composition is prepared by a method comprising the step of blending the foregoing components. The porous silica precursor composition is coated on a substrate and then fired to thus form a porous silica film. Also disclosed herein include a semiconductor element, an apparatus for displaying an image and a liquid crystal display, each having the foregoing porous silica film.

Abstract: An integrated circuit structure includes a semiconductor substrate, a through-silicon via (TSV) extending into the semiconductor substrate, a pad formed over the semiconductor substrate and spaced apart from the TSV, and an interconnect structure formed over the semiconductor substrate and electrically connecting the TSV and the pad. The interconnect structure includes an upper portion formed on the pad and a lower portion adjacent to the pad, and the upper portion extends to electrically connect the TSV.

Abstract: One or more embodiments of the present invention relates to a method for passivating metallic interconnects, said method including: forming a metallic conductor embedded in at least one surrounding dielectric layer, said metallic conductor including a metal or alloy chosen from a group consisting of Cu, Ag, and alloys including one or more of these metals, said metallic conductor and said at least one surrounding dielectric layer having top surfaces; and forming a capping passivation film directly on the top surface of the metallic conductor, but not over the top surface of the at least one surrounding dielectric layer, wherein said capping passivation film including one or more materials selected from the group consisting of copper sulfide, silver sulfide, copper selenide, silver selenide, copper telluride, and silver telluride, wherein the copper sulfide refers to CuSX or Cu2SX, the silver sulfide refers to AgSX or Ag2SX, the copper selenide refers to CuSeXor Cu2SeX, and the copper telluride refers to CuTeX

Abstract: A method for producing a contact through the pre-metal dielectric (PMD) layer of an integrated circuit, between the front end of line and the back end of line, and the device produced thereby are disclosed. The PMD layer includes oxygen. In one aspect, the method includes producing a hole in the PMD, depositing a conductive barrier layer at the bottom of the hole, depositing a CuMn alloy on the bottom and side walls of the hole, filling the remaining portion of the hole with Cu. The method further includes performing an anneal process to form a barrier on the side walls of the hole, wherein the barrier has an oxide including Mn. The method further includes performing a CMP process.

Abstract: An integrated circuit structure and methods for forming the same are provided. The integrated circuit structure includes a semiconductor substrate; a dielectric layer over the semiconductor substrate; an opening in the dielectric layer; a conductive line in the opening; a metal alloy layer overlying the conductive line; a first metal silicide layer overlying the metal alloy layer; and a second metal silicide layer different from the first metal silicide layer on the first metal silicide layer. The metal alloy layer and the first and the second metal silicide layers are substantially vertically aligned to the conductive line.

Abstract: Techniques are disclosed that enable an interconnect structure that is resistance to electromigration. A liner is deployed underneath a seed layer of the structure. The liner can be a thin continuous and conformal layer, and may also limit oxidation of an underlying barrier (or other underlying surface). A dopant that is compatible (non-alloying, non-reactive) with the liner is provided to alloy the seed layer, and allows for dopant segregation at the interface at the top of the seed layer. Thus, electromigration performance is improved.

Abstract: A trench is formed in an insulation film formed on top of a semiconductor substrate, and a barrier metal film is formed on the surface of the trench. After a copper or copper alloy film is formed on the barrier metal film, an oxygen absorption film in which a standard energy of formation of an oxidation reaction in a range from room temperature to 400° C. is negative, and in which an absolute value of the standard energy of formation is larger than that of the barrier metal film is formed, and the assembly is heated in a temperature range of 200 to 400° C. A semiconductor device can thereby be provided that has highly reliable wiring, in which the adhesion to the barrier metal film in the copper interface is enhanced, copper diffusion in the interface is suppressed, and electromigration and stress migration are prevented.

Abstract: Provided, is a reliable semiconductor device with a layered interconnect structure that may develop no trouble of voids and interconnect breakdowns, in which the layered interconnect structure comprises a conductor film and a neighboring film as so layered on a semiconductor substrate that the neighboring film is contacted with the conductor film.

Abstract: A circuit device including a multilayer wiring structure having an improved heat radiation performance, and a manufacturing method thereof is provided. A circuit device of the invention includes a first wiring layer and a second wiring layer laminated while interposing a first insulating layer. The first wiring layer is connected to the second wiring layer in a desired position through a connecting portion formed so as to penetrate the first insulating layer. The connecting portion includes a first connecting portion protruding in a thickness direction from the first wiring layer, and a second connecting portion protruding in the thickness direction from the second wiring layer. The first connecting portion and the second connecting portion contact each other at an intermediate portion in the thickness direction of the insulating layer.

Abstract: A semiconductor structure having a substrate, a seed layer over the substrate; a silicon layer disposed on the seed layer; a transistor device in the silicon layer; a III-V device disposed on the seed layer; and a plurality of electrical contacts, each one of the electrical contacts having a layer of TiN or TaN and a layer of copper or aluminum on the layer of TaN or TiN, one of the electrical contacts being electrically connected to the transistor and another one of the electrical contacts being electrically connected to the III-V device.

Abstract: A semiconductor device according to an embodiment of the present invention includes a line layer containing Cu (copper), an inter layer dielectric formed on the line layer, a via hole formed in the inter layer dielectric on the line layer, a first barrier layer formed on the line layer in the via hole, a second barrier layer formed on the first barrier layer and on a sidewall of the via hole, and a conductive layer formed on the second barrier layer and containing Al (aluminum).

Abstract: An integrated circuit structure having improved resistivity and a method for forming the same are provided. The integrated circuit structure includes a dielectric layer, an opening in the dielectric layer, an oxide-based barrier layer directly on sidewalls of the opening, and conductive materials filling the remaining portion of the opening.

Abstract: A semiconductor device includes a semiconductor substrate; an insulating film formed over the semiconductor substrate, there being formed in the insulating film a trench that in a sectional view has a stepped shape; and a wiring formed in the trench, wherein the wiring includes, a main portion with a first thickness; and an extended portion with a second thickness that is thinner than the first thickness and that extends outward from a side of the main portion.

Abstract: Disclosed are a semiconductor device having a multilayered interconnection structure formed by using a Cu damascene method, and a method of fabricating the same. A Cu interconnection is buried on a first barrier metal layer in a trench formed in the surface of an insulating film. An interlayer dielectric film is formed on the insulating film, first barrier metal layer, and Cu interconnection, and a hole is formed in a position corresponding to the Cu interconnection. An Al-based interconnection is electrically connected to the Cu interconnection in the hole of the interlayer dielectric film. A stacked film is interposed at least between the Cu interconnection and Al-based interconnection. This stacked film includes a second barrier metal layer for preventing the reaction between Cu and Al, and a third barrier metal layer for increasing the fluidity of Al with respect to the second barrier metal layer.

Abstract: A method for forming copper wirings in a semiconductor device may include depositing a lower insulating film over a semiconductor substrate; forming vias in the lower insulating film; depositing tungsten over the entire surface of upper portion of the lower insulating film so that the vias are gap-filled with the tungsten; forming tungsten plugs by performing a tungsten chemical mechanical polishing process to remove excess tungsten deposited over the upper portion of the lower insulating film; removing the tungsten remaining over the upper portion of the lower insulating film by performing a tungsten etchback process; depositing an upper insulating film over the upper portion of the lower insulating film; exposing upper portions of the tungsten plugs by forming trenches on the upper insulating film; depositing copper over the entire surface of the upper insulating film so that the trenches are gap-filled with the copper; and planarizing the copper over the upper portion of the trenches.