Principal Metal Being Copper (epo) Patents (Class 257/E23.161)
  • Patent number: 8378488
    Abstract: A semiconductor device has an interlayer insulating film that is formed on a semiconductor substrate and has a trench formed therein; a first diffusion barrier film formed on an inner surface of the trench; a Cu wiring layer buried in the trench with the first diffusion barrier film interposed between the Cu wiring layer and the inner surface of the trench; a second diffusion barrier film formed on top of the interlayer insulating film and the Cu wiring layer; an alloy layer primarily containing Cu formed at a first interface between the Cu wiring layer and the second diffusion barrier film; a first reaction layer that is formed at a second interface between the interlayer insulating film and the second diffusion barrier film; and a second reaction layer that is formed on the alloy layer and the first reaction layer.
    Type: Grant
    Filed: July 30, 2009
    Date of Patent: February 19, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Shinya Arai
  • Patent number: 8349730
    Abstract: An integrated circuit structure and methods for forming the same are provided. The integrated circuit structure includes a semiconductor substrate; a dielectric layer over the semiconductor substrate; an opening in the dielectric layer; a conductive line in the opening; a metal alloy layer overlying the conductive line; a first metal silicide layer overlying the metal alloy layer; and a second metal silicide layer different from the first metal silicide layer on the first metal silicide layer. The metal alloy layer and the first and the second metal silicide layers are substantially vertically aligned to the conductive line.
    Type: Grant
    Filed: June 25, 2010
    Date of Patent: January 8, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Hsueh Shih, Shau-Lin Shue
  • Publication number: 20130001781
    Abstract: An interconnect structure is provided which includes at least one patterned and cured low-k material located directly on a surface of a substrate; and at least one least one conductively filled region embedded within an interconnect pattern located within the at least one patterned and cured low-k material, wherein the at least one conductively filled region has an inflection point at a lower region of the interconnect pattern that is in proximity to an upper surface of the substrate and the interconnect region having an upper region that has substantially straight sidewalls.
    Type: Application
    Filed: September 1, 2012
    Publication date: January 3, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Maxime Darnon, Qinghuang Lin
  • Patent number: 8344509
    Abstract: A method for fabricating a semiconductor device, includes forming a dielectric film above a substrate; forming an opening in the dielectric film; forming a first film containing a metal whose energy for forming silicide thereof is lower than that of Cu silicide inside the opening; forming a second film that is conductive and contains copper (Cu) in the opening in which the first film containing the metal is formed; and forming a compound film containing Cu and silicon (Si) selectively on the second film in an atmosphere in which a temperature of the substrate is below 300° C.
    Type: Grant
    Filed: January 5, 2010
    Date of Patent: January 1, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yumi Hayashi, Atsuko Sakata, Kei Watanabe, Noriaki Matsunaga, Shinichi Nakao, Makoto Wada, Hiroshi Toyoda
  • Patent number: 8344352
    Abstract: Incompatible materials, such as copper and nitrided barrier layers, may be adhered more effectively to one another. In one embodiment, a precursor of copper is deposited on the nitrided barrier. The precursor is then converted, through the application of energy, to copper which could not have been as effectively adhered to the barrier in the first place.
    Type: Grant
    Filed: July 18, 2011
    Date of Patent: January 1, 2013
    Assignee: Intel Corporation
    Inventors: Juan E. Dominguez, Adrien R. Lavoie, John J. Plombon, Joseph H. Han, Harsono S. Simka
  • Publication number: 20120319282
    Abstract: Methods and apparatus for forming a semiconductor device are provided which may include any number of features. One feature is a method of forming an interconnect structure that results in the interconnect structure having a top surface and portions of the side walls of the interconnect structure covered in a dissimilar material. In some embodiments, the dissimilar material can be a conductive material or a nano-alloy. The interconnect structure can be formed by removing a portion of the interconnect structure, and covering the interconnect structure with the dissimilar material. The interconnect structure can comprise a damascene structure, such as a single or dual damascene structure, or alternatively, can comprise a silicon-through via (TSV) structure.
    Type: Application
    Filed: June 20, 2011
    Publication date: December 20, 2012
    Applicant: Tessera, Inc.
    Inventors: Cyprian Uzoh, Belgacem Haba, Craig Mitchell
  • Publication number: 20120319281
    Abstract: The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a. A groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Defective filling of the buried conductor and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented.
    Type: Application
    Filed: July 13, 2012
    Publication date: December 20, 2012
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventor: Kenichi Watanabe
  • Patent number: 8330276
    Abstract: The semiconductor device includes a first interconnect layer insulating film, first copper interconnects that are embedded in the first interconnect layer insulating film, and an interlayer insulating film that is formed on the first copper interconnects and the first interconnect layer insulating film. The semiconductor device includes a second interconnect layer insulating film that is formed on the interlayer insulating film and second copper interconnects that are embedded in the second interconnect layer insulating film. The first and second interconnect layer insulating films include first and second low dielectric constant films, respectively. The interlayer insulating film has higher mechanical strength than the first and second interconnect layer insulating films.
    Type: Grant
    Filed: July 15, 2010
    Date of Patent: December 11, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Noriaki Oda, Shinichi Chikaki
  • Patent number: 8324731
    Abstract: An integrated circuit device having at least a bond pad for semiconductor devices and method for fabricating the same are provided. A bond pad has a first passivation layer having a plurality of openings. A conductive layer which overlies the openings and portions of the first passivation layer, having a first portion overlying the first passivation layer and a second portion overlying the openings. A second passivation layer overlies the first passivation layer and covers edges of the conductive layer.
    Type: Grant
    Filed: November 23, 2009
    Date of Patent: December 4, 2012
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chen-Hua Yu, Shwang-Ming Jeng, Yung-Cheng Lu, Huilin Chang, Ting-Yu Shen, Yichi Liao
  • Patent number: 8304906
    Abstract: Partial air gap formation for providing interconnect isolation in integrated circuits is described. One embodiment is an integrated circuit (“IC”) structure includes a substrate having two adjacent interconnect features formed thereon; caps formed over and aligned with each of the interconnect features; sidewalls formed on opposing sides of each of the interconnect features and a gap formed between the interconnect features; and a dielectric material layer disposed over the substrate to cover the caps and the gap.
    Type: Grant
    Filed: May 28, 2010
    Date of Patent: November 6, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Lin Huang, Jiing-Feng Yang, Chii-Ping Chen, Dian-Hau Chen, Yuh-Jier Mii
  • Publication number: 20120273952
    Abstract: Microelectronic chip including a semiconductor substrate; at least one area of its surface which is suitable to be electrically connected to a metal frame designed to accommodate the chip; at least one interconnect area formed by a copper-based conductive layer and comprising a connecting device, the interconnect area being connected to the area by a conductor, wherein the area is formed by a layer forming a copper diffusion barrier inserted between interconnect area and the substrate.
    Type: Application
    Filed: April 25, 2012
    Publication date: November 1, 2012
    Applicants: STMicroelectronics (Crolles 2) SAS, STMicroelectronics S.A.
    Inventors: Laurent Gay, Francois Guyader, Frederic Diette
  • Publication number: 20120248609
    Abstract: An object of the invention is to fully fill a wiring material in via holes formed in a low-hardness interlayer insulating film and a high-hardness interlayer insulating film, respectively, upon forming a Cu wiring in interlayer insulating films by using the dual damascene process. According to the invention, a second interlayer insulating film has therein both a wiring trench and a via hole. The via hole has, at the opening portion thereof, a recess portion having a tapered cross-sectional shape. It is formed by causing the second interlayer insulating film to retreat obliquely downward. The diameter of the opening portion of the via hole therefore becomes greater than the diameter of a region below the opening portion and it becomes possible to fully fill a wiring material in the via hole even if the via hole has a fine diameter.
    Type: Application
    Filed: February 14, 2012
    Publication date: October 4, 2012
    Inventor: Kazuo TOMITA
  • Publication number: 20120241958
    Abstract: By forming an aluminum nitride layer by a self-limiting process sequence, the interface characteristics of a copper-based metallization layer may be significantly enhanced while nevertheless maintaining the overall permittivity of the layer stack at a lower level.
    Type: Application
    Filed: June 4, 2012
    Publication date: September 27, 2012
    Inventors: CHRISTOF STRECK, Volker Kahlert
  • Publication number: 20120235302
    Abstract: A semiconductor manufacturing method includes: forming a seed film including a first metal over a bottom surface and a side wall of an opening portion formed over interlayer insulating films and a field portion located over the interlayer insulating film except the opening portion, forming a resist over the seed film and filling the opening portion with the resist, removing part of the resist, exposing the seed film formed over the upper portion of the side walls of the opening portion and the field portion, forming a cover film including a second metal, whose resistivity is higher than that of the first metal, over the seed film located over the upper portion of the side wall of the opening portion and the field portion, exposing the seed film by removing the resist, and forming a plating film including the first metal over the exposed seed film.
    Type: Application
    Filed: February 16, 2012
    Publication date: September 20, 2012
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventor: Akira FURUYA
  • Patent number: 8258627
    Abstract: A plurality of metal interconnects incorporating a Group II element alloy for protecting the metal interconnects and methods to form and incorporate the Group II element alloy are described. In one embodiment, a Group II element alloy is used as a seed layer, or a portion thereof, which decreases the line resistance and increases the mechanical strength of a metal interconnect. In another embodiment, a Group II element alloy is used to form a barrier layer, which, in addition to decreasing the line resistance and increasing the mechanical integrity, also increases the chemical integrity of a metal interconnect.
    Type: Grant
    Filed: June 18, 2010
    Date of Patent: September 4, 2012
    Assignee: Intel Corporation
    Inventors: Aaron A. Budrevich, Adrien R. Lavoie
  • Publication number: 20120211890
    Abstract: A metal thin film forming method includes depositing a Ti film on an insulating film formed on a substrate and depositing a Co film on the Ti film. The film forming method further includes modifying a laminated film of the Ti film and the Co film on the insulating film to a metal thin film containing Co3Ti alloy by heating the laminated film in an inert gas atmosphere or a reduction gas atmosphere.
    Type: Application
    Filed: February 2, 2012
    Publication date: August 23, 2012
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Shuji AZUMO, Yasuhiko KOJIMA
  • Publication number: 20120193799
    Abstract: A circuit substrate is presented. The circuit substrate comprises internal terminal electrode 2; a substrate 1; a wiring layer 21 formed on a portion of the surface of the substrate and having one end thereof connected to the internal terminal electrode; an insulating film contacting as a surface with the wiring layer; and an external terminal electrode 9 connected to the other end of the wiring layer and used for connecting to the exterior. The angle of the cross-section of the wiring layer taken perpendicularly to the surface of the substrate in the edge portion that the wiring layer contains is 55° (55 degree) or less, and the wiring layer that contains multiple mutually independent columnar crystals extending perpendicularly in a direction different from the direction of the surface of the substrate.
    Type: Application
    Filed: February 10, 2012
    Publication date: August 2, 2012
    Applicant: SKLink Co., Ltd.
    Inventors: Masao SAKUMA, Kanji OTSUKA
  • Patent number: 8227347
    Abstract: An interconnecting structure production method includes providing a substrate, forming a semiconductor layer on the substrate, forming a doped semiconductor layer on the semiconductor layer, the doped semiconductor layer containing a dopant, forming an oxide layer in a surface of the doped semiconductor layer by heating the surface of the doped semiconductor layer in atmosphere of an oxidizing gas with a water molecule contained therein, forming an alloy layer on the oxide layer, and forming an interconnecting layer on the alloy layer.
    Type: Grant
    Filed: April 16, 2010
    Date of Patent: July 24, 2012
    Assignee: Hitachi Cable, Ltd.
    Inventor: Noriyuki Tatsumi
  • Publication number: 20120175775
    Abstract: An integrated circuit comprising an electromigration barrier includes a line, the line comprising a first conductive material, the line further comprising a plurality of line segments separated by one or more electromigration barriers, wherein the one or more electromigration barriers comprise a second conductive material that isolates electromigration effects within individual segments of the line.
    Type: Application
    Filed: March 20, 2012
    Publication date: July 12, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: David V. Horak, Takeshi Nogami, Shom Ponoth, Chih-Chao Yang
  • Patent number: 8216933
    Abstract: A method of depositing a bilayer of tungsten over tungsten nitride by a plasma sputtering process in which krypton is used as the sputter working gas during the tungsten deposition. Argon may be used as the sputtering working gas during the reactive sputtering deposition of tungsten nitride. The beneficial effect of reduction of tungsten resistivity is increased when the thickness of the tungsten layer is less than 50 nm and further increased when less than 35 nm. The method may be used in forming a gate stack including a polysilicon layer over a gate oxide layer over a silicon gate region of a MOS transistor in which the tungsten nitride acts as a barrier. A plasma sputter chamber in which the invention may be practiced includes gas sources of krypton, argon, and nitrogen.
    Type: Grant
    Filed: August 31, 2010
    Date of Patent: July 10, 2012
    Assignee: Applied Materials, Inc.
    Inventors: Wei D. Wang, Srinivas Gandikota, Kishore Lavu
  • Publication number: 20120168953
    Abstract: A structure is provided with a self-aligned resist layer on a surface of metal interconnects for use in forming air gaps in an insulator material and method of fabricating the same. The non-lithographic method includes applying a resist on a structure comprising at least one metal interconnect formed in an insulator material. The method further includes blanket-exposing the resist to energy and developing the resist to expose surfaces of the insulator material while protecting the metal interconnects. The method further includes forming air gaps in the insulator material by an etching process, while the metal interconnects remain protected by the resist.
    Type: Application
    Filed: March 13, 2012
    Publication date: July 5, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Daniel C. EDELSTEIN, Elbert E. HUANG, Robert D. MILLER
  • Publication number: 20120161320
    Abstract: Electrical interconnects for integrated circuits and methods of fabrication of interconnects are provided. Devices are provided comprising copper interconnects having metal liner layers comprising cobalt and a metal selected from the group consisting of Ru, Pt, Ir, Pd, Re, or Rh. Devices having barrier layers comprising ruthenium and cobalt are provided. Methods include providing a substrate having a trench or via formed therein, forming a metal layer, the metal being selected from the group consisting of Ru, Pt, Ir, Pd, Re, and Rh, onto surfaces of the feature, depositing a copper seed layer comprising a cobalt dopant, and depositing copper into the feature.
    Type: Application
    Filed: December 23, 2010
    Publication date: June 28, 2012
    Inventors: Rohan N. Akolkar, James S. Clarke
  • Publication number: 20120153480
    Abstract: In sophisticated metallization systems of semiconductor devices, a sensitive core metal, such as copper, may be efficiently confined by a conductive barrier material comprising a copper/silicon compound, such as a copper silicide, which may provide superior electromigration behavior and higher electrical conductivity compared to conventionally used tantalum/tantalum nitride barrier systems.
    Type: Application
    Filed: July 27, 2011
    Publication date: June 21, 2012
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Ronny Pfuetzner, Jens Heinrich
  • Publication number: 20120146225
    Abstract: A damascene structure includes a conductive layer, a first dielectric layer, a first barrier metal layer, a barrier layer, and a second barrier metal layer sequentially formed on the conductive layer. The first dielectric layer having a via therein. The barrier layer is comprised of a material different with that of the first barrier metal layer. A bottom of the barrier layer disposed on the via bottom is not punched through. The accomplished barrier layers will have lower resistivity on the via bottom in the first dielectric layer and they are capable of preventing copper atoms from diffusing into the dielectric layer.
    Type: Application
    Filed: February 16, 2012
    Publication date: June 14, 2012
    Inventors: Yu-Ru YANG, Chien-Chung Huang
  • Patent number: 8198174
    Abstract: A three-dimensional (3D) chip stack structure and method of fabricating the structure thereof are provided. The 3D chip stack structure includes a plurality of vertically stacked chips which are interconnected and bonded together, wherein each of the vertically stacked chips include one or more IC device strata. The 3D chip stack structure further includes an air channel interconnect network embedded within the chip stack structure, and wherein the air channel interconnect network is formed in between at least two wafers bonded to each other of the vertically stacked wafers and in between at least two bonded wafers of the vertically stacked wafers at a bonding interface thereof.
    Type: Grant
    Filed: August 5, 2009
    Date of Patent: June 12, 2012
    Assignee: International Business Machines Corporation
    Inventors: Louis L. Hsu, Brian L. Ji, Fei Liu, Conal E. Murray
  • Patent number: 8198732
    Abstract: A semiconductor device of the present invention includes an insulating film made of a low dielectric constant material having a smaller specific dielectric constant than SiO2, a wiring trench formed in the insulating film, a first barrier film made of SiO2 or SiCO formed at least on the side surface of the wiring trench, Cu wiring mainly composed of Cu embedded in the wiring trench, and a second barrier film made of a compound containing Si, O and a predetermined metallic element covering the surface of the Cu wiring opposed to the wiring trench.
    Type: Grant
    Filed: May 21, 2008
    Date of Patent: June 12, 2012
    Assignee: Rohm Co., Ltd.
    Inventor: Satoshi Kageyama
  • Patent number: 8188600
    Abstract: The present invention provides a semiconductor device which is capable of enhancing adhesion at an interface between a wire-protection film and copper, suppressing dispersion of copper at the interface to avoid electromigration and stress-inducing voids, and having a highly reliable wire. An interlayer insulating film, and a first etching-stopper film are formed on a semiconductor substrate on which a semiconductor device is fabricated. A first alloy-wire covered with a first barrier metal film is formed on the first etching-stopper film by a damascene process. The first alloy-wire is covered at an upper surface thereof with a first wire-protection film. The first wire-protection film covering an upper surface of the first alloy-wire contains at least one metal among metals contained in the first alloy-wire.
    Type: Grant
    Filed: June 24, 2005
    Date of Patent: May 29, 2012
    Assignee: NEC Corporation
    Inventors: Mari Amano, Munehiro Tada, Yoshihiro Hayashi
  • Patent number: 8174121
    Abstract: A semiconductor device is provided. The semiconductor device includes a substrate in which a first interlayer insulation layer having a first via hole and a first trench is formed. The semiconductor device also includes a first via plug and a first metal line respectively formed by filling the first via hole and the first trench with a first metal, a predetermined scratch being formed on the first metal line; and a second via plug a second metal line respectively formed by filling a second via hole and a second trench with a second metal, the second metal lines being separated.
    Type: Grant
    Filed: August 27, 2008
    Date of Patent: May 8, 2012
    Assignee: Dongbu Electronics Co. Ltd.
    Inventor: Min Dae Hong
  • Publication number: 20120104613
    Abstract: It is an object of the present invention to provide a copper-based bonding wire whose material cost is low, having excellent ball bondability, reliability in a heat cycle test or reflow test, and storage life, enabling an application to thinning of a wire used for fine pitch connection. The bonding wire includes a core material having copper as a main component and an outer layer which is provided on the core material and contains a metal M and copper, in which the metal M differs from the core material in one or both of components and composition. The outer layer is 0.021 to 0.12 ?m in thickness.
    Type: Application
    Filed: January 12, 2012
    Publication date: May 3, 2012
    Applicants: NIPPON MICROMETAL CORPORATION, NIPPON STEEL MATERIALS CO., LTD.
    Inventors: Tomohiro Uno, Keiichi Kimura, Shinichi Terashima, Takashi Yamada, Akihito Nishibayashi
  • Publication number: 20120098122
    Abstract: The embodiments of methods and structures for forming through silicon vias a CMOS substrate bonded to a MEMS substrate and a capping substrate provide mechanisms for integrating CMOS and MEMS devices that use less real-estate and are more reliable. The through silicon vias electrically connect to metal-1 level of the CMOS devices. Copper metal may be plated on a barrier/Cu-seed layer to partially fill the through silicon vias, which saves time and cost. The formation method may involve using dual dielectric layers on the substrate surface as etching mask to eliminate a photolithographical process during the removal of oxide layer at the bottoms of through silicon vias. In some embodiments, the through silicon vias land on polysilicon gate structures to prevent notch formation during etching of the vias.
    Type: Application
    Filed: November 11, 2010
    Publication date: April 26, 2012
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Hsueh-An YANG
  • Publication number: 20120080791
    Abstract: One or more embodiments relate to a method of forming an electronic device, comprising: providing a workpiece; forming a first barrier layer over the workpiece; forming an intermediate conductive layer over the first barrier layer; forming a second barrier layer over the intermediate conductive layer; forming a seed layer over the second barrier layer; removing a portion of the seed layer to leave a remaining portion of the seed layer and to expose a portion of the second barrier layer; and electroplating a fill layer on the remaining portion of the seed layer.
    Type: Application
    Filed: September 30, 2010
    Publication date: April 5, 2012
    Inventors: Hans-Joachim BARTH, Gottfried BEER, Joern PLAGMANN, Jens POHL, Werner ROBL, Rainer STEINER, Mathias VAUPEL
  • Publication number: 20120074571
    Abstract: An apparatus includes an interconnect in a recess. The interconnect includes a liner structure and the liner structure in the recess. The liner structure is breached at the recess bottom feature and a bottom interconnect makes a single-interface contact with a subsequent interconnect through the breach.
    Type: Application
    Filed: September 24, 2010
    Publication date: March 29, 2012
    Inventor: Adrien R. Lavoie
  • Publication number: 20120074553
    Abstract: A method and a system for improving reliability of a semiconductor device are provided. In one embodiment, a semiconductor device is provided comprising a semiconductor chip, a metallization layer comprising a metallic material disposed over a surface of the semiconductor chip, and an alloy layer comprising the metallic material disposed over the metallization layer.
    Type: Application
    Filed: September 27, 2010
    Publication date: March 29, 2012
    Inventors: Khalil HOSSEINI, Joachim MAHLER, Manfred MENGEL
  • Publication number: 20120074574
    Abstract: One or more embodiments relate to a method of forming a semiconductor structure, comprising: providing a workpiece; forming a barrier layer over the workpiece; forming a seed layer over the barrier layer; forming an inhibitor layer over the seed layer; removing a portion of said inhibitor layer to expose a portion of the seed layer; and selectively depositing a fill layer on the exposed seed layer.
    Type: Application
    Filed: September 29, 2010
    Publication date: March 29, 2012
    Inventors: Hans-Joachim BARTH, Gottfried BEER, Joern PLAGMANN, Jens POHL, Werner ROBL, Rainer STEINER, Mathias VAUPEL
  • Publication number: 20120074573
    Abstract: One or more embodiments relate to a method of forming a semiconductor device, comprising: forming a structure, the structure including at least a first element and a second element; and forming a passivation layer over the structure, the passivation layer including at least the first element and the second element, the first element and the second element of the passivation layer coming from the structure.
    Type: Application
    Filed: September 29, 2010
    Publication date: March 29, 2012
    Inventors: Gerald DALLMANN, Heike ROSSLAU, Norbert URBANSKY, Scott WALLACE
  • Patent number: 8138604
    Abstract: An interconnect structure is provided that has enhanced electromigration reliability without degrading circuit short yield, and improved technology extendibility. The inventive interconnect structure includes a dielectric material having a dielectric constant of about 3.0 or less. The dielectric material has at least one conductive material embedded therein. A noble metal cap is located directly on an upper surface of the at least one conductive region. The noble metal cap does not substantially extend onto an upper surface of the dielectric material that is adjacent to the at least one conductive region, and the noble cap material does not be deposited on the dielectric surface. A method fabricating such an interconnect structure utilizing a low temperature (about 300° C. or less) chemical deposition process is also provided.
    Type: Grant
    Filed: June 21, 2007
    Date of Patent: March 20, 2012
    Assignee: International Business Machines Corporation
    Inventors: Chih-Chao Yang, Daniel C. Edelstein
  • Publication number: 20120061840
    Abstract: A dual damascene structure is disclosed. The dual damascene structure includes: a substrate comprising thereon a base dielectric layer and a lower wiring layer inlaid in the base dielectric layer; a dielectric layer on the substrate; a via opening in the dielectric layer, wherein the via opening misaligns with the lower wiring layer thus exposing a portion of the lower wiring layer and a portion of the base dielectric layer, wherein the via opening comprises a bottom including a recessed area; a barrier layer lining interior surface of the via opening and covers the exposed lower wiring layer and the base dielectric layer, wherein only the barrier layer fills the recessed area; and a copper layer filling the via opening on the barrier layer.
    Type: Application
    Filed: November 17, 2011
    Publication date: March 15, 2012
    Inventors: Chun-Jen Huang, Yu-Tsung Lai, Jyh-Cherng Yau, Jiunn-Hsiung Liao
  • Patent number: 8129844
    Abstract: Electronic devices and design structures of electronic devices containing metal silicide layers. The devices include: a thin silicide layer between two dielectric layers, at least one metal wire abutting a less than whole region of the silicide layer and in electrical contact with the silicide layer.
    Type: Grant
    Filed: June 20, 2008
    Date of Patent: March 6, 2012
    Assignee: International Business Machines Corporation
    Inventors: Felix Patrick Anderson, Zhong-Xiang He, Thomas Leddy McDevitt, Eric Jeffrey White
  • Publication number: 20120049371
    Abstract: A cap layer for a copper interconnect structure formed in a first dielectric layer is provided. In an embodiment, a conductive layer is located within a dielectric layer and a top surface of the conductive layer has either a recess, a convex surface, or is planar. An alloy layer overlies the conductive layer and is a silicide alloy having a first material from the conductive layer and a second material of germanium, arsenic, tungsten, or gallium.
    Type: Application
    Filed: November 7, 2011
    Publication date: March 1, 2012
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hui-Lin Chang, Hung Chun Tsai, Yung-Cheng Lu, Syun-Ming Jang
  • Patent number: 8125013
    Abstract: A semiconductor structure and design structure includes at least a first trench and a second trench having different depths arranged in a substrate, a capacitor arranged in the first trench, and a via arranged in the second trench.
    Type: Grant
    Filed: August 14, 2008
    Date of Patent: February 28, 2012
    Assignee: International Business Machines Corporation
    Inventors: David S. Collins, Kai D. Feng, Zhong-Xiang Ile, Peter J. Lindgren, Robert M. Rassel
  • Publication number: 20120043658
    Abstract: Some embodiments include methods for depositing copper-containing material utilizing physical vapor deposition of the copper-containing material while keeping a temperature of the deposited copper-containing material at greater than 100° C. Some embodiments include methods in which openings are lined with a metal-containing composition, copper-containing material is physical vapor deposited over the metal-containing composition while a temperature of the copper-containing material is no greater than about 0° C., and the copper-containing material is then annealed while the copper-containing material is at a temperature in a range of from about 180° C. to about 250° C. Some embodiments include methods in which openings are lined with a composition containing metal and nitrogen, and the lined openings are at least partially filled with copper-containing material.
    Type: Application
    Filed: August 20, 2010
    Publication date: February 23, 2012
    Inventors: Dale W. Collins, Joe Lindgren
  • Patent number: 8120181
    Abstract: A system and method for forming post passivation metal structures is described. Metal interconnections and high quality electrical components, such as inductors, transformers, capacitors, or resistors are formed on a layer of passivation, or on a thick layer of polymer over a passivation layer.
    Type: Grant
    Filed: July 30, 2008
    Date of Patent: February 21, 2012
    Assignee: Megica Corporation
    Inventors: Mou-Shiung Lin, Chiu-Ming Chou, Chien-Kang Chou
  • Publication number: 20120025382
    Abstract: Structures and methods of forming metallization layers on a semiconductor component are disclosed. The method includes etching a metal line trench using a metal line mask, and etching a via trench using a via mask after etching the metal line trench. The via trench is etched only in regions common to both the metal line mask and the via mask.
    Type: Application
    Filed: October 12, 2011
    Publication date: February 2, 2012
    Applicant: Infineon Technologies AG
    Inventors: Philipp Riess, Erdem Kaltalioglu, Hermann Wendt
  • Publication number: 20120025381
    Abstract: An interlayer insulating film containing oxygen and carbon is formed on a semiconductor substrate. A groove is formed in the interlayer insulating film. An auxiliary film containing predetermined first and second metallic elements is formed on a bottom surface and a sidewall of the formed groove. Then, an interconnect body layer containing copper is formed to fill the groove. By performing a thermal treatment, a first barrier film containing a compound of the first metallic element and an oxygen element of the interlayer insulating film, and a second barrier film containing a compound of the second metallic element and carbon element of the interlayer insulating film are formed on the interlayer insulating film on the bottom surface and the sidewall of the groove.
    Type: Application
    Filed: October 12, 2011
    Publication date: February 2, 2012
    Applicant: Panasonic Corporation
    Inventors: Tatsuya Kabe, Susumu Matsumoto
  • Patent number: 8102051
    Abstract: The semiconductor device according to the present invention includes a first insulating layer made of a material containing Si and O, a groove shaped by digging down the first insulating layer, an embedded body, embedded in the groove, made of a metallic material mainly composed of Cu, a second insulating layer, stacked on the first insulating layer and the embedded body, made of a material containing Si and O, and a barrier film, formed between the embedded body and each of the first insulating layer and the second insulating layer, made of MnxSiyOz (x, y and z: numbers greater than zero).
    Type: Grant
    Filed: June 20, 2008
    Date of Patent: January 24, 2012
    Assignee: Rohm Co., Ltd.
    Inventor: Yuichi Nakao
  • Publication number: 20120013008
    Abstract: One aspect of the present invention is a method of processing a substrate. In one embodiment, the method comprises forming an electrical conductor on or in the substrate by providing a mixture comprising metal particles and an electroless deposition solution and electrolessly depositing a metal matrix and co-depositing the metal particles. In another embodiment, the method comprises forming an electrical conductor on or in the substrate by providing a mixture comprising metal particles and an electrochemical plating solution and electrochemically plating a metal matrix and co-depositing the metal particles. Another aspect of the present invention is a mixture for the formation of an electrical conductor on or in a substrate. Another aspect of the present invention is an electronic device.
    Type: Application
    Filed: July 13, 2010
    Publication date: January 19, 2012
    Inventors: Artur Kolics, Fritz Redeker
  • Publication number: 20120001334
    Abstract: An integrated circuit structure includes a semiconductor substrate; an interconnect structure over the semiconductor substrate, wherein the interconnect structure comprises a top inter-metal dielectric (IMD); an opening penetrating the interconnect structure into the semiconductor substrate; a conductor in the opening; and an isolation layer having a vertical portion and a horizontal portion physically connected to each other. The vertical portion is on sidewalls of the opening. The horizontal portion is directly over the interconnect structure. The integrated circuit structure is free from passivation layers vertically between the top IMD and the horizontal portion of the isolation layer.
    Type: Application
    Filed: September 15, 2011
    Publication date: January 5, 2012
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Cheng Kuo, Kai-Ming Ching, Chen Chen-Shien
  • Publication number: 20120001337
    Abstract: In accordance with an embodiment, a structure comprises a substrate having a first area and a second area; a through substrate via (TSV) in the substrate penetrating the first area of the substrate; an isolation layer over the second area of the substrate, the isolation layer having a recess; and a conductive material in the recess of the isolation layer, the isolation layer being disposed between the conductive material and the substrate in the recess.
    Type: Application
    Filed: June 30, 2010
    Publication date: January 5, 2012
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Yu Tsai, Shih-Hui Wang, Chien-Ming Chiu, Chia-Ho Chen, Fang Wen Tsai, Weng-Jin Wu, Jing-Cheng Lin, Wen-Chih Chiou, Shin-Puu Jeng, Chen-Hua Yu
  • Patent number: 8089154
    Abstract: It is an object of the present invention to provide a technology for forming an ULSI fine copper wiring by a simpler method. An electronic component in which a thin alloy film of tungsten and a noble metal used as a barrier-seed layer for an ULSI fine copper wiring is formed on a base material, wherein the thin alloy film has a composition comprising tungsten at a ratio equal to or greater than 50 at. % and the noble metal at a ratio of equal to or greater than 5 at. % and equal to or less than 50 at. %. The noble metal is preferably one or more kinds of metals selected from the group consisting of ruthenium, rhodium, and iridium.
    Type: Grant
    Filed: February 19, 2009
    Date of Patent: January 3, 2012
    Assignee: Nippon Mining & Metals Co., Ltd.
    Inventors: Junnosuke Sekiguchi, Toru Imori
  • Patent number: 8076778
    Abstract: A semiconductor device and related method for fabricating the same include providing a stacked structure including an insulating base layer and lower and upper barrier layers with a conductive layer in between, etching the stacked structure to provide a plurality of conductive columns that each extend from the lower barrier layer, each of the conductive columns having an overlying upper barrier layer cap formed from the etched upper barrier layer, wherein the lower barrier layer is partially etched to provide a land region between each of the conductive lines, forming a liner layer over the etched stacked structure exposing the land region, and etching the liner layer and removing the exposed land region to form a plurality of conductive lines.
    Type: Grant
    Filed: September 30, 2009
    Date of Patent: December 13, 2011
    Assignee: Macronix International Co., Ltd.
    Inventors: Kuo Liang Wei, Hsu Sheng Yu, Hong-Ji Lee