Abstract: A method for fabricating a semiconductor device, includes forming a dielectric film above a substrate; forming an opening in the dielectric film; forming a first film containing a metal whose energy for forming silicide thereof is lower than that of Cu silicide inside the opening; forming a second film that is conductive and contains copper (Cu) in the opening in which the first film containing the metal is formed; and forming a compound film containing Cu and silicon (Si) selectively on the second film in an atmosphere in which a temperature of the substrate is below 300° C.

Abstract: Interconnect structures and methods of manufacturing the same are disclosed herein. The method includes forming a barrier layer within a structure and forming an alloy metal on the barrier layer. The method further includes forming a pure metal on the alloy metal, and reflowing the pure metal such that the pure metal migrates to a bottom of the structure, while the alloy metal prevents exposure of the barrier layer. The method further includes completely filling in the structure with additional metal.

Abstract: Disclosed are methods of depositing a copper seed layer to be used for subsequent electroplating a bulk-layer of copper thereon. A copper seed layer may be deposited with different processes, including CVD, PVD, and electroplating. With electroplating methods for depositing a copper seed layer, disclosed are methods for depositing a copper alloy seed layer, methods for depositing a copper seed layer on the semi-noble metal layer with a non-corrosive electrolyte, methods of treating the semi-noble metal layer that the copper seed layer is deposited on, and methods for promoting a more uniform copper seed layer deposition across a semiconductor wafer.

Abstract: A technology that improves the reliability of a semiconductor device and realizes a high performance by a laminated structure that has enough barrier properties against copper, reduces the wire delay time by lowering the capacitance between wirings and improves the adhesion between wirings is provided. There is a semiconductor device having: a first copper wiring layer, a first barrier layer on the first copper wiring layer, a silicon oxide series porous insulating layer on the first barrier layer, a second barrier layer on the silicon oxide series porous insulating layer, and a second copper wiring layer on the second barrier layer, wherein at least one of the first barrier layer and the second barrier layer consists of an amorphous carbon film, wherein a silicon series insulating layer is directly connected between the amorphous carbon film and any of the first copper wiring layer or the second copper wiring layer.

Abstract: Semiconductor devices having copper interconnects and methods for their fabrication are provided. In one embodiment, a semiconductor device is fabricated with a copper interconnect on substrate such as an FEOL processed substrate. The method includes forming a copper layer on a substrate. The copper layer is formed from grains. The copper layer is modified such that the modified copper layer has an average grain size of larger than about 0.05 microns. In the method, the modified copper layer is etched to form a line along the substrate and a via extending upwards from the line.

Abstract: There are disclosed herein various implementations of semiconductor packages including an interposer without through-semiconductor vias (TSVs). One exemplary implementation includes a first active die situated over an interposer. The interposer includes an interposer dielectric having intra-interposer routing traces. The first active die communicates electrical signals to a package substrate situated below the interposer utilizing the intra-interposer routing traces and without utilizing TSVs. In one implementation, the semiconductor package includes a second active die situated over the interposer, the second active die communicating electrical signals to the package substrate utilizing the intra-interposer routing traces and without utilizing TSVs. Moreover, in one implementation, the first active die and the second active die communicate chip-to-chip signals through the interposer.

Abstract: In a manufacturing method of a barrier layer, a via hole is formed in an insulating layer that covers a conductive layer over a substrate, and then the barrier layer is formed in the via hole. The barrier layer is provided by forming a second titanium nitride film after forming a first titanium nitride film. The second titanium nitride film is formed using a method having a weak anisotropy than the first titanium nitride film.

Abstract: The present invention relates to a semiconductor device and a semiconductor package having the same. The semiconductor device includes a conductive element. The conductive element is disposed on a protruded conductive via and liner, and covers a sidewall of the liner. Whereby, the conductive element can protect the protruded conductive via and liner from being damaged. Further, the size of the conductive element is large, thus it is easy to perform a probe test process.

Abstract: In a method of forming a wiring structure for a semiconductor device, an insulation layer is formed on a semiconductor substrate on which a plurality of conductive structures is positioned. An upper surface of the insulation layer is planarized and spaces between the conductive structures are filled with the insulation layer. The insulation layer is partially removed from the substrate to form at least one opening through which the substrate is partially exposed. A residual metal layer is formed on a bottom and a lower portion of the sidewall of the at least one opening and a metal nitride layer is formed on the residual metal layer and an upper sidewall of the opening with a metal material. Accordingly, an upper portion of the barrier layer can be prevented from being removed in a planarization process for forming the metal plug.

Abstract: Provided is a film-forming method for performing a film-forming process on a surface of a target substrate to be processed in an evacuable processing chamber, a recessed portion being formed on the surface of the target substrate. The method includes a transition metal-containing film processing process in which a transition metal-containing film is formed by a heat treatment by using a source gas containing a transition metal; and a metal film forming process in which a metal film containing an element of the group VIII of the periodic table is formed.

Abstract: An integrated circuit (IC) includes a substrate having a topside semiconductor surface including active circuitry configured to provide functionality and a bottomside surface. A plurality of through substrate vias (TSVs) extend from the topside semiconductor surface to beyond the bottomside surface to provide protruding TSV tips. The TSVs include an outer dielectric liner, a metal comprising diffusion barrier layer on the dielectric liner, and a metal filler on the metal comprising barrier layer. A dielectric metal gettering layer (MGL) is on the bottomside surface lateral to and on sidewalls of the protruding TSV tips. The MGL includes at least one metal gettering agent selected from a halogen or a Group 15 element in an average concentration from 0.1 to 10 atomic %.

Abstract: One or more embodiments relate to a semiconductor structure, comprising: a barrier layer overlying a workpiece surface; a seed layer overlying the barrier layer; an inhibitor layer overlying said seed layer, the inhibitor layer having a opening exposing a portion of the seed layer, and a fill layer overlying the exposed portion of the seed layer.

Abstract: By forming an aluminum nitride layer by a self-limiting process sequence, the interface characteristics of a copper-based metallization layer may be significantly enhanced while nevertheless maintaining the overall permittivity of the layer stack at a lower level.

Abstract: The present invention extends the above referenced continuation-in-part application by in addition creating high quality electrical components, such as inductors, capacitors or resistors, on a layer of passivation or on the surface of a thick layer of polymer. In addition, the process of the invention provides a method for mounting discrete electrical components at a significant distance removed from the underlying silicon surface.

Abstract: Disclosed herein are various methods of forming methods of forming a non-planar cap layer above a conductive line on a semiconductor device, and to devices incorporating such a non-planar cap layer. In one illustrative example, the method includes forming a conductive structure in a layer of insulating material, recessing an upper surface of the conductive structure relative to an upper surface of the layer of insulating material such that the recessed upper surface of the conductive structure and the upper surface of the layer of insulating material are positioned in different planes and, after recessing the upper surface of the conductive structure, forming a first cap layer on the conductive structure and the layer of insulating material.

Abstract: A semiconductor device has an interlayer insulating film that is formed on a semiconductor substrate and has a trench formed therein; a first diffusion barrier film formed on an inner surface of the trench; a Cu wiring layer buried in the trench with the first diffusion barrier film interposed between the Cu wiring layer and the inner surface of the trench; a second diffusion barrier film formed on top of the interlayer insulating film and the Cu wiring layer; an alloy layer primarily containing Cu formed at a first interface between the Cu wiring layer and the second diffusion barrier film; a first reaction layer that is formed at a second interface between the interlayer insulating film and the second diffusion barrier film; and a second reaction layer that is formed on the alloy layer and the first reaction layer.

Abstract: An integrated circuit structure and methods for forming the same are provided. The integrated circuit structure includes a semiconductor substrate; a dielectric layer over the semiconductor substrate; an opening in the dielectric layer; a conductive line in the opening; a metal alloy layer overlying the conductive line; a first metal silicide layer overlying the metal alloy layer; and a second metal silicide layer different from the first metal silicide layer on the first metal silicide layer. The metal alloy layer and the first and the second metal silicide layers are substantially vertically aligned to the conductive line.

Abstract: An interconnect structure is provided which includes at least one patterned and cured low-k material located directly on a surface of a substrate; and at least one least one conductively filled region embedded within an interconnect pattern located within the at least one patterned and cured low-k material, wherein the at least one conductively filled region has an inflection point at a lower region of the interconnect pattern that is in proximity to an upper surface of the substrate and the interconnect region having an upper region that has substantially straight sidewalls.

Abstract: Incompatible materials, such as copper and nitrided barrier layers, may be adhered more effectively to one another. In one embodiment, a precursor of copper is deposited on the nitrided barrier. The precursor is then converted, through the application of energy, to copper which could not have been as effectively adhered to the barrier in the first place.

Abstract: A method for fabricating a semiconductor device, includes forming a dielectric film above a substrate; forming an opening in the dielectric film; forming a first film containing a metal whose energy for forming silicide thereof is lower than that of Cu silicide inside the opening; forming a second film that is conductive and contains copper (Cu) in the opening in which the first film containing the metal is formed; and forming a compound film containing Cu and silicon (Si) selectively on the second film in an atmosphere in which a temperature of the substrate is below 300° C.

Abstract: The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a. A groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Defective filling of the buried conductor and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented.

Abstract: Methods and apparatus for forming a semiconductor device are provided which may include any number of features. One feature is a method of forming an interconnect structure that results in the interconnect structure having a top surface and portions of the side walls of the interconnect structure covered in a dissimilar material. In some embodiments, the dissimilar material can be a conductive material or a nano-alloy. The interconnect structure can be formed by removing a portion of the interconnect structure, and covering the interconnect structure with the dissimilar material. The interconnect structure can comprise a damascene structure, such as a single or dual damascene structure, or alternatively, can comprise a silicon-through via (TSV) structure.

Abstract: The semiconductor device includes a first interconnect layer insulating film, first copper interconnects that are embedded in the first interconnect layer insulating film, and an interlayer insulating film that is formed on the first copper interconnects and the first interconnect layer insulating film. The semiconductor device includes a second interconnect layer insulating film that is formed on the interlayer insulating film and second copper interconnects that are embedded in the second interconnect layer insulating film. The first and second interconnect layer insulating films include first and second low dielectric constant films, respectively. The interlayer insulating film has higher mechanical strength than the first and second interconnect layer insulating films.

Abstract: An integrated circuit device having at least a bond pad for semiconductor devices and method for fabricating the same are provided. A bond pad has a first passivation layer having a plurality of openings. A conductive layer which overlies the openings and portions of the first passivation layer, having a first portion overlying the first passivation layer and a second portion overlying the openings. A second passivation layer overlies the first passivation layer and covers edges of the conductive layer.

Abstract: Partial air gap formation for providing interconnect isolation in integrated circuits is described. One embodiment is an integrated circuit (“IC”) structure includes a substrate having two adjacent interconnect features formed thereon; caps formed over and aligned with each of the interconnect features; sidewalls formed on opposing sides of each of the interconnect features and a gap formed between the interconnect features; and a dielectric material layer disposed over the substrate to cover the caps and the gap.

Abstract: Microelectronic chip including a semiconductor substrate; at least one area of its surface which is suitable to be electrically connected to a metal frame designed to accommodate the chip; at least one interconnect area formed by a copper-based conductive layer and comprising a connecting device, the interconnect area being connected to the area by a conductor, wherein the area is formed by a layer forming a copper diffusion barrier inserted between interconnect area and the substrate.

Abstract: An object of the invention is to fully fill a wiring material in via holes formed in a low-hardness interlayer insulating film and a high-hardness interlayer insulating film, respectively, upon forming a Cu wiring in interlayer insulating films by using the dual damascene process. According to the invention, a second interlayer insulating film has therein both a wiring trench and a via hole. The via hole has, at the opening portion thereof, a recess portion having a tapered cross-sectional shape. It is formed by causing the second interlayer insulating film to retreat obliquely downward. The diameter of the opening portion of the via hole therefore becomes greater than the diameter of a region below the opening portion and it becomes possible to fully fill a wiring material in the via hole even if the via hole has a fine diameter.

Abstract: By forming an aluminum nitride layer by a self-limiting process sequence, the interface characteristics of a copper-based metallization layer may be significantly enhanced while nevertheless maintaining the overall permittivity of the layer stack at a lower level.

Abstract: A semiconductor manufacturing method includes: forming a seed film including a first metal over a bottom surface and a side wall of an opening portion formed over interlayer insulating films and a field portion located over the interlayer insulating film except the opening portion, forming a resist over the seed film and filling the opening portion with the resist, removing part of the resist, exposing the seed film formed over the upper portion of the side walls of the opening portion and the field portion, forming a cover film including a second metal, whose resistivity is higher than that of the first metal, over the seed film located over the upper portion of the side wall of the opening portion and the field portion, exposing the seed film by removing the resist, and forming a plating film including the first metal over the exposed seed film.

Abstract: A plurality of metal interconnects incorporating a Group II element alloy for protecting the metal interconnects and methods to form and incorporate the Group II element alloy are described. In one embodiment, a Group II element alloy is used as a seed layer, or a portion thereof, which decreases the line resistance and increases the mechanical strength of a metal interconnect. In another embodiment, a Group II element alloy is used to form a barrier layer, which, in addition to decreasing the line resistance and increasing the mechanical integrity, also increases the chemical integrity of a metal interconnect.

Abstract: A metal thin film forming method includes depositing a Ti film on an insulating film formed on a substrate and depositing a Co film on the Ti film. The film forming method further includes modifying a laminated film of the Ti film and the Co film on the insulating film to a metal thin film containing Co3Ti alloy by heating the laminated film in an inert gas atmosphere or a reduction gas atmosphere.

Abstract: A circuit substrate is presented. The circuit substrate comprises internal terminal electrode 2; a substrate 1; a wiring layer 21 formed on a portion of the surface of the substrate and having one end thereof connected to the internal terminal electrode; an insulating film contacting as a surface with the wiring layer; and an external terminal electrode 9 connected to the other end of the wiring layer and used for connecting to the exterior. The angle of the cross-section of the wiring layer taken perpendicularly to the surface of the substrate in the edge portion that the wiring layer contains is 55° (55 degree) or less, and the wiring layer that contains multiple mutually independent columnar crystals extending perpendicularly in a direction different from the direction of the surface of the substrate.

Abstract: An interconnecting structure production method includes providing a substrate, forming a semiconductor layer on the substrate, forming a doped semiconductor layer on the semiconductor layer, the doped semiconductor layer containing a dopant, forming an oxide layer in a surface of the doped semiconductor layer by heating the surface of the doped semiconductor layer in atmosphere of an oxidizing gas with a water molecule contained therein, forming an alloy layer on the oxide layer, and forming an interconnecting layer on the alloy layer.

Abstract: An integrated circuit comprising an electromigration barrier includes a line, the line comprising a first conductive material, the line further comprising a plurality of line segments separated by one or more electromigration barriers, wherein the one or more electromigration barriers comprise a second conductive material that isolates electromigration effects within individual segments of the line.

Abstract: A method of depositing a bilayer of tungsten over tungsten nitride by a plasma sputtering process in which krypton is used as the sputter working gas during the tungsten deposition. Argon may be used as the sputtering working gas during the reactive sputtering deposition of tungsten nitride. The beneficial effect of reduction of tungsten resistivity is increased when the thickness of the tungsten layer is less than 50 nm and further increased when less than 35 nm. The method may be used in forming a gate stack including a polysilicon layer over a gate oxide layer over a silicon gate region of a MOS transistor in which the tungsten nitride acts as a barrier. A plasma sputter chamber in which the invention may be practiced includes gas sources of krypton, argon, and nitrogen.

Abstract: A structure is provided with a self-aligned resist layer on a surface of metal interconnects for use in forming air gaps in an insulator material and method of fabricating the same. The non-lithographic method includes applying a resist on a structure comprising at least one metal interconnect formed in an insulator material. The method further includes blanket-exposing the resist to energy and developing the resist to expose surfaces of the insulator material while protecting the metal interconnects. The method further includes forming air gaps in the insulator material by an etching process, while the metal interconnects remain protected by the resist.

Abstract: Electrical interconnects for integrated circuits and methods of fabrication of interconnects are provided. Devices are provided comprising copper interconnects having metal liner layers comprising cobalt and a metal selected from the group consisting of Ru, Pt, Ir, Pd, Re, or Rh. Devices having barrier layers comprising ruthenium and cobalt are provided. Methods include providing a substrate having a trench or via formed therein, forming a metal layer, the metal being selected from the group consisting of Ru, Pt, Ir, Pd, Re, and Rh, onto surfaces of the feature, depositing a copper seed layer comprising a cobalt dopant, and depositing copper into the feature.

Abstract: In sophisticated metallization systems of semiconductor devices, a sensitive core metal, such as copper, may be efficiently confined by a conductive barrier material comprising a copper/silicon compound, such as a copper silicide, which may provide superior electromigration behavior and higher electrical conductivity compared to conventionally used tantalum/tantalum nitride barrier systems.

Abstract: A damascene structure includes a conductive layer, a first dielectric layer, a first barrier metal layer, a barrier layer, and a second barrier metal layer sequentially formed on the conductive layer. The first dielectric layer having a via therein. The barrier layer is comprised of a material different with that of the first barrier metal layer. A bottom of the barrier layer disposed on the via bottom is not punched through. The accomplished barrier layers will have lower resistivity on the via bottom in the first dielectric layer and they are capable of preventing copper atoms from diffusing into the dielectric layer.

Abstract: A semiconductor device of the present invention includes an insulating film made of a low dielectric constant material having a smaller specific dielectric constant than SiO2, a wiring trench formed in the insulating film, a first barrier film made of SiO2 or SiCO formed at least on the side surface of the wiring trench, Cu wiring mainly composed of Cu embedded in the wiring trench, and a second barrier film made of a compound containing Si, O and a predetermined metallic element covering the surface of the Cu wiring opposed to the wiring trench.

Abstract: A three-dimensional (3D) chip stack structure and method of fabricating the structure thereof are provided. The 3D chip stack structure includes a plurality of vertically stacked chips which are interconnected and bonded together, wherein each of the vertically stacked chips include one or more IC device strata. The 3D chip stack structure further includes an air channel interconnect network embedded within the chip stack structure, and wherein the air channel interconnect network is formed in between at least two wafers bonded to each other of the vertically stacked wafers and in between at least two bonded wafers of the vertically stacked wafers at a bonding interface thereof.

Abstract: The present invention provides a semiconductor device which is capable of enhancing adhesion at an interface between a wire-protection film and copper, suppressing dispersion of copper at the interface to avoid electromigration and stress-inducing voids, and having a highly reliable wire. An interlayer insulating film, and a first etching-stopper film are formed on a semiconductor substrate on which a semiconductor device is fabricated. A first alloy-wire covered with a first barrier metal film is formed on the first etching-stopper film by a damascene process. The first alloy-wire is covered at an upper surface thereof with a first wire-protection film. The first wire-protection film covering an upper surface of the first alloy-wire contains at least one metal among metals contained in the first alloy-wire.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate in which a first interlayer insulation layer having a first via hole and a first trench is formed. The semiconductor device also includes a first via plug and a first metal line respectively formed by filling the first via hole and the first trench with a first metal, a predetermined scratch being formed on the first metal line; and a second via plug a second metal line respectively formed by filling a second via hole and a second trench with a second metal, the second metal lines being separated.

Abstract: It is an object of the present invention to provide a copper-based bonding wire whose material cost is low, having excellent ball bondability, reliability in a heat cycle test or reflow test, and storage life, enabling an application to thinning of a wire used for fine pitch connection. The bonding wire includes a core material having copper as a main component and an outer layer which is provided on the core material and contains a metal M and copper, in which the metal M differs from the core material in one or both of components and composition. The outer layer is 0.021 to 0.12 ?m in thickness.

Abstract: The embodiments of methods and structures for forming through silicon vias a CMOS substrate bonded to a MEMS substrate and a capping substrate provide mechanisms for integrating CMOS and MEMS devices that use less real-estate and are more reliable. The through silicon vias electrically connect to metal-1 level of the CMOS devices. Copper metal may be plated on a barrier/Cu-seed layer to partially fill the through silicon vias, which saves time and cost. The formation method may involve using dual dielectric layers on the substrate surface as etching mask to eliminate a photolithographical process during the removal of oxide layer at the bottoms of through silicon vias. In some embodiments, the through silicon vias land on polysilicon gate structures to prevent notch formation during etching of the vias.

Abstract: One or more embodiments relate to a method of forming an electronic device, comprising: providing a workpiece; forming a first barrier layer over the workpiece; forming an intermediate conductive layer over the first barrier layer; forming a second barrier layer over the intermediate conductive layer; forming a seed layer over the second barrier layer; removing a portion of the seed layer to leave a remaining portion of the seed layer and to expose a portion of the second barrier layer; and electroplating a fill layer on the remaining portion of the seed layer.

Abstract: One or more embodiments relate to a method of forming a semiconductor structure, comprising: providing a workpiece; forming a barrier layer over the workpiece; forming a seed layer over the barrier layer; forming an inhibitor layer over the seed layer; removing a portion of said inhibitor layer to expose a portion of the seed layer; and selectively depositing a fill layer on the exposed seed layer.

Abstract: One or more embodiments relate to a method of forming a semiconductor device, comprising: forming a structure, the structure including at least a first element and a second element; and forming a passivation layer over the structure, the passivation layer including at least the first element and the second element, the first element and the second element of the passivation layer coming from the structure.

Abstract: An apparatus includes an interconnect in a recess. The interconnect includes a liner structure and the liner structure in the recess. The liner structure is breached at the recess bottom feature and a bottom interconnect makes a single-interface contact with a subsequent interconnect through the breach.

Abstract: A method and a system for improving reliability of a semiconductor device are provided. In one embodiment, a semiconductor device is provided comprising a semiconductor chip, a metallization layer comprising a metallic material disposed over a surface of the semiconductor chip, and an alloy layer comprising the metallic material disposed over the metallization layer.