Abstract: Semiconductor device components and methods are disclosed. In one embodiment, a semiconductor device component includes a conductive segment having a first surface, a second surface opposite the first surface, a first end, and a second end opposite the first end. A first via is coupled to the second surface of the conductive segment at the first end. A second via is coupled to the first surface of the conductive segment at the second end, and a third via is coupled to the second surface of the conductive segment at the second end.

Abstract: A structural member for use in semiconductor packaging is disclosed. The structural member includes a plurality of packaging regions to facilitate packaging dies in, for example, a wafer format. A packaging region has a die attach region surrounded by a peripheral region. A die is attached to the die attach region. In one aspect, the die attach region has opening through the surfaces of the structural member for accommodating a die. Through-vias disposed are in the peripheral regions. The structural member reduces warpage that can occur during curing of the mold compound used in encapsulating the dies. In another aspect, the die attach region does not have an opening. In such cases, the structural member serves as an interposer between the die and a substrate.

Abstract: A package-on-package (POP) package precursor and packaged devices and systems therefrom includes an electronic substrate including electrically conductive layers and a top surface. A first portion of the top surface has an IC die attached thereon. A second portion of the top surface has a plurality of first attach pads on opposing sides of the IC die for electrically coupling to a first electronic device on top of the IC die. At least a third portion of the top surface is positioned laterally with respect to the first and second portion. The third portion includes a plurality of second attach pads for electrically coupling to at least a second electronic device. At least one of the electrically conductive layers includes a coupling trace that couples at least one of the plurality of second attach pads to the IC die and/or one or more of the plurality of first attach pads.

Abstract: The semiconductor module includes a plurality of memory die on a first side of a substrate and a plurality of buffer die on a second side of the substrate. Each of the memory die is disposed opposite and electrically coupled to one of the buffer die.

Abstract: A semiconductor package includes a package board, a pellet provided over the package board, and a protection member covering the package board and the pellet and including a hole penetrating the protection member.

Abstract: A semiconductor chip includes a body part having a first surface and a second surface facing away from the first surface, and an opening passing from the first surface to the second surface of the body part.

Abstract: Methods of forming bonded semiconductor structures include providing a substrate structure including a relatively thinner layer of material on a thicker substrate body, and forming a plurality of through wafer interconnects through the layer of material. A first semiconductor structure may be bonded over the thin layer of material, and at least one conductive feature of the first semiconductor structure may be electrically coupled with at least one of the through wafer interconnects. A transferred layer of material may be provided over the first semiconductor structure on a side thereof opposite the first substrate structure, and at least one of an electrical interconnect, an optical interconnect, and a fluidic interconnect may be formed in the transferred layer of material. A second semiconductor structure may be provided over the transferred layer of material on a side thereof opposite the first semiconductor structure. Bonded semiconductor structures are fabricated using such methods.

Abstract: Semiconductor dice judged as good dice are stacked on a base substrate in which through holes and through hole electrodes are formed. Next, a protection layer to cover the semiconductor dice is formed. It is preferable that the protection layer is composed of a plurality of resin layers (a first resin layer and a second resin layer) that are different, in hardness from each other. Then, a conductive terminal that is connected with the through hole electrode is formed on a back surface of the base substrate. Next, the second resin layer and the base substrate are cut along predetermined dicing lines and separated into individual semiconductor devices in chip form. A process step of separation into the semiconductor devices is performed while each of the semiconductor dice is mounted on the base substrate in wafer form.

Abstract: Provided is a chip stack package and a method of manufacturing the same. A chip stack package may include a base chip including a base substrate, a base through via electrode penetrating the base substrate, a base chip pad connected to the base through via electrode, and a base encapsulant. The chip stack package may further include at least one stack chip on a surface of the base substrate. The chip stack package may also include an external connection terminal connected to the base through via electrode and the base chip pad and protruding from the base encapsulant, and an external encapsulant surrounding and protecting outer surfaces of the base chip and the at least one stack chip, wherein the chip through via electrode and the chip pad are connected to the base through via electrode and the base chip pad of the base chip.

Abstract: A semiconductor package including a plurality of stacked semiconductor die, and methods of forming the semiconductor package, are disclosed. In order to ease wirebonding requirements on the controller die, the controller die may be mounted directly to the substrate in a flip chip arrangement requiring no wire bonds or footprint outside of the controller die. Thereafter, a spacer layer may be affixed to the substrate around the controller die to provide a level surface on which to mount one or more flash memory die. The spacer layer may be provided in a variety of different configurations.

Abstract: A method of manufacturing a plurality of electronic devices is provided. Each one of a plurality of first conductive terminals on a plurality of integrated circuits formed on a device wafer is connected to a respective one of a plurality of second conductive terminals on a carrier wafer, thereby forming a combination wafer assembly. The combination wafer assembly is singulated between the integrated circuits to form separate electronic assemblies. The combination wafer assembly also allows for an underfill material to be introduced and to cured at wafer level and for thinning of the device wafer at wafer level without requiring a separate supporting substrate. Alignment between the device wafer and the carrier wafer can be tested by conducting a current through first and second conductors in the device and carrier wafers, respectively.

Abstract: The present invention relates to a semiconductor package having at least one first layer chip, a plurality of first metal bumps, at least one second layer chip and a package body. The first layer chip includes a first active surface upon which the first metal bumps are disposed and a plurality of first signal coupling pads disposed adjacent to the first active surface. The second layer chip is electrically connected to the first layer chip, and includes a second active surface that faces the first active surface and a plurality of second signal coupling pads. The second signal coupling pads are capacitively coupled to the first signal coupling pads so as to provide proximity communication between the first layer chip and the second layer chip. The package body encapsulates the first layer chip, the first metal bumps, and the second layer chip, and the first metal bumps are partially exposed.

Abstract: A power semiconductor component including a semiconductor body and two load terminals is provided. Provided furthermore is a potential probe positioned to tap an electric intermediate potential of the semiconductor body at a tap location of the semiconductor body for an electric voltage applied across the two load terminals, the intermediate potential being intermediate to the electric potentials of the two load terminals, but differing from each of the two electric potentials of the two load terminals.

Abstract: A method performs electrical testing and assembly of an electronic device on a wafer and comprising a pad made in an oxide layer covered by a passivation layer. The method includes connecting the electronic device to a testing apparatus; providing said electronic device with a metallization layer extending on the passivation layer from the pad to a non-active area of said wafer. The method comprises-performing the electrical testing on wafer of the electronic device by placing a probe of on a portion of the extended metallization layer; performing the cut of said wafer, reducing the extension of the metallization layer to the edge of the electronic device; embedding the device inside a package, forming on the metallization layer an electrical connection configured to connect the metallization layer to a circuit in said package.

Abstract: A packaged semiconductor device has a metal plate (1200) with sawed sides (1200c), a flat first surface (1200a) and a parallel second surface (1200b); the plate is separated into a first section (1201) and a second section (1202) spaced apart by a gap (1230). The plate has on the second surface (1200b) at least one insular mesa (1205) of the same metal in each section, the mesas raised from the second plate surface. The device further has an insulating member (1231), which adheres to the first plate surface, bridges the gap, and thus couples the first and second sections together. The device further has a vertical stack (1270) of two power FET chips (1210) and (1220), each having a pair of terminals on the first chip surface (1211 and 1212; 1221 and 1222 respectively) and a single terminal on the second chip surface. The single terminals of chip (1210) and chip (1220) are attached to each other to form the common terminal (1240).

Abstract: In an embodiment, a stacked semiconductor package includes a wiring board having external connection terminals and internal connection terminals, and first and second modules stacked on the wiring board. Each of the first and second modules includes a plurality of semiconductor chips mounted on an interposer and a sealing resin layer. The interposers and the internal connection terminals of the wiring board are electrically connected by connecting members such as metal wires, printed wiring layers or metal bumps. The first and second modules are collectively sealed by a sealing resin layer formed on the wiring board.

Abstract: A device includes a first semiconductor chip and a first encapsulant that encapsulates the first semiconductor chip and that includes a cavity. A carrier and an electrical component are mounted on the carrier. The carrier is arranged such that the electrical component is enclosed by the cavity.

Abstract: According to an exemplary embodiment, a bondwireless power module includes a common output pad coupling an emitter/anode node of a high side device to a collector/cathode node of a low side device. The bondwireless power module also includes a high side conductive clip connecting a collector of the high side device to a cathode of the high side device, and causing current to traverse through the high side conductive clip to another high side conductive clip in another power module. The bondwireless power module further includes a low side conductive clip connecting an emitter of the low side device to an anode of the low side device, and causing current to traverse through the low side conductive clip to another low side conductive clip in the another power module. The bondwireless power module can be a motor drive inverter module.

Abstract: A through substrate via (TSV) die includes a substrate including a topside semiconductor surface having active circuitry. The die includes a plurality of TSVs that each include an inner metal core that extend from the topside semiconductor surface to protruding TSV tips that extend out from the bottomside surface. A metal cap is on the protruding TSV tips that includes at least one metal layer that has a metal that is not in the inner metal core. A plurality of protruding warpage control features are on the bottomside surface lateral to the protruding TSV tips, wherein the plurality of protruding warpage control features do not have the protruding TSV tips thereunder. The plurality of protruding warpage control features can include the same metal layer(s) used for the metal cap.

Abstract: A stacked structure of chips including a first chip and a second chip is provided. The first chip includes a first and a second circuit blocks, a signal path, a first and a second hardwired switches. The second chip stacks with the first chip stack and includes a third circuit block, a third and a fourth hardwired switches. If the first circuit block is defective and the second and the third circuit blocks are functional, the first hardwired switch and the third hardwired switch are set correspondingly such that a power-supply bonding pad is connected to the third power terminal and disconnected to the first power terminal, and the second hardwired switch and the fourth hardwired switch are set correspondingly such that the third signal terminal is electrically connected to the signal path to make the third circuit block replace the first circuit block and provide the first function.

Abstract: A stacked semiconductor device including a plurality of semiconductor chips stacked vertically, a plurality of scribe lane elements each forming a step with a semiconductor chip of the plurality of semiconductor chips and respectively formed on a side surface of each of the plurality of semiconductor chips, a redistribution element respectively formed on each of the plurality of semiconductor chips and the scribe lane elements, and a signal connection member formed on the side surface of each of the plurality of semiconductor chips and electrically connecting the redistribution elements.

Abstract: A technique capable of promoting miniaturization of an RF power module used in a mobile phone etc. is provided. A directional coupler is formed inside a semiconductor chip in which an amplification part of the RF power module is formed. A sub-line of the directional coupler is formed in the same layer as a drain wire coupled to the drain region of an LDMOSFET, which will serve as the amplification part of the semiconductor chip. Due to this, the predetermined drain wire is used as a main line and the directional coupler is configured by a sub-line arranged in parallel to the main line via an insulating film, together with the main line.

Abstract: A IC package for a wireless device includes an antenna that is attached to the chip. The electrically conductive elements of the antenna are spaced away from the antenna and particularly the endpoint of the antenna to prevent interference with the antenna. An element on the IC package may be shielded antenna. The antenna may have the shape of a space-filling curve, including a Hilbert, box-counting or grid dimension curve.

Abstract: A method of forming a metal pattern on a dielectric material that comprises forming at least one trench in a photosensitive, insulative material is disclosed. The at least one trench may be positioned over at least one bond pad. A metal is formed over the photosensitive, insulative material and into the at least one trench and a photoresist material is formed over the metal. A portion of the photoresist material may be removed to expose elevated areas of the metal such that a remaining portion of the photoresist material does not extend beyond sidewalls of the at least one trench and onto the elevated areas of the metal. The metal may be exposed laterally beyond the remaining portion of the photoresist material.

Abstract: A semiconductor device and a method for fabricating the same, wherein a portion of a substrate comprising a pad is removed to form a via hole. An insulating layer is formed on the substrate. A portion of the insulating layer is removed to form a plurality of openings exposing portions of the pad. A through electrode is formed to fill the via hole and to be electrically connected to the pad through one of the plurality of openings. A portion of the pad is exposed by another opening among the plurality of openings.

Abstract: A method for manufacturing a three-dimensional, electronic system includes: providing a first integrated circuit structure in a first substrate, wherein the first integrated circuit structure has a first contact pad at a first main side of the first substrate; providing a second substrate with a second main side; forming a vertical contact area in the second substrate; after step (c) forming a semiconductor layer on the second main side of the second substrate; forming a semiconductor device of a second integrated circuit structure in the second substrate with the semiconductor layer; removing the substrate material from a side of the second substrate opposite the second main side, so that the vertical contact area at the opposite side is electrically exposed; arranging the first and second substrates on top of each other aligning the vertical contact area with the contact pad, so that an electrical connection between the first and second integrated circuit structures is produced via the vertical contact area

Abstract: A memory card has a wiring board, four memory chips stacked on a main surface of the wiring board, and a controller chip and an interposer mounted on a surface of the memory chip of the uppermost layer. The memory chips are stacked on the surface of the wiring board so that their long sides are directed in the same direction as that of the long side of the wiring board. The memory chip of the lowermost layer is mounted on the wiring board in a dislocated manner by a predetermined distance in a direction toward a front end of the memory card so as not to overlap the pads of the wiring board. The three memory chips stacked on the memory chip of the lowermost layer are disposed so that their short sides on which pads are formed are located at the front end of the memory card.

Abstract: Microelectronic packages are fabricated by stacking integrated circuits upon one another. Each integrated circuit includes a semiconductor layer having microelectronic devices and a wiring layer on the semiconductor layer having wiring that selectively interconnects the microelectronic devices. After stacking, a via is formed that extends through at least two of the integrated circuits that are stacked upon one another. Then, the via is filled with conductive material that selectively electrically contacts the wiring. Related microelectronic packages are also described.

Abstract: An integrated circuit package system includes: providing an integrated circuit substrate; forming an internal stacking module coupled to the integrated circuit substrate including: forming a flexible substrate, coupling a stacking module integrated circuit to the flexible substrate, and bending a flexible extension over the stacking module integrated circuit; and molding a package body on the integrated circuit substrate and the internal stacking module.

Abstract: A microelectronic unit is provided in which front and rear surfaces of a semiconductor element may define a thin region which has a first thickness and a thicker region having a thickness at least about twice the first thickness. A semiconductor device may be present at the front surface, with a plurality of first conductive contacts at the front surface connected to the device. A plurality of conductive vias may extend from the rear surface through the thin region of the semiconductor element to the first conductive contacts. A plurality of second conductive contacts can be exposed at an exterior of the semiconductor element. A plurality of conductive traces may connect the second conductive contacts to the conductive vias.

Abstract: An interconnect substrate is placed over a first inductor of a semiconductor chip and a second inductor of another semiconductor chip. The interconnect substrate includes a third inductor and a fourth inductor. The third inductor is located above the first inductor. The distance from the first inductor to the third inductor is longer than the distance from the second inductor to the fourth inductor.

Abstract: A wafer level package, and a semiconductor wafer, electronic system, and a memory module that include one or more of the wafer level packages, and methods of fabricating the die packages on a wafer level, and integrated circuit modules that include one or more die packages are provided. In one embodiment, the die package comprises a redistribution layer interconnecting two or more dies disposed on a substrate, typically a semiconductor wafer, the redistribution layer including a first trace connecting a bond pad of each of two dies, and a second trace connecting one of the bond pads of the two dies to a ball pad. The die package of the invention can comprise memory devices such as static random access memories (SRAMs), and can be incorporated into a variety of electronic systems as part of memory packages such as single in-line memory modules (SIMMs) or dual in-line memory modules.

Abstract: An integrated circuit (IC) device includes a substrate having a top surface including active circuitry including a plurality of I/O nodes, and a plurality of die pads coupled to the plurality of I/O nodes. A first dielectric layer including first dielectric vias is over the plurality of die pads. A redirect layer (RDL) including a plurality of RDL capture pads is coupled to the plurality of die pads over the first dielectric vias. A second dielectric layer including second dielectric vias is over the plurality of RDL capture pads. At least one of the second dielectric vias is a crack arrest via that has a via shape that includes an apex that faces away from a neutral stress point of the IC die and is oriented along a line from the neutral stress point to the crack arrest via to face in a range of ±30 degrees from the line. Under bump metallization (UBM) pads are coupled to the plurality of RDL capture pads over the second dielectric vias, and metal bonding connectors are on the UBM pads.

Abstract: An integrated circuit package on package system includes: providing a lead having a wire-bonded die with a bond wire connected thereto; mounting a fan-in interposer over the wire-bonded die and the bond wire; connecting the fan-in interposer to the lead with the bond wires; and encapsulating the wire-bonded die, bond wires, and the fan-in interposer with an encapsulation leaving a portion of the fan-in interposer exposed.

Abstract: This document discusses, among other things, a semiconductor die package having a first and a second discrete components embedded into a dielectric substrate. An integrated circuit (IC) die is surface mounted on a first side of the dielectric substrate. The semiconductor die package includes a plurality of conductive regions on the second side of the dielectric substrate for mounting the semiconductor die package. A plurality of through hole vias couple the IC die to the first and second discrete components and the plurality of conductive regions.

Abstract: A semiconductor package includes: a wiring board; and a semiconductor device which is formed on the wiring board; wherein the semiconductor device includes: a semiconductor chip; and a penetration electrode, one end of which is fixed on one plane of the semiconductor chip, and the other end of which penetrates the semiconductor chip and is fixed on the other plane of the semiconductor chip, the penetration electrode penetrating the semiconductor chip in such a manner that the penetration electrode is not contacted to a wall plane of the semiconductor chip by a space portion formed in the semiconductor chip; and the wiring board and the semiconductor device are electrically connected via the penetration electrode.

Abstract: A multilayer module comprised of stacked IC package layers is disclosed. A plurality of layers preferably having ball grid array I/O are stacked and interconnected using one or more interposer layers for the routing of electronic signals to appropriate locations in the module through angularly depending leads. The stack is further comprised of an interface PCB for the routing of electronics signals to and from the layers in the module and for connection to an external circuit.

Abstract: The invention relates to a method for connecting two joining surfaces, particularly in the field of semiconductors, wherein at least one joining surface is produced by depositing a layer comprising 20 to 40% gold and 80 to 60% silver onto a substrate and selectively removing the silver from the deposited layer in order to produce a nanoporous gold layer as a joining surface. The joining surface with the nanoporous gold layer and an additional joining surface are disposed one above the other and pressed together.

Abstract: The semiconductor package includes a printed circuit board, a first semiconductor chip, and a second semiconductor chip. The printed circuit board includes a slot. The first semiconductor chip is mounted on the printed circuit board to cover a first part of the slot. The second semiconductor chip is mounted on the printed circuit board to cover a second part of the slot separate from the first part. The first semiconductor chip is substantially coplanar with the second semiconductor chip.

Abstract: A method of packaging an electronic device includes providing a patterned dielectric layer with an area sized to receive a first die, and another area sized to receive a second die, placing the first and second dies within the first and second areas, encapsulating the dies with an encapsulating material that has a different composition from the dielectric layer, forming a first signal line between the dies, forming a second signal line to the first die, and forming an additional signal line to the first die. The dielectric layer is disposed between the first signal line and the encapsulating material, the electronic device transmits a signal in an approximate range of 1 GHz to 100 GHz along the second signal line, and a signal that does not exceed approximately 900 MHz along the additional signal line.

Abstract: A multi-chip package includes a substrate (110) having a first side (111), an opposing second side (112), and a third side (213) that extends from the first side to the second side, a first die (120) attached to the first side of the substrate and a second die (130) attached to the first side of the substrate, and a bridge (140) adjacent to the third side of the substrate and attached to the first die and to the second die. No portion of the substrate is underneath the bridge. The bridge creates a connection between the first die and the second die. Alternatively, the bridge may be disposed in a cavity (615, 915) in the substrate or between the substrate and a die layer (750). The bridge may constitute an active die and may be attached to the substrate using wirebonds (241, 841, 1141, 1541).

Abstract: The present invention relates to a semiconductor package and method for making the same. The semiconductor package includes a silicon substrate unit, a bridge chip and at least one active chip. The silicon substrate unit has a cavity and a plurality of vias. The bridge chip is attached to the cavity and has a plurality of non-contact pads. The active chip is disposed above the bridge chip and has a plurality of non-contact pads and a plurality of conducting elements. The conducting elements of the active chip contact the vias of the silicon substrate unit, the non-contact pads of the active chip face but are not in physical contact with the non-contact pads of the bridge chip, so as to provide proximity communication between the active chip and the bridge chip.

Abstract: A sensor module includes a support member having a first flat surface, a second flat surface orthogonally connected to the first flat surface, a third flat surface orthogonally connected to the first flat surface and the second flat surface, and a fourth flat surface opposed to the first flat surface as an attachment surface to an external member, the first flat surface having a support surface depressed from the first flat surface, IC chips having connection terminals on active surface sides with inactive surface sides along the active surfaces respectively attached to the respective surfaces of the support member, and vibration gyro elements having connection electrodes, and the vibration gyro elements are provided on the active surface sides of the IC chips and the connection electrodes are attached to the connection terminals of the IC chips so that principal surfaces are respectively along the respective surfaces of the support member.

Abstract: A ramp-stack chip package is described. This chip package includes a vertical stack of semiconductor dies or chips that are offset from each other in a horizontal direction, thereby defining a terrace with exposed pads. A high-bandwidth ramp component, which is positioned approximately parallel to the terrace, is electrically and mechanically coupled to the exposed pads. For example, the ramp component may be coupled to the semiconductor dies using: solder, microsprings and/or an anisotropic conducting film. Furthermore, each of the semiconductor dies includes a static bend so that an end segment of each of the semiconductor dies is parallel to the direction and is mechanically coupled to the ramp component. These end segments may facilitate high-bandwidth communication of signals between the chips and the ramp component, for example, via proximity communication.

Abstract: A semiconductor integrated circuit includes a first conductor provided in a first region on a substrate and a second conductor provided in a second region on the substrate. The second region is a region enclosing the first region. A minimum design dimension in linewidth of the first conductor is smaller than a minimum design dimension in linewidth of the second conductor.

Abstract: A first circuit element and a second element are mounted with their electrode forming surfaces facing a wiring layer. A first bump electrode formed integrally with the wiring layer on one face substantially penetrates a first insulating resin layer. A gold plating layer covering an element electrode of the first circuit element and a gold plating layer disposed on top of the first bump electrode are bonded together by Au—Au bonding. A second bump electrode formed integrally with the wiring layer on one face substantially penetrates the first and the second insulating resin layer. A gold plating layer covering an element electrode of the second circuit element and a gold plating layer disposed on top of the second bump electrode are bonded together by Au—Au bonding.

Abstract: A circuit substrate has one or more active components and a plurality of passive circuit elements on a first surface. An active semiconductor device has a substrate with layers of material and a plurality of terminals. The active semiconductor device is flip-chip mounted on the circuit substrate and at least one of the terminals of the device is electrically connected to an active component on the circuit substrate. The active components on the substrate and the flip-chip mounted active semiconductor device, in combination with passive circuit elements, form preamplifiers and an output amplifier respectively. In a power switching configuration, the circuit substrate has logic control circuits on a first surface. A semiconductor transistor flip-chip mounted on the circuit substrate is electrically connected to the control circuits on the first surface to thereby control the on and off switching of the flip-chip mounted device.

Abstract: A multi-chip stack package structure comprises a substrate, which has a chip placement area defined on its upper surface and a plurality of contacts disposed outside the chip placement area; a first chip is disposed in the chip placement area with the rear surface, a plurality of first pads being disposed on the active surface and a plurality of first bumps each being formed on one of the first pads; a plurality of metal wires connect the first bumps to the contacts; a second chip with a plurality of second pads being disposed on the active surface and a plurality of second bumps each being formed on one of the second pads, the second chip being mounted to the first chip with its active surface facing the active surface of the first chip, wherein the second bumps correspondingly connect the metal wires and the first bumps respectively.

Abstract: A multi-chip stack package structure comprises a substrate, which has a chip placement area defined on its upper surface and a plurality of contacts disposed outside the chip placement area; a first chip is disposed in the chip placement area with the rear surface, a plurality of first pads being disposed on the active surface and a plurality of first bumps each being formed on one of the first pads; a plurality of metal wires connect the first bumps to the contacts; a second chip with a plurality of second pads being disposed on the active surface and a plurality of second bumps each being formed on one of the second pads, the second chip being mounted to the first chip with its active surface facing the active surface of the first chip, wherein the second bumps correspondingly connect the metal wires and the first bumps respectively.

Abstract: A III-nitride device that includes a silicon body having formed therein an integrated circuit and a III-nitride device formed over a surface of the silicon body.