Abstract: Two integrated circuits having circuitry on one of their major surfaces are ground on their opposite major surfaces to reduce their thickness. The ground integrated circuits are then adhered together to form a composite body and placed in a chamber formed within a substrate such as a printed circuit board. Electrical connections are formed between contacts of the integrated circuits and contacts of the substrate. Components may be mounted on the outer surfaces of the substrate.

Abstract: A stacked semiconductor package and an electronic system, the stacked semiconductor package including a plurality of semiconductor chips, a set of the semiconductor chips being stacked such that an extension region of a top surface of each semiconductor chip of the set extends beyond an end of a semiconductor chip stacked thereon to form a plurality of extension regions; and a plurality of protection layers on the extension regions and on an uppermost semiconductor chip of the plurality of semiconductor chips.

Abstract: An electronic package-on-package system with integrated shielding. The package-on-package system includes a first package having a first die and a second package having a second die and a substrate. The system also includes a conductive shield having a first portion and a second portion. The first portion is disposed between the first die and the second die and the second portion is disposed between the substrate and the first portion. The first portion is coupled to the second portion for shielding the first die from the second die.

Abstract: A method for manufacturing of an integrated circuit package-in-package system includes: mounting a first integrated circuit device over a substrate; mounting an integrated circuit package system having an inner encapsulation over the first integrated circuit device with a first offset; mounting a second integrated circuit device over the first integrated circuit device and adjacent to the integrated circuit package system; connecting the integrated circuit package system and the substrate; and forming a package encapsulation as a cover for the first integrated circuit device, the integrated circuit package system, and the second integrated circuit device.

Abstract: A module, which in one embodiment may be a packaged millimeter waver module, includes a semiconductor lid portion; a packaging portion attached to the lid portion, wherein the packaging portion comprises a plurality of vias, a carrier portion, wherein a first semiconductor die is attached to the carrier portion, the packaging portion is attached to the carrier portion so that the packaging portion is over the carrier portion and the semiconductor die is within an opening in the packaging portion, and the lid portion and the carrier portion form an first air gap around the first semiconductor device.

Abstract: The present disclosure relates to the field of integrated circuit package design and, more particularly, to packages using a bumpless build-up layer (BBUL) designs. Embodiments of the present description relate to the field of fabricating microelectronic packages, wherein an interposer, such as a through-silicon via interposer, may be used in a bumpless build-up layer package to facilitate stacked microelectronic components.

Abstract: Alignment for electronic devices using a template having holes to align the protrusions of one or more integrated circuits. There are least one integrated circuit having a plurality of protrusions arranged in a protrusion pattern. There is a template with holes disposed on the integrated circuit, wherein at least some of the holes are arranged in the protrusion pattern and the holes are disposed onto the protrusions such that a portion of the protrusions extends from the template. There is an interconnect disposed on the template, wherein the interconnect has a plurality of electric contacts, wherein at least some of the electrical contacts are arranged in the protrusion pattern, and wherein at least some of the electrical contacts are electrically coupled to at least some of the protrusions.

Abstract: In a multi-chip semiconductor device, a second semiconductor chip is stacked on a first semiconductor chip with an adhesive layer being interposed therebetween, and the first and second semiconductor chips are sealed by resin containing a mixture of, e.g., a filler. The first semiconductor chip includes a first region on a surface of which the second semiconductor chip is stacked, and a second region on a surface of which the second semiconductor chip does not stacked. In one of interconnect layers including an uppermost layer, a wiring pattern is not provided, which extends across a border between the first and second regions.

Abstract: A semiconductor wafer contains a plurality of semiconductor die with bumps formed over contact pads on an active surface of the semiconductor die. An ACF is deposited over the bumps and active surface of the wafer. An insulating layer can be formed between the ACF and semiconductor die. The semiconductor wafer is singulated to separate the die. The semiconductor die is mounted to a temporary carrier with the ACF oriented to the carrier. The semiconductor die is forced against the carrier to compress the ACF under the bumps and form a low resistance electrical interconnect to the bumps. An encapsulant is deposited over the semiconductor die and carrier. The carrier is removed. An interconnect structure is formed over the semiconductor die and encapsulant. The interconnect structure is electrically connected through the compressed ACF to the bumps. The ACF reduces shifting of the semiconductor die during encapsulation.

Abstract: A semiconductor device includes first, second, and third conductive lines, each with a respective line portion formed over a substrate and extending in a first direction and with a respective branch portion extending from an end of the respective line portion in a direction different from the first direction. The branch portion of a middle conductive line is disposed between and shorter than the respective branch portions of the outer conductive lines such that contact pads may be formed integral with such branch portions of the conductive lines.

Abstract: A microelectronic package includes a substrate (110), a die (120) embedded within the substrate, the die having a front side (121) and a back side (122) and a through-silicon-via (123) therein, build-up layers (130) built up over the front side of the die, and a power plane (140) in physical contact with the back side of the die. In another embodiment, the microelectronic package comprises a substrate (210), a first die (220) and a second die (260) embedded in the substrate and having a front side (221, 261) and a back side (222, 262) and a through-silicon-via (223, 263) therein, build-up layers (230) over the front sides of the first and second dies, and an electrically conductive structure (240) in physical contact with the back sides of the first and second dies.

Abstract: A semiconductor die and semiconductor package formed therefrom, and methods of fabricating the semiconductor die and package, are disclosed. The semiconductor die includes an edge formed with a plurality of corrugations defined by protrusions between recesses. Bond pads may be formed on the protrusions. The semiconductor die formed in this manner may be stacked in the semiconductor package in staggered pairs so that the die bond pads on the protrusions of a lower die are positioned in the recesses of the upper die.

Abstract: The present invention provides an interconnect structure in which a patternable low-k material is employed as an interconnect dielectric material. Specifically, this invention relates to single-damascene and dual-damascene low-k interconnect structures with at least one patternable low-k dielectric. In general terms, the interconnect structure includes at least one patterned and cured low-k dielectric material located on a surface of a substrate. The at least one cured and patterned low-k material has conductively filled regions embedded therein and typically, but not always, includes Si atoms bonded to cyclic rings via oxygen atoms. The present invention also provides a method of forming such interconnect structures in which no separate photoresist is employed in patterning the patterned low-k material.

Abstract: In accordance with the present invention, there is provided multiple embodiments of a semiconductor package including at least two electronic components which are provided in a stacked arrangement, and are each electrically connected to an underlying substrate through the use of conductive wires. In accordance with one embodiment of the present invention, the electronic components are separated from each other by an intervening spacer which is typically fabricated from aluminum, or from silicon coated with aluminum. In this particular embodiment, the uppermost electronic component of the stack is electrically connected to at least one of the conductive wires through the use of a conductive paste layer which is also used to secure the uppermost electronic component to the underlying spacer.

Abstract: The present invention relates to a semiconductor package and a method for making the same. The semiconductor package includes a first chip and a second chip. The first chip comprises a first active surface, at least one first non-top metal layer and a plurality of first signal coupling pads. The first non-top metal layer is disposed adjacent to and spaced apart from the first active surface by a second distance. The first signal coupling pads are disposed on the first non-top metal layer. The second chip is electrically connected to the first chip. The second chip comprises a second active surface, at least one second non-top metal layer and a plurality of third signal coupling pads. The second active surface faces the first active surface of the first chip. The second non-top metal layer is disposed adjacent to and spaced apart from the second active surface by a fourth distance.

Abstract: An MCP type semiconductor memory device having a structure in which a stack memory chip including a plurality of stacked memory chips and a memory controller chip are juxtaposed on a substrate is provided, which achieves a reduction in package size. The semiconductor memory device includes a stack memory chip including a plurality of stacked memory chips, a substrate on which the stack memory chip is provided, and a memory controller chip provided adjacent to the stack memory chip on the substrate. The stack memory chip is constructed such that an upper memory chip is stacked so as to shift toward a mounting position of the memory controller chip relative to a memory chip immediately below the upper memory chip. At least a part of the memory controller chip is received within a space between the substrate and a part of the stack memory chip that protrudes toward the memory controller chip.

Abstract: A semiconductor device has a substrate and RF FEM formed over the substrate. The RF FEM includes an LC low-pass filter having an input coupled for receiving a transmit signal. A Tx/Rx switch has a first terminal coupled to an output of the LC filter. A diplexer has a first terminal coupled to a second terminal of the Tx/Rx switch and a second terminal for providing an RF signal. An IPD band-pass filter has an input coupled to a third terminal of the Tx/Rx switch and an output providing a receive signal. The LC filter includes conductive traces wound to exhibit inductive and mutual inductive properties and capacitors coupled to the conductive traces. The IPD filter includes conductive traces wound to exhibit inductive and mutual inductive properties and capacitors coupled to the conductive traces. The RF FEM substrate can be stacked over a semiconductor package containing an RF transceiver.

Abstract: An electrostatic discharge (ESD) protection scheme for a semiconductor device stacking process is provided, in which an equivalent electrical resistance of a specific path is designed to be less than an equivalent electrical resistance of other paths. Accordingly, when a first active layer and a second active layer in the semiconductor device are stacked, by designing suitable ESD protection cells on such a specific path, electrical charges accumulated on the top layer wafer (or die) select such a specific path over the other paths to be released to the grounded bottom layer wafer (or die), so as to achieve an ESD protection effect. In addition, since such a specific path also serves as a heat dissipation path in a three dimensional integrated circuit (3D IC), an overall heat resistance of the 3D IC may be reduced to improve a heat dissipation effect.

Abstract: A method of topside only dual-side testing of an electronic assembly includes providing a singulated through substrate via (TSV) die flip chip attached to a die support including a package substrate. The TSVs on the TSV die extend from its frontside to contactable TSV tips on its bottomside. The TSVs on the frontside of the TSV die are coupled to embedded topside substrate pads on a top surface of the ML substrate. The die support includes lateral coupling paths between at least a portion of the embedded topside substrate pads and lateral topside pads on a topside surface of the die support lateral to the die area. The contactable TSV tips are contacted with probes to provide a first topside connection to the TSVs, and the lateral topside pads are contacted with probes to provide a second topside connection. Dual-side testing across the electronic assembly is performed using the first and second topside connections.

Abstract: A device is provided that includes a first conductive substrate and a second conductive substrate. A first power semiconductor component having a first thickness can be electrically coupled to the first conductive substrate. A second power semiconductor component having a second thickness can be electrically coupled to the second conductive substrate. A positive terminal can also be electrically coupled to the first conductive substrate, while a negative terminal can be electrically coupled to the second power semiconductor component, and an output terminal may be electrically coupled to the first power semiconductor component and the second conductive substrate. The terminals, the power semiconductor components, and the conductive substrates may thereby be incorporated into a common circuit loop, and may together be configured such that a width of the circuit loop in at least one direction is defined by at least one of the first thickness or the second thickness.

Abstract: The present invention relates to a semiconductor package. The semiconductor package includes a substrate, a first chip and a second chip. The substrate has a first surface, a second surface and at least one through hole. The first chip is disposed adjacent to the first surface of the substrate. The first chip includes a first active surface and a plurality of first signal pads. Part of the first active surface is exposed to the through hole. The position of the first signal pads corresponds to the through hole. The second chip is disposed adjacent to the second surface. The second chip includes a second active surface and a plurality of second signal pads. Part of the second active surface is exposed to the through hole. The position of the second signal pads corresponds to the through hole, and the second signal pads are capacitively coupled to the first signal pads of the first chip, so as to provide proximity communication between the first chip and the second chip.

Abstract: Ultra-low power single metallic single-wall-nano-tube (SWNT) interconnects for sub-threshold circuits are provided. According to some embodiments, an interconnect structure for use in electronic circuits can generally comprise a first substrate, a second substrate, and an interconnect. The first substrate can be spaced apart from the second substrate. The interconnect is preferably a single wall carbon nanotube (SWNT) interconnect. The SWNT interconnect can be disposed between the first and second substrates to electrically connect the substrates. The substrates can form parts of electrical components (e.g., a transistor, processor, memory, filters, etc.) operating in a subthreshold operational state. Other aspects, features, and embodiments are claimed and described.

Abstract: A semiconductor package has a first substrate having a plurality of electrically conductive patterns formed thereon. A first semiconductor die is coupled to the plurality of conductive patterns. A second semiconductor die is coupled to the first semiconductor die by a die attach material. A third semiconductor die is coupled to the second semiconductor die by a die attach material. A second substrate having a plurality of electrically conductive patterns formed thereon is coupled to the third semiconductor die. A plurality of contacts is coupled to a bottom surface of the first substrate. A connector jack is coupled to the second substrate. A plurality of leads is coupled to the second semiconductor die by conductive wires.

Abstract: A semiconductor circuit structure includes an interconnect region, and a material transfer region. The semiconductor circuit structure includes a conductive bonding region which couples the material transfer region to the interconnect region through a bonding interface. The conductive bonding region includes a barrier layer between a conductive layer and bonding layer. The bonding layer is positioned towards the material transfer region, and the conductive layer is positioned towards the interconnect region.

Abstract: A semiconductor component and methods for manufacturing the semiconductor component that includes a monolithically integrated common mode choke. In accordance with embodiments, a transient voltage suppression device may be coupled to the monolithically integrated common mode choke.

Abstract: A semiconductor wafer comprises a first chip and a second chip, each chip comprising a core, link layer and physical layer. A kerf area physically connects the two chips on the wafer, and a kerf area interconnect selectively couples the link layers of the two chips while the two physical layers are disabled.

Abstract: A semiconductor integrated circuit having a multi-chip structure includes a number of stacked semiconductor chips. Each of the semiconductor chips includes a first through electrode formed through the semiconductor chip, a first bump pad formed over the semiconductor chip at a region where the first bump pad is separated from the first through electrode, a first internal circuit formed inside the semiconductor chip, coupled to the first through electrode through a first metal path, and coupled to the first bump pad through a second metal path; and a redistribution layer (RDL) formed over a backside of the semiconductor chip.

Abstract: The present invention relates to a semiconductor package and method for making the same. The semiconductor package includes a silicon substrate unit, a bridge chip and at least one active chip. The silicon substrate unit has a cavity and a plurality of vias. The bridge chip is attached to the cavity and has a plurality of non-contact pads. The active chip is disposed above the bridge chip and has a plurality of non-contact pads and a plurality of conducting elements. The conducting elements of the active chip contact the vias of the silicon substrate unit, the non-contact pads of the active chip face but are not in physical contact with the non-contact pads of the bridge chip, so as to provide proximity communication between the active chip and the bridge chip.

Abstract: A package system includes a first integrated circuit disposed over an interposer. The interposer includes at least one molding compound layer including a plurality of electrical connection structures through the at least one molding compound layer. A first interconnect structure is disposed over a first surface of the at least one molding compound layer and electrically coupled with the plurality of electrical connection structures. The first integrated circuit is electrically coupled with the first interconnect structure.

Abstract: A multi-chip stacked package primarily comprises a chip carrier, a first chip disposed on the chip carrier, a plurality of die-attaching bars, a second chip stacked on the first chip by the adhesion of the die-attaching bars, and a plurality of bonding wires electrically connecting the first chip to the chip carrier. The die-attaching bars are formed on the first chip in a specific pattern and have an adhesive surface away from the first chip for adhering the second chip. The bonding wires have a loop height lower than the adhesive surface in a manner that specific sections of the bonding wires are embedded in the corresponding die-attaching bar from the adhesive surface. Accordingly, the die-attaching bars can modify and fasten the bonding wires in advance to avoid collapse and deformation of the bonding wires during stacking of the second chip and encapsulating processes.

Abstract: An impurity element imparting one conductivity type is included in a layer close to a gate insulating film of layers with high crystallinity, so that a channel formation region is formed not in a layer with low crystallinity which is formed at the beginning of film formation but in a layer with high crystallinity which is formed later in a microcrystalline semiconductor film. Further, the layer including an impurity element is used as a channel formation region. Furthermore, a layer which does not include an impurity element imparting one conductivity type or a layer which has an impurity element imparting one conductivity type at an extremely lower concentration than other layers, is provided between a pair of semiconductor films including an impurity element functioning as a source region and a drain region and the layer including an impurity element functioning as a channel formation region.

Abstract: A semiconductor device has a semiconductor die with a plurality of bumps formed over a surface of the first semiconductor die. A penetrable adhesive layer is formed over a temporary carrier. The adhesive layer can include a plurality of slots. The semiconductor die is mounted to the carrier by embedding the bumps into the penetrable adhesive layer. The semiconductor die and interconnect structure can be separated by a gap. An encapsulant is deposited over the first semiconductor die. The bumps embedded into the penetrable adhesive layer reduce shifting of the first semiconductor die while depositing the encapsulant. The carrier is removed. An interconnect structure is formed over the semiconductor die. The interconnect structure is electrically connected to the bumps. A thermally conductive bump is formed over the semiconductor die, and a heat sink is mounted to the interconnect structure and thermally connected to the thermally conductive bump.

Abstract: Scalable transfer-join bonding techniques are provided. In one aspect, a transfer-join bonding method is provided. The method includes the following steps. A first bonding structure is provided having at least one metal pad embedded in an insulator and at least one via in the insulator over the metal pad. The via has tapered sidewalls. A second bonding structure is provided having at least one copper stud tapered to complement the tapered sidewalls of the via, such that the via and the copper stud fit together like a lock-and-key. The first bonding structure is bonded to the second bonding structure by way of a metal-to-metal bonding between the metal pad and the copper stud. A transfer join bonded structure is also provided.

Abstract: A through-hole interconnection structure for a semiconductor wafer, in which: the each wafer includes at least a first wafer and a second wafer electrically connected to the first wafer; an electrical signal connecting section of the second wafer is provided to protrude from a bonding surface of the second wafer, the bonding surface being bonded with the first wafer; and the electrical signal connecting section has a cross section with a curved line or two or more straight lines extending in different directions when the second wafer is seen along a cross section parallel to the bonding surface.

Abstract: A method of fabricating a packaging structure includes cutting a panel of packaging substrate into a plurality of packaging substrate blocks each having a plurality of packaging substrate units; mounting and packaging a semiconductor chip on each of the packaging substrate unit to form package blocks each having multiple packaging structure units; and cutting package blocks to form a plurality of package units. In the method, the alignment difference between the packaging structure units in each package block is minimized by appropriately cutting and forming substrate blocks to achieve higher precision and better yield, and also packaging of semiconductor chips can be performed on all package units in the substrate blocks, thereby integrating fabrication with packaging at one time to improve production efficiency and reduce the overall costs as a result.

Abstract: Systems and methods for utilizing power overlay (POL) technology and semiconductor press-pack technology to produce semiconductor packages with higher reliability and power density are provided. A POL structure may interconnect semiconductor devices within a semiconductor package, and certain embodiments may be implemented to reduce the probability of damaging the semiconductor devices during the pressing of the conductive plates. In one embodiment, springs and/or spacers may be used to reduce or control the force applied by an emitter plate onto the semiconductor devices in the package. In another embodiment, the emitter plate may be recessed to exert force on the POL structure, rather than directly against the semiconductor devices. Further, in some embodiments, the conductive layer of the POL structure may be grown to function as an emitter plate, and regions of the conductive layer may be made porous to provide compliance.

Abstract: A package-on-package (POP) package precursor and packaged devices and systems therefrom includes an electronic substrate including electrically conductive layers and a top surface. A first portion of the top surface has an IC die attached thereon. A second portion of the top surface has a plurality of first attach pads on opposing sides of the IC die for electrically coupling to a first electronic device on top of the IC die. At least a third portion of the top surface is positioned laterally with respect to the first and second portion. The third portion includes a plurality of second attach pads for electrically coupling to at least a second electronic device. At least one of the electrically conductive layers includes a coupling trace that couples at least one of the plurality of second attach pads to the IC die and/or one or more of the plurality of first attach pads.

Abstract: A wafer level semiconductor package is provided. A warpage control barrier line formed in every package of a single wafer prevents wafer from warping. The changed shape of the interface between a semiconductor chip and a molding layer at the edge of the package disperses stress applied to the outside of the package, and suppress the generation and propagation of crack. The size of the package is reduced to that of the semiconductor, and the thickness of the package is minimized.

Abstract: A semiconductor device has a thermally-conductive frame and interconnect structure formed over the frame. The interconnect structure has an electrical conduction path and thermal conduction path. A first semiconductor die is mounted to the electrical conduction path and thermal conduction path of the interconnect structure. A portion of a back surface of the first die is removed by grinding. An EMI shielding layer can be formed over the first die. The first die can be mounted in a recess of the thermally-conductive frame. An opening is formed in the thermally-conductive frame extending to the electrical conduction path of the interconnect structure. A second semiconductor die is mounted over the thermally-conductive frame opposite the first die. The second die is electrically connected to the interconnect structure using a bump disposed in the opening of the thermally-conductive frame.

Abstract: A system for interconnecting at least two die each die having a plurality of conducting layers and dielectric layers disposed upon a substrate which may include active and passive elements. In one embodiment there is at least one interconnect coupling at least one conducting layer on a side of one die to at least one conducting layer on a side of the other die. Another interconnect embodiment is a slug having conducting and dielectric layers disposed between two or more die to interconnect between the die. Other interconnect techniques include direct coupling such as rod, ball, dual balls, bar, cylinder, bump, slug, and carbon nanotube, as well as indirect coupling such as inductive coupling, capacitive coupling, and wireless communications. The die may have features to facilitate placement of the interconnects such as dogleg cuts, grooves, notches, enlarged contact pads, tapered side edges and stepped vias.

Abstract: A stack package includes a first package having a first semiconductor chip and a first encapsulation member which seals the first semiconductor chip. A second package is stacked on the first package, and includes a second semiconductor chip and a second encapsulation member which seals the second semiconductor chip. Flexible conductors are disposed within the first encapsulation member of the first package in such a way as to electrically connect the first package and the second package.

Abstract: A system for interconnecting at least two die each die having a plurality of conducting layers and dielectric layers disposed upon a substrate which may include active and passive elements. In one embodiment there is at least one interconnect coupling at least one conducting layer on a side of one die to at least one conducting layer on a side of the other die. Another interconnect embodiment is a slug having conducting and dielectric layers disposed between two or more die to interconnect between the die. Other interconnect techniques include direct coupling such as rod, ball, dual balls, bar, cylinder, bump, slug, and carbon nanotube, as well as indirect coupling such as inductive coupling, capacitive coupling, and wireless communications. The die may have features to facilitate placement of the interconnects such as dogleg cuts, grooves, notches, enlarged contact pads, tapered side edges and stepped vias.

Abstract: A chip stack package includes a plurality of chips that are stacked by using adhesive layers as intermediary media, and a through via electrode formed through the chips to electrically couple the chips. The through via electrode is classified as a power supply through via electrode, a ground through via electrode, or a signal transfer through via electrode. The power supply through via electrode and the ground through via electrode are formed of a first material such as copper, and the signal transfer through via electrode is formed of second material such as polycrystalline silicon doped with impurities. The signal transfer through via electrode may have a diametrically smaller cross section than that of each of the power supply through via electrode and the ground through via electrode regardless of their resistivities.

Abstract: Multiple devices, including a first device and a second device, have operational circuitry and opposing first and second surfaces. First and second electrical contacts are formed at the first surface, while a third electrical contact is formed at the second surface opposite the first electrical contact. The first electrical contact is electrically connected to the operational circuitry, and the second electrical contact is electrically connected to the third electrical contact. The first device and the second device are subsequently stacked such that the first surface of the second device is located adjacent the second surface of the first device such that the first electrical contact of the second device is aligned with the third electrical contact of the first device. The first electrical contact of the second device is electrically connected to the third electrical contact of the first device.

Abstract: A transparent board is positioned on a support board provided with a positioning mark, and a release material is provided. A semiconductor element is then positioned so that the electrode element faces upward, and the support board is then removed. An insulating resin is then formed on the release material so as to cover the semiconductor element; and a via, a wiring layer, an insulation layer, an external terminal, and a solder resist are then formed. The transparent board is then peeled from the semiconductor device through the use of the release material. A chip can thereby be mounted with high precision, there is no need to provide a positioning mark during mounting of the chip on the substrate in the manufacturing process, and the substrate can easily be removed. As a result, a semiconductor device having high density and a thin profile can be manufactured at low cost.

Abstract: A device includes a first semiconductor chip and a first encapsulant that encapsulates the first semiconductor chip and that includes a cavity. A carrier and an electrical component are mounted on the carrier. The carrier is arranged such that the electrical component is enclosed by the cavity.

Abstract: An embodiment of a semiconductor device package includes: (1) an interconnection unit including a patterned conductive layer; (2) an electrical interconnect extending substantially vertically from the conductive layer; (3) a semiconductor device adjacent to the interconnection unit and electrically connected to the conductive layer; (4) a package body: (a) substantially covering an upper surface of the interconnection unit and the device; and (b) defining an opening adjacent to an upper surface of the package body and exposing an upper surface of the interconnect; and (5) a connecting element electrically connected to the device, substantially filling the opening, and being exposed at an external periphery of the device package. The upper surface of the interconnect defines a first plane above a second plane defined by at least a portion of the upper surface of the interconnection unit, and below a third plane defined by the upper surface of the package body.

Abstract: A multi-chip module (MCM) is described in which at least two substrates are mechanically coupled by an adhesive layer that maintains alignment and a zero (or near zero) spacing between proximity connectors on surfaces of the substrates, thereby facilitating high signal quality during proximity communication between the substrates. In order to provide sufficient shear strength, the adhesive layer has a thickness that is larger than the spacing. This may be accomplished using one or more positive and/or negative features on the substrates. For example, the adhesive may be bonded to: one of the surfaces and an inner surface of a channel that is recessed below the other surface; inner surfaces of channels that are recessed below both of the surfaces; or both of the surfaces. In this last case, the zero (or near zero) spacing may be achieved by disposing proximity connectors on a mesa that protrudes above at least one of the substrate surfaces.

Abstract: A semiconductor chip module includes a first flip-chip unit and a second flip-chip unit. The first flip-chip unit has a first chip and a first glass circuit board. The first chip is connected with the first glass circuit board by flip-chip bonding. The second flip-chip unit has a second chip and a second glass circuit board. The second chip is connected with the second glass circuit board by flip-chip bonding. The first flip-chip unit and the second flip-chip unit are attached to each other. A method for manufacturing the semiconductor chip module is also disclosed.

Abstract: A microelectronic assembly including a first and second microelectronic elements. Each of the microelectronic elements have oppositely-facing first and second surfaces and edges bounding the surfaces. The first microelectronic element is disposed on the second microelectronic element with the second surface of the first microelectronic element facing toward the first surface of the second microelectronic element. The first microelectronic element preferably extends beyond at least one edge of the second microelectronic element and the second microelectronic element preferably extends beyond at least one edge of the first microelectronic element.