Abstract: The invention provides a light-emitting device 10 including a light-emitting element 12 and a substrate 11 where the light-emitting element 12 is arranged, characterized in that a housing part 28 housing the light-emitting element 12 and having a shape that is tapered upward from the substrate 11 and a metal frame 15 surrounding the light-emitting element 12 and including the side face 28A of the housing part 28 made into a almost mirror-polished surface are provided on the substrate 11.

Abstract: A semiconductor package includes a base substrate on which semiconductor elements are disposed; a covering member which is provided to the base substrate, which covers the semiconductor elements, and which includes an opening at an end thereof at the side of the base substrate; and a connector substrate which is provided on the base substrate in a manner that the connector substrate closes the opening, which includes a first high-frequency signal line in an area located inside the covering member for a first surface, and which includes a second high-frequency signal line on a second surface being a surface on the opposite side of the first surface, the second high-frequency signal line being electrically connected to the first high-frequency signal line; wherein the base substrate is formed in a manner that the base substrate is located away from the second high-frequency signal line.

Abstract: Various semiconductor chip packages and methods of assembling and making the same are disclosed. In one aspect, a method of manufacturing is provided that includes coupling a stiffener frame to a first side of a substrate. The stiffener frame has a central opening to accommodate a semiconductor chip and an outer edge surface. A semiconductor chip is coupled to the first side in the opening. A lid is coupled to the stiffener frame with an adhesive. The lid has a first edge surface set back from the outer edge surface of the stiffener frame. The adhesive is set back from the outer edge surface of the stiffener frame.

Abstract: An integrated circuit structure is provided. The integrated circuit structure includes a die and an anisotropic conducing film (ACF) adjoining the back surface of the die. The die includes a front surface; a back surface on an opposite side of the die than the front surface; and a through-silicon via (TSV) exposed through the back surface of the die.

Abstract: A light emitting diode package structure having a heat-resistant cover and a method of manufacturing the same include a base, a light emitting diode chip, a plastic shell, and a packaging material. The plastic shell is in the shape of a bowl and has an injection hole thereon. After the light emitting diode chip is installed onto the base, the plastic shell is covered onto the base to fully and air-tightly seal the light emitting diode chip, and the packaging material is injected into the plastic shell through the injection hole until the plastic shell is filled up with the packaging material to form a packaging cover, and finally the plastic shell is removed to complete the LED package structure.

Abstract: An electronic component has a board, a semiconductor element mounted on an upper surface of the board, a ground electrode formed in a region surrounding the semiconductor element on the upper surface of the board, a conductive cap that overlaps the board such that the semiconductor element is covered therewith, and a conductive joining member that joins a whole periphery of a lower surface of the conductive cap to the ground electrode. The conductive cap includes a pressing portion on the lower surface thereof The lower surface of the conductive cap and the ground electrode are joined by the conductive joining member on an outer peripheral side of the pressing portion.

Abstract: This invention provides a magnetic shielding package structure of a magnetic memory device, in which at least a magnetic memory device is embedded between a magnetic shielding substrate and a magnetic shielding layer. A plurality of through vias is formed in the magnetic shielding substrate or the magnetic shielding layer, and a plurality of conductive contacts passes through the through vias such that electrical connection between the magnetic memory device and the external is established.

Abstract: A semiconductor package has a substrate having a first heat transfer path for transferring heat from an optical functional element to a back surface of the substrate, a first heat dissipation unit dissipating the transferred heat therefrom, a second heat transfer path for transferring heat generated in an internal cavity and heat from a window lid itself to a back surface and/or a side surface of the substrate, a second heat dissipation unit dissipating the transferred heat therefrom. The heat transfer paths extend through the substrate and have thermal vias.

Abstract: A device is disclosed which includes, in one illustrative example, an integrated circuit die having an active surface and a molded body extending around a perimeter of the die, the molded body having lips that are positioned above a portion of the active surface of the die. Another illustrative example includes an integrated circuit die having an active surface, a molded body extending around a perimeter of the die and a CTE buffer material formed around at least a portion of the perimeter of the die adjacent the active surface of the die, wherein the CTE buffer material is positioned between a portion of the die and a portion of the molded body and wherein the CTE buffer material has a coefficient of thermal expansion that is intermediate a coefficient of thermal expansion for the die and a coefficient of thermal expansion for the molded body.

Abstract: According to one embodiment, a micro-optical device includes an electro-optical circuit and an annular frame disposed on a surface of a substrate. The electro-optical circuit has an active region that is encapsulated by a window and an interconnect region adjacent at least one edge of the electro-optical circuit. The annular frame extends around an outer periphery of the window and is separated from the window by a gap, the annular frame and the electro-optical circuit form a cavity for placement of a plurality of bonding wires the interconnect that electro-optical circuit to the substrate.

Abstract: A molding compound comprising a resin, a filler, and a carbon nano-tube dispersion is disclosed. The carbon nano-tube dispersion achieves a low average agglomeration size in the molding compound thereby providing desirable electromechanical properties and laser marking compatibility. A shallow laser mark may be formed in a mold cap with a maximum depth of less than 10 microns.

Abstract: A semiconductor sensor device includes a sensor chip. The sensor chip includes a sensor region and contact areas on its upper side and is further arranged in a cavity housing. The cavity housing includes side walls, a housing bottom, a cavity, external contacts on the outside of the cavity and contact pads on an upper side of the housing bottom facing the cavity. The sensor chip is embedded into a rubber-elastic plastic composition within the cavity of the cavity housing such that the sensor region of the sensor chip faces the housing bottom and the contact areas of the sensor chip are electrically connected to the contact pads on the housing bottom via elastic flip-chip contacts.

Abstract: One embodiment of an electronic component packaging system includes a base adapted for supporting an electronic component, a lid sealed to the base, the lid including a fillport, and the fillport hermetically sealed by light irradiation.

Abstract: The present invention provides a semiconductor element mounting substrate 101 including: a base substrate 1 having a region 2 for mounting a semiconductor element 11, the region 2 being set on the major surface of the base substrate 1; a plurality of wiring patterns 3 formed on the base substrate 1 and connected to the semiconductor element 11; and a dummy pattern 8 formed like a frame in the region 2 for mounting the semiconductor element 11 and not connected to the wiring patterns 3.

Abstract: The present invention can prevent a lid from tilting when the lid is attached to a substrate. An electronic device 200 includes: a substrate 202; an electronic component mounted on the substrate 202; and a lid 100 including a cover portion 102 protruding in a direction opposite the substrate 202 and covering the electronic component and a flange portion 104 arranged at the periphery of the cover portion 102 and adhered to the substrate 202. A protrusion portion 106 protruding for a predetermined height in a direction of the substrate 202 compared to other areas of the flange portion 104 is arranged on the flange portion 104 of the lid 100.

Abstract: A method of manufacturing a semiconductor device includes providing a semiconductor substrate having first and second main surfaces opposite to each other. A trench is formed in the semiconductor substrate at the first main surface. The trench extends to a first depth position in the semiconductor substrate. The trench is lined with the dielectric material. The trench is filled with a conductive material. An electrical component is electrically connected to the conductive material exposed at the first main surface. A cap is mounted to the first main surface. The cap encloses the electrical component and the electrical connection.

Abstract: A semiconductor package is disclosed including a plurality semiconductor die mounted on stacked and bonded layers of substrate, for example polyimide tape used in tape automated bonding processes. The tape may have a plurality of repeating patterns of traces and contact pads formed thereon. The traces each include aligned interconnect pads on the respective top and bottom surfaces of the substrate for bonding the traces of one pattern to the traces of another pattern after the patterns have been singulated from the substrate, aligned and stacked. Semiconductor die such as flash memory and a controller die are mounted on the traces of the respective patterns on the substrate. In order for the controller die to uniquely address a specific flash memory die in the stack, a group of traces on each substrate supporting the memory die are used as address pins and punched in a unique layout relative to the layout of the traces other substrates.

Abstract: A first container member (9, 109, 212) mounting an electronic device (71, 171, 261) thereon and a second container member (2, 102, 202) are bonded with an adhesive (3, 103) or a metal layer (103, 251). Thus an inner space (90, 190, 211) is formed and the electronic device can be closed in the inner space at a low temperature. In the case the adhesive is used, an exposed surface of the adhesive is coated with a metal film (4) to improve the closeness of the inner space. Further, an electronic device (261, 272) may be mounted on the second container member so as to increase the electronic device arrangement density in a packaged electronic device.

Abstract: A semiconductor device of the invention includes: a substrate having a hollowed hollow section on a top surface; a semiconductor chip mounted in the hollow section of the substrate; and a lid having a substantially plate-shaped top plate section that opposes the substrate and covers the hollow section, and having at least one pair of side wall sections that project from a circumference of the top plate section towards the substrate and that engage with a side surface of the substrate. The substrate and the lid can be accurately positioned.

Abstract: This application relates to a method of manufacturing a semiconductor device comprising: providing a metal carrier; placing the metal carrier into a mold for forming a molded structure holding the metal carrier; segmenting the metal carrier into at least two disconnected metal carrier segments; and attaching a semiconductor chip to the molded structure.

Abstract: A flash memory card and methods of manufacturing same are disclosed. The card includes a semiconductor package fabricated to receive a single-sided or double-sided lid. A surface of the semiconductor package may be formed with holes, trenches and/or pockmarks. After the holes, trenches and/or pockmarks are formed, a lid may be attached to the package surface in an injection molding process. During the injection molding process, the molten plastic flows into the holes, trenches and/or pockmarks to interconnect with the surface of the semiconductor package. Thus, when the molten plastic hardens, the holes, trenches and/or pockmarks ensure that the lid remains firmly attached to semiconductor package.

Abstract: A dynamic quantity sensor includes a sensor chip having a movable portion at one surface side thereof and a silicon layer at another surface side thereof. The movable portion is displaced under application of a dynamic quantity. The silicon layer is separated from the movable portion through an insulator. The dynamic quantity sensor also includes a circuit chip for transmitting/receiving electrical signals to/from the sensor chip. The circuit chip is disposed to confront the one surface of the sensor chip through a gap portion and cover the movable portion. The sensor chip and the circuit chip are bonded to each other around the gap portion so that a bonding portion is formed to substantially surround the gap portion and thereby seal the gap portion.

Abstract: The invention relates to a miniature microwave package comprising a microwave chip (60) having an active face (62). The chip includes a protective lid (72) fixed to the active face, at least partially covering it, the lid including at least one recess forming, with the active face of the chip, a cavity (94, 96, 98). The invention is used in miniature microwave packages.

Abstract: A semiconductor device of the invention includes: a substrate having a hollowed hollow section on a top surface; a semiconductor chip mounted in the hollow section of the substrate; and a lid having a substantially plate-shaped top plate section that opposes the substrate and covers the hollow section, and having at least one pair of side wall sections that project from a circumference of the top plate section towards the substrate and that engage with a side surface of the substrate. The substrate and the lid can be accurately positioned.

Abstract: A method (200) is provided for reducing stresses applied to one or more bonded interconnects (106) of a substrate (103) and a PCB (Printed Circuit Board) (104). The method comprises the steps of coupling (204) a compound (108) on a top surface of the substrate, wherein the compound has the property of expanding when a heat profile is applied thereto, coupling (206) a cover (102) to the PCB that overhangs at least a portion of the compound, and applying (208) the heat profile to the compound and optionally the cover and/or PCB. More than one apparatus implementing the method is also included.

Abstract: The microcavity is delineated by a cover which is formed on a sacrificial layer and in which at least one hole is formed for removal of the sacrificial layer. A plug covers the hole and part of the cover along the periphery of the hole. The plug is made from a material that can undergo creep deformation and can be a polymerized material, in particular selected from photoresists and polyimide, or glass, in particular selected from phosphosilicate glasses. A sealing layer is deposited on the plug and the cover such as to seal the microcavity hermetically. The hole has, for example, a dimension of less than 5 micrometers and is preferably arranged on the highest part of the microcavity. The plug can have a thickness of between 2 and 6 micrometers.

Abstract: A disclosed semiconductor device comprises a substrate, an element on the substrate and a sealing structure for sealing the element. The sealing structure has a structure such that a partition wall made of a metallic material formed on the substrate by a plating method so as to surround the element and a cap portion disposed on the partition wall are bonded via a bonding layer made of an inorganic material.

Abstract: A semiconductor package includes a semiconductor die. Encapsulant is flowed around a portion of the semiconductor die. The encapsulant is etched and a conductive material is deposited into the etched portion of the encapsulant to form a thermally conductive structure. In one embodiment, a trench is etched into the encapsulant and a thermally conductive material is deposited into the trench to form a thermal channel. In alternative embodiments, thermally conductive through hole vias (THVs) are formed in the encapsulant. A thermally conductive pad may be formed over the semiconductor die to facilitate removal of heat energy from the hot spots of the semiconductor die. A thermally conductive trace is formed to interconnect the thermal channel and the thermally conductive pad. A heat sink may be deposited over the semiconductor package. The packages are singulated by cutting through the encapsulant or the thermal channel.

Abstract: A cap wafer, fabrication method, and a semiconductor chip are provided. The cap wafer includes a cap wafer substrate; a penetrated electrode formed to penetrate the cap wafer substrate; and an electrode pad connected with a lower portion of the penetrated electrode on a lower surface of the cap wafer substrate, wherein the penetrated electrode has an oblique section which gradually widens from an upper surface to the lower surface of the cap wafer substrate. The fabrication method includes forming an oblique-via hole on a lower surface of a cap wafer substrate, the oblique-via hole having an oblique section which gradually narrows in a direction moving away from the lower surface of the cap wafer substrate; and forming a penetrated electrode in the oblique-via hole. The semiconductor chip includes a base wafer; a cap wafer; a cavity; a penetrated electrode; and a pad bonding layer.

Abstract: A semiconductor device comprises: (a) a wiring board having front surface lands disposed on a front surface and rear surface lands disposed on a rear surface; (b) a semiconductor chip formed with an integrated circuit and electrode terminals electrically connected to the integrated circuit; and (c) a sealing resin that covers a front side of the wiring board when the semiconductor chip is mounted on the front side of the wiring board such that the front surface lands and the rear surface lands are electrically connected to the electrode terminals, wherein (d) holes having a shape and dimensions that allow projecting electrodes of the other semiconductor device to be inserted therein are formed in the sealing resin such that the front surface lands disposed further toward an inner side than a front surface of the semiconductor chip are exposed.

Abstract: A multi-lid semiconductor package includes one or more die disposed on a substrate, an interconnect disposed on the substrate, one or more die lids, a die thermal interface between the one or more die and the corresponding die lid or lids, one or more substrate lids, and a substrate interface between the substrate and the corresponding substrate lid or lids. The multi-lid semiconductor package may include one or more discrete surface mount components disposed on the substrate. The multi-lid semiconductor package may include a sealant between the one or more die lids and the one or more substrate lids and the substrate. The one or more die lids and the one or more substrate lids may differ in construction, design, placement, and/or thermal performance.

Abstract: A hermetic MEMS device (100) comprising a carrier (110) having a surface (111) including a device (101) and an attachment stripe (122), the stripe spaced from the device and surrounding the device; a metallic foil (102) having a central bulge portion (103) and a peripheral rim portion (104) meeting the stripe, the bulge cross section parallel to the carrier monotonically decreasing from the rim (104) towards the bulge apex (105); and the foil positioned over the carrier surface so that the bulge arches over the device and the rim forms a seal with the stripe.

Abstract: Single-die or multi-die packaged modules that incorporate three-dimensional integration of active devices with discrete passive devices to create a package structure that allows active devices (such as, silicon or gallium-arsenide devices) to share the same footprint area as an array of passive surface mount components. In one example, a module includes at least one active device stacked on top of an array of passive surface mount components on a substrate. A conductive or non-conductive adhesive can be used to adhere the active device to the array of passive devices.

Abstract: An RF power transistor package with a rectangular ceramic base can house one or more dies affixed to an upper surface of the ceramic base. Source leads attached to the ceramic base extend from at least opposite sides of the rectangular base beneath a periphery of a non-conductive cover overlying the ceramic base. The cover includes recesses arranged to receive the one or more die, the ceramic base, gate and drain leads and a portion of the source leads. The cover further includes bolt holes arranged to clamp the ceramic base and source leads to a heat sink. Bosses at corners of the cover outward of the bolt holes exert a downward bowing force along the periphery of the cover between the bolt holes.

Abstract: A semiconductor device according to the invention is a semiconductor device which includes a low dielectric constant film of which the relative dielectric constant is less than 3.5, is provided with one or more seal rings that are moisture blocking walls in closed loop form in a plan view, and where at least one of the seal rings includes a seal ring protrusion portion in inward protruding form in the vicinity of a chip corner.

Abstract: A cap wafer with cavities is etched through areas not covered by a patterned photoresist to form a plurality of openings. The cap wafer is bonded to a transparent wafer at the surface having the cavities and is segmented around the cavities to form a plurality of cap structures. The cap structures are hermetically sealed to a device wafer to form hermetic windows over devices and pads located on the device wafer.

Abstract: A semiconductor device includes: a substrate; a semiconductor chip that is fixed to a first surface of the substrate; a chip covering lid body that is provided on the first surface of the substrate so as to cover the semiconductor chip and that forms a hollow first space portion that surrounds the semiconductor chip, and in which there is provided a substantially cylindrical aperture portion that extends to the outer side of the first space portion and has an aperture end at a distal end thereof and that is connected to the first space portion; and a first resin mold portion that forms the first space portion via the chip covering lid body and covers the substrate such that the aperture end is exposed, and that fixes the substrate integrally with the chip covering lid body.

Abstract: A semiconductor package includes a semiconductor chip having an upper surface, side surfaces connected with the upper surface, and bonding pads formed on the upper surface. A first insulation layer pattern is formed to cover the upper surface and the side surfaces of the semiconductor chip and expose the bonding pads. Re-distribution lines are placed on the first insulation layer pattern and include first re-distribution line parts and second re-distribution line parts. The first re-distribution line parts have an end connected with the bonding pads and correspond to the upper surface of the semiconductor chip and the second re-distribution line parts extend from the first re-distribution line parts beyond the side surfaces of the semiconductor chip. A second insulation layer pattern is formed over the semiconductor chip and exposes portions of the first re-distribution line parts and the second re-distribution line parts.

Abstract: An optoelectronic component (1) having a semiconductor arrangement (4) which emits and/or receives electromagnetic radiation and which is arranged on a carrier (22) which is thermally conductively connected to a heat sink (12). External electrical connections (9) are connected to the semiconductor arrangement (4), where the external electrical connections (9) are arranged in electrically insulated fashion on the heat sink (12) at a distance from the carrier (22). This results in an optimized component in terms of the dissipation of heat loss and the radiation of light and also in terms of making electrical contact and the packing density in modules.

Abstract: A chip package is disclosed. The chip package comprises a chip, a plurality of bond pads, a plurality of connecting lines and a rigid cover. The chip has a plurality of recesses arranged along at least an edge of the chip and also has an active surface and a backside. The bond pads are disposed on the active surface and the bond pads are arranged to be corresponding to the recesses respectively. The connecting lines are disposed on surfaces of the recesses respectively at the edge of the chip. For each of the connecting lines, a first end of the connecting line is connected to one of the bond pads and a second end of the connecting line extends to the backside to be a terminal pad. The rigid cover is located on the active surface without covering the bond pads on the active surface.

Abstract: Methods and apparatus for improved thermal performance and electromagnetic interference (EMI) shielding in integrated circuit (IC) packages is described. A die-up or die-down package includes a heat spreader cap defining a cavity, an IC die, and a leadframe. The leadframe includes a centrally located die attach pad, a plurality of leads, and a plurality of tie bars that couple the die attach pad to the leads. The IC die is mounted to the die attach pad. A planar rim portion of the cap that surrounds the cavity is coupled to the leadframe. The cap and the leadframe form an enclosure structure that substantially encloses the IC die, and shields EMI emanating from and radiating towards the IC die. The enclosure structure also dissipates heat generated by the IC die during operation.

Abstract: A molded leadless package (MLP) semiconductor device includes a heat spreader with a single connecting projection extending from an edge of a cap of the heat spreader to a leadframe. The heat spreader can include additional projections on its edges that act as heat collectors and help to secure the spreader in the MLP. The connecting projection is attached to a lead of the leadframe so that heat gathered by the cap can be transferred through the connecting projection to the lead and to a printed circuit board to which the lead is connected. In embodiments, the heat spreader includes a central heat collector projection from the cap toward the die, preferably in the form of a solid cylinder, that enhances heat collection and transfer to the cap. The cap can include fins projecting from its top surface to facilitate radiant and convection cooling.

Abstract: Various semiconductor chip packages and methods of making the same are provided. In one aspect, a method of manufacturing is provided that includes providing a substrate that has a first side and a first plurality of passive devices on the first side. A stiffener frame is coupled on the first side. The stiffener frame has first and second spaced apart opposing walls that define a channel in which the first plurality of passive devices is positioned, and a central opening that does not cover a central portion of the first side of the substrate.

Abstract: An apparatus for heatsink attachment and a method for forming the apparatus. The apparatus includes a substrate, a semiconductor chip on top of and physically attached to the substrate, and a lid on top of the substrate. The lid includes a first thermally conductive material. The apparatus further includes a heatsink on top of the lid. The heatsink includes a second thermally conductive material. The semiconductor chip and the substrate share a common interface surface that defines a reference direction perpendicular to the common interface surface and pointing from the substrate towards the semiconductor chip. The lid is disposed between the substrate and the heatsink. The lid includes a first protruding member. The first protruding member of the lid is farther away from the substrate than a portion of the heatsink in the reference direction.

Abstract: The present invention provides a semiconductor device capable of being mass-produced and a manufacturing method of the semiconductor device. The present invention also provides a semiconductor device using an extreme thin integrated circuit and a manufacturing method of the semiconductor device. Further, the present invention provides a low power consumption semiconductor device and a manufacturing method of the semiconductor device. According to one aspect of the present invention, a semiconductor device that has a semiconductor nonvolatile memory element transistor over an insulating surface in which a floating gate electrode of the memory transistor is formed by a plurality of conductive particles or semiconductor particles is provided.

Abstract: MEMS packaging schemes having a system-on-package (SOP) configuration and a system-on-board (SOB) configuration are provided. The MEMS package comprises one or more MEMS dies, a cap section having one or more integrated circuit (IC) dies, and a packaging substrate or a printed circuit board (PCB) arranged in a stacking manner. Vertical connectors, such as through-silicon-vias (TSVs), are formed to provide short electrical connections between the various components. The MEMS packaging schemes enable higher integration density, reduced MEMS package footprints, reduced RC delays and power consumption.

Abstract: In an imaging apparatus constituted of a case body for mounting an imaging device and a flexible substrate bonding to an external connection terminal provided on the case body, the flexible substrate is bent along each face of case body 41 so as to surround case body 41. By bending the flexible substrate, a load applied to the flexible substrate is received at the bent portion of the flexible substrate, there is formed a structure hard to transmit the load to the bonding portion to the external connection terminal. Further, by fixing the case body to a portion of the flexible substrate with an adhesive agent, etc., there is formed a structure not to transmit a stress to the direction of peeling the flexible substrate from the external connection terminal. Also, the case body is covered with the flexible substrate equipped with an electromagnetic wave shield material.

Abstract: A device according to the present invention includes a MEMS device supported on a first side of a die. A first side of an isolator is attached to the first side of the die. A package is attached to the first side of the isolator, with at least one electrically conductive attachment device attaching the die to the isolator and attaching the isolator to the package. The isolator may include isolation structures and a receptacle.

Abstract: This invention provides a sensor semiconductor package and a method for fabricating the same. The method includes: mounting on a substrate a sensor chip having a sensor area; electrically connecting the sensor chip and the substrate by means of bonding wires; forming on a transparent member an adhesive layer with an opening corresponding in position to the sensor area; and mounting the transparent member on the substrate via the adhesive layer while heating the substrate, such that the adhesive layer melts, to thereby encapsulate the periphery of the sensor chip and the bonding wires while exposing the sensor area from the adhesive layer. Thus, the sensor area is sealed by the transparent member cooperative with the adhesive layer, making the sensor semiconductor package thus-obtained dam-free, light, thin, and compact, and incurs low process costs. Also, the product reliability is enhanced since the bonding wires are encapsulated by the adhesive layer without severing concern.

Abstract: A semiconductor chip package is provided. The semiconductor chip package comprises a package substrate having a first surface and a second surface opposite to the first surface. A through hole extends through the package substrate. A semiconductor chip is disposed on the first surface of the package substrate, wherein a bottom surface of the semiconductor chip covers one end of the through hole. At least two bonding fingers are disposed on the second surface of the package substrate and arranged on sides of the through hole. A conductive line is disposed on the second surface of the package substrate and between the two bonding fingers and the through hole, wherein two terminals of the conductive line are electrically connected to the two bonding fingers, respectively.