Abstract: A cap member capable of alleviating degradation of reliability and improving fabrication yields is provided. The cap member has a cylindrical side wall portion, a top face portion closing one end of the side wall portion and having a light exit hole formed therein to allow extraction of laser light from a semiconductor laser chip; a light transmission window fitted to the top face portion to stop the light exit hole, and a flange portion arranged at the other end of the side wall portion and welded on the upper face of a stem on which the semiconductor laser chip is mounted. A groove portion is formed in an inner surface of the top face portion, and this groove portion makes part of the top face portion in a predetermined region less thick than the other part thereof.

Abstract: The power semiconductor package includes a semiconductor mounting substrate, a mother case having an opening and containing the semiconductor mounting substrate therein, a securing member having a plurality of securing positions formed along a rim constituting the opening, and a screw terminal and a pin terminal secured at the rim and electrically connected to the semiconductor mounting substrate. The screw terminal and the pin terminal are each secured by the securing member at one of the plurality of securing positions thereof. Thus, the package can adapt to variation in shape and arrangement of terminals due to differences in circuit configuration and the like of the semiconductor apparatuses, and can reduce restriction on the layout within the enclosure.

Abstract: Various sockets for multiple sizes of chip package substrates are disclosed. In one aspect, an apparatus is provided that includes a socket that has a peripheral wall defining an interior space adapted to receive either of a first semiconductor chip package substrate and a second semiconductor chip package substrate. The first semiconductor chip package substrate has a first size and a first plurality of structural features and the second semiconductor chip package substrate has a second size different than the first size and a second plurality of structural features. The socket has a third plurality of structural features operable to engage the structural features of either of semiconductor chip package substrates to selectively enable the first semiconductor chip package substrate to be located at a first preselected position in the interior space and the second semiconductor chip package substrate to be located at a second preselected position in the interior space.

Abstract: A required number of wiring layers 32 are formed on a temporary substrate 31 of which thermal expansion coefficient differs from that of a semiconductor chip 38 by 2×10?6/° C. or less and a part of the wiring layer of the uppermost layer is exposed to an opening part of an insulating layer 36 of the uppermost layer as a pad 34 and a wiring substrate is fabricated and a solder bonding member of the semiconductor chip 38 is brought into contact with the pad 34 of the wiring substrate and reflow is performed and the semiconductor chip 38 is attached to the wiring substrate 36. Thereafter, an outer peripheral part of the attached semiconductor chip 38 is sealed while exposing an upper surface of the semiconductor chip and removing the temporary substrate 31 and then a terminal for external connection is formed on the wiring substrate.

Abstract: A device including a housing for a semiconductor chip is disclosed. One embodiment provides a plurality of leads. A first lead forms an external contact element at a first housing side and extends at the first housing side into the housing in the direction of an opposite second housing side. The length of the first lead within the housing is greater than half the distance between the first and the second housing side.

Abstract: A semiconductor device includes a substrate, at least one semiconductor element mounted on the substrate, a resin housing for housing the semiconductor element, the resin housing having a cover thereon, at least one pin provided and standing in the resin housing, and at least one printed substrate disposed inside the resin housing or outside the resin housing. The printed substrate and the cover of the resin housing are positioned by the pin.

Abstract: A method for making a semiconductor device includes creating conductive structures on a substrate. Contact pads of a semiconductor die are connected to first ends of conductive structures. The semiconductor die is encapsulated or embedded and the substrate is removed such that second ends of the conductive structures are exposed to the exterior.

Abstract: The present invention provides a wafer level chip size package having cavities within which micro-machined parts are free to move, allowing access to electrical contacts, and optimized for device performance. Also a method for fabricating a wafer level chip size package for MEMS devices is disclosed. This packaging method provides a well packed device with the size much closely to the original one, making it possible to package the whole wafer at the same time and therefore, saves the cost and cycle time.

Abstract: Various semiconductor chip packages and package lids are disclosed. In one aspect, a method of manufacturing is provided that includes forming a semiconductor chip package lid with a peripheral wall that defines a first interior space. A first bridge structure is formed in the first interior space. The first bridge structure is adapted to engage a surface of a substrate.

Abstract: A rectify element as a semiconductor device has a disk section, a first solder part, a buffer plate, a second solder part, a semiconductor chip, and a lead, and a sealing member with which the semiconductor chip is sealed. A cylindrical concave part is formed at one end surface of the disk section. A side wall of the cylindrical concave part faced to an inner peripheral wall at the upper surface of the disk section has a sloped shape of an angle of more than 90° to a contact surface of the upper surface of the disk section on which the semiconductor chip is placed.

Abstract: A semiconductor package including a through-electrode for stacked a semiconductor package and a semiconductor package having the same is disclosed. The semiconductor package through-electrode includes a first electrode having a recessed portion formed therein to pass through a semiconductor chip. A second electrode is disposed within the recess of the first electrode. The first electrode of the semiconductor package through-electrode includes a first metal having a first hardness, and a second electrode comprises a second metal having a second hardness lower than the first hardness. The through-electrode passes through the semiconductor chip body and may be formed with the first metal having the first hardness and/or a first melting point and the second metal having the second hardness and/or a second melting point which are lower than the first hardness and/or the first melting point. This through-electrode allows a plurality of semiconductor packages to be easily stacked.

Abstract: The invention relates to a circuit arrangement with an electronic circuit on a printed circuit board and an electrically screening housing surrounding the circuit board, wherein there are on said circuit board a HF plug-and-socket connector connected to the electronic circuit with an outer conductor part and an inner conductor part, wherein the HF plug-and-socket connector penetrates through an opening in the housing. The outer conductor part of the HF plug-and-socket connector is electrically isolated from the housing, and wherein a tunnel-like screening sleeve surrounds the outer conductor part both axially and circumferentially at least partially, the sleeve being connected electrically to the housing and capacitively to the outer conductor part of the HF plug-and-socket connector.

Abstract: A semiconductor sensor device and method is disclosed. In one embodiment, the semiconductor device includes a cavity housing and a sensor chip. In one embodiment, the cavity housing has an opening to the surroundings. The sensor region of the sensor chip faces said opening. The sensor chip is mechanically decoupled from the cavity housing. In one embodiment, the sensor chip is embedded into a rubber-elastic composition on all sides in the cavity of the cavity housing.

Abstract: An integrated circuit structure is provided. The integrated circuit structure includes a die and an anisotropic conducing film (ACF) adjoining the back surface of the die. The die includes a front surface; a back surface on an opposite side of the die than the front surface; and a through-silicon via (TSV) exposed through the back surface of the die.

Abstract: A semiconductor device and a fabrication method thereof are provided. An opening having at least one slanted side is formed on a substrate. At least one chip and at least one passive component are mounted on the substrate. An encapsulant having a cutaway corner is formed on the substrate to encapsulate the chip and the passive component, wherein the cutaway corner of the encapsulant is spaced apart from the slanted side of the opening by a predetermined distance. A singulation process is performed to cut the encapsulant to form a package with a chamfer. The package is embedded in a lid to form the semiconductor device, wherein a portion of the substrate located between the slanted side of the opening and the cutaway corner of the encapsulant is exposed from the encapsulant to form an exposed portion. The present invention also provides a carrier for the semiconductor device.

Abstract: The invention relates to a semiconductor device comprising through contacts through a plastic housing composition and a method for the production thereof. For this purpose, the wiring substrate has a solder deposit on which through contact elements are arranged vertically with respect to the wiring substrate and extend as far as the top side of the semiconductor device.

Abstract: A stress-isolated MEMS device (14) includes a platform (26) suspended over a substrate wafer (24). In one embodiment, the platform (26) is suspended by springs (38), but other suspension techniques may also be used. A transducer (28) is formed over the platform (26). The transducer (28) includes immovable portions (50) and movable portions (52). The transducer (28) and platform (26) are sealed within a cavity (62) formed within a cap support (30) between a cap wafer (32) and the substrate wafer (24). A leadframe (22) is affixed to the substrate wafer (24). The cap wafer (32) and other portions of the device (14) become embedded in a package material (20) so that a substantially solid boundary forms between the cap wafer (32) and the package material (20).

Abstract: A chip stacked package structure and applications are provided, wherein the chip stacked package structure comprises a substrate, a first chip, circuit board and a second chip. The substrate has a first surface and an opposite second surface. The first chip having a first active surface and an opposite first rear surface is electrically connected to first surface of substrate serving by a flip chip bonding process. The circuit board has a dielectric layer set on the first rear surface and a patterned conductive layer set on the dielectric layer is electrically connected to the substrate via a bonding wire. The second chip set on the patterned conductive layer has a plurality of second pads formed on a second active surface thereof and eclectically connected to the patterned conductive layer.

Abstract: The present invention relates to an electronic device whose component body contains at least one stress relief element (4), a substrate (1) with an upper surface and side walls at least one circuit element (2) located on said substrate (1) and at least one passivation and/or isolating layer (3) placed on said substrate (1), whereby said isolating layer (3) covers said at least one circuit element (2) and/or said substrate (1) and contains a top surface, at least one outer side surface which is located towards a side wall of said substrate and at least one outer edge, which is formed by said top surface and said at least one outer side surface, characterized in that at least one stress relief element (4) is made out of a ductile material and simultaneously a) covers the top surface of said passivation and/or isolating layer (3); and b) overlaps said outer edge of said passivation and/or isolating layer (3); and c) extends along said outer surface of said passivation and/or isolating layer (3); and d1) con

Abstract: In a ceramic package including one or more ceramic layers and being capable of having an electronic component and a lid fixed to a surface thereof, a surface of a ceramic layer having a sealing electrode for joining the lid through a sealing member and a pad to be connected to input and output electrodes and/or a ground electrode of the electronic component is divided into an inner portion having the pad and an outer portion having the sealing electrode with a stepped side wall as a border for preventing the sealing member from flowing, and one of the inner portion and the outer portion projects relative to the other.

Abstract: A lead structure for a semiconductor component includes: external leads for external connections outside a plastic housing composition, internal leads for electrical connections within the plastic housing composition, and a chip mounting island composed of the lead material. While leaving free contact pads of the internal leads, the top sides of the chip mounting island and the internal leads are equipped with nanotubes as an anchoring layer. The plastic housing composition is arranged in the interspaces between the nanotubes arranged on the internal leads, while an adhesive composition for the semiconductor chip is arranged in the interspaces between the nanotubes arranged on the chip mounting island. The adhesive composition and the plastic housing composition fill the interspaces in a manner free of voids.

Abstract: A structure of semiconductor device package having inter-adhesion with gap comprising: a chip with bonding pads and a sensor area embedded into a substrate with die window and inter-connecting through holes, wherein a RDL is formed over the substrate for coupling between the bonding pads and the inter-connecting through holes; a multiple rings (dam bar) formed over the substrate, the RDL, and the bonding pads area except the sensor area; an adhesive glues fill into the space of the multiple ring except the sensor area; and a transparency material bonded on the top of the multiple ring and the adhesive glues, wherein the adhesive glues adhesion between the transparency material and the multiple rings.

Abstract: A semiconductor device capable of elevating a yield rate of products to improve the productivity and also ensuring high reliability in production and a manufacturing method of the semiconductor device are provided. The semiconductor device includes a semiconductor substrate 2, a MEMS part 3 formed on a surface of the semiconductor substrate 2 and a cap part arranged at a distance from the MEMS part 3 and also arranged on the surface of the semiconductor substrate 2 so as to cover the MEMS part 3. In the semiconductor device, the cap part is formed by a sidewall area E surrounding the MEMS part 3 and a top board area F having a hollow layer and also forming a closed space together with the semiconductor substrate 2 and the sidewall area E.

Abstract: The invention relates to a module comprising a carrier, a first semiconductor chip applied to the carrier and having a movable element and a second semiconductor chip applied to the first semiconductor chip, wherein an active first main surface of the first semiconductor chip faces the carrier and a first cavity is formed between the two semiconductor chips.

Abstract: The present invention provides a semiconductor device package with the multi-chips comprising a substrate with a die receiving through hole, a conductive connecting through holes structure and coupled the first contact pads on an upper surface and second contact pads on a lower surface of the substrate through a conductive connecting through holes. A first die having first bonding pads is disposed within the die receiving through hole. A first adhesion material is formed under the die and a second adhesion material is filled in the gap between the die and sidewall of the die receiving though holes of the substrate. Then, a first conductive wire is formed to couple the first bonding pads and the first contact pads. Further, a second die having second bonding pads is attached on the first die. A second conductive wire is formed to couple the second bonding pads and the first contact pads. A plurality of dielectric layer is formed on the first and second bonding wire, the first and second die and the substrate.

Abstract: A semiconductor sensor for detecting a rotational speed of a rotor is contained in a cylindrical housing, an opening of which is closed with a cover member. The cover member includes a mounting plate integrally molded therewith. Components including a bare sensing chip and other circuit chips are directly mounted on a flat surface of the mounting plate. The components mounted on the flat surface are covered with gel having a high flowability. The gel is prevented from flowing out of the flat surface toward the cover member by banks formed at both sides of the flat surface. On an inner wall of the bank, curved surfaces and depressions are formed to surely suppress creeping up of the gel and to trap the gel therein if it creeps up the inner wall of the bank. Thus, the gel is surely prevented from flowing out even though the banks do not entirely surround the flat mounting surface.

Abstract: A method of fabricating protective caps for protecting devices on wafer surface includes: (a) providing a non-metal cap substrate and forming a metal layer on the non-metal cap substrate; (b) forming a plurality of cavities on a surface of the metal layer, wherein the location of each cavity corresponds to each of the devices on the wafer surface; and (c) forming a protective cap in each cavity and forming a plurality of bonding media around the cavities.

Abstract: A semiconductor device having a topology adjustment and a method for adjusting the topology of a semiconductor device. The semiconductor device includes a semiconductor wafer having first and second opposing sides with an active area formed on a first portion of the first side having a topology extending a first distance above the first side. A support member is attached to a second portion of the first side and extending a second distance above the first side, wherein the first distance is about the same as the second distance. In some exemplary embodiments, the support member is formed by applying adhesive to the second portion. The wafer is then spun to adjust the second distance.

Abstract: A method comprising constraining a circumference of a blank of a Cu—Mo alloy and one of surfaces to be worked with the use of a die, and using a working punch or a counter punch to apply working pressures to the other of the surfaces to be worked, thereby obtaining a cup-shaped body.

Abstract: A cap package for MEMS includes a substrate, a cap made of a carbon added plastic material and capped on the substrate to define with the substrate an accommodation chamber, and a chip mounted on the substrate and located inside the accommodation chamber. The substrate has a conducting portion electrically connected with the cap and grounded.

Abstract: The invention relates to an electronic module having plug contacts, which has a semiconductor chip embedded in a plastics composition with its rear side and its edge sides. An active top side of the semiconductor chip forms, together with the plastics composition, an overall top side, there being arranged on the latter a rewiring layer with plug contact areas and rewiring lines that connect the plug contact areas to contact areas of the top side of the semiconductor chip.

Abstract: An IC chip package includes a substrate (2), a chip (5), a plurality of bonding wires (52), and a cover (6). The substrate has a top surface, a receiving chamber (23) having an opening at the top surface, a plurality of solder pads (3) arranged around the top surface and respectively corresponding to the solder pads arranged at a bottom surface opposite to the top surface, and a plurality of vias (4) having conductive material electrically connecting the top solder pads with the bottom solder pads defined therein. The chip is mounted in the receiving chamber, and has a plurality of chip solder pads (51) arranged around a top surface thereof. The bonding wires respectively electrically connect the top solder pads of the substrate with the chip solder pads. The cover is fastened to the top surface of the substrate, and covers the opening.

Abstract: A chip packaging overflow proof device includes a chip disposed on a substrate; a circuit connected to the chip being provided to each of both sides of the substrate; both of the substrate and the chip being placed in a packaging base; a socket being each provided on both sides of the packaging base to receive insertion by a lid; a first cable-terminating hole being provided between the socket and the lid to permit the circuit to penetrate through; one or a plurality of retaining wall being disposed on the packaging base at where closer to the socket; a second cable-terminating hole being provided on the retaining hole; an overflow space being defined between the retaining wall and the socket; the overflow space being disposed at a level lower than that of the second cable-terminating hole; and the overflow space accepts any squeeze-out from a chip packaging colloid.

Abstract: An electronic component device of the present invention includes: a silicon package unit having a structure in which a through electrode provided to a silicon substrate while an electrode post connected to the through electrode is provided upright on an upper side of the silicon substrate; an electronic component mounted on the electrode post and having a connection terminal connected to the top end of the electrode post; and a cap package unit joined onto a periphery of the silicon package unit, and constructing a housing portion in which the electronic component is housed to be hermetically sealed.

Abstract: A process for fabricating an integrated circuit package includes: selectively etching a first side of a substrate thereby providing etched regions of the substrate to partially define at least a plurality of contact pads; adding a dielectric material to the etched regions of the substrate; selectively etching a second side of the substrate to further define at least the plurality of contact pads and thereby provide a package base of at least the contact pads and the dielectric; mounting a semiconductor die to the package base and connecting the semiconductor die to the contact pads; fixing a lid to the package base to cover the semiconductor die in a cavity between the lid and the package base; and singulating to provide the integrated circuit package.

Abstract: A method relating to a multi-functional, structural circuit, referred to as a structural circuit, is disclosed. The method can include thermoforming a liquid crystal polymer (LCP) circuit with a structural element (215). At least one circuit component can be attached to the surface of the LCP circuit (220).

Abstract: A metal lid for packaging semiconductor chips is stamped to form a sloped sidewall with a set-back from the edge of a package substrate. After the metal lid is placed over the semiconductor chip, molding compound is formed around portions of the exposed perimeter of the package substrate and against the sloped sidewall of the lid. The molding compound securely attaches the lid to the package substrate, providing improved reliability to the lid-substrate joint. The lightweight lid also increases standoff when a solder ball-grid array is used to connect the packaged IC to a printed wiring board, improving the reliability of the ball-grid array connections.

Abstract: A memory module comprises a base plate and one or more IC embedding seats formed thereon to provide IC memory chip being installed in detachable manner taking the advantage of easy installation, convenient maintenance or replacement of IC memory chip, particularly no longer using SMT, soldering paste, or flux for IC maintenance and replacement; the IC embedding seat comprises a mainbody and a sliding cover formed a cover to the mainbody with sliding movement to open or close the mainbody, and the mainbody has one or more IC mounting compartments has a plurality of conducting pin units arrayed in matrix arrangement to form electric connection with the base plate; during IC maintenance and replacement, the defective IC memory chip shall be freely removed from the memory module without de-soldering to prevent other good IC memory chip from damage due to high temperature.

Abstract: A semiconductor device is provided, which is capable of improving mounting flexibility relatively and increasing general versatility, as well as realizing heat radiation characteristics and low on-resistance. Moreover, the semiconductor device is provided, which is capable of improving reliability, performing processing in manufacturing processes easily and reducing manufacturing costs. Also, the semiconductor device capable of decreasing the mounting area is provided. A semiconductor chip in which an IGBT is formed and a semiconductor chip in which a diode is formed are mounted over a die pad. Then, the semiconductor chip and the semiconductor chip are connected by using a clip. The clip is arranged so as not to overlap with bonding pads formed at the semiconductor chip in a flat state. The bonding pads formed at the semiconductor chip are connected to electrodes by using wires.

Abstract: According to the invention, in an assembly comprising an electronic component (108), said component is connected by microbeads (107) to at least one heat sink (106, 109), said beads being connected to electrically-conductive lines on said electronic component and to electrically-conductive lines on at least one heat sink, said beads carrying, on the one hand, electrical signals between the electronic component and each heat sink bearing said electrically-conductive lines and, on the other hand, the heat from the electronic component to each heat sink, via heat conduction.

Abstract: A flash-memory drive replaces a hard-disk drive using an integrated device electronics (IDE) interface. The flash drive has a printed-circuit board assembly (PCBA) with a circuit board with flash-memory chips and a controller chip. The controller chip includes an input/output interface circuit to an external computer over the IDE interface, and a processing unit to read blocks of data from the flash-memory chips. The PCBA is encased inside an upper case and a lower case, with an IDE connector that fits through and opening between the cases. The cases can be assembled with the PCBA by a snap-together, ultrasonic-press, screw-fastener, or thermal-bond adhesive method. Center lines formed on the inside of the cases fit between rows of flash-memory chips to improve case rigidity. The connector has two rows of pins that straddle the center line of the circuit board for a balanced design.

Abstract: The present invention includes the steps of forming a first resin film uncured on a wiring substrate including a wiring pattern, burying an electronic parts having a connection terminal on an element formation surface in the first resin film uncured in a state where the connection terminal is directed upward, forming a second resin film for covering the electronic parts, obtaining an insulation film by curing the first and second resin films by heat treatment, forming a via hole in a predetermined portion of the insulation film on the wiring pattern and the connection terminal, and forming an upper wiring pattern connected to the wiring pattern and the connection terminal through the via hole, on the insulation film.

Abstract: The present invention relates to semiconductor devices. According to the present invention a semiconductor device is described, comprising: a substrate for carrying a semiconductor chip on a first surface of said substrate; said semiconductor chip being punctually attached to said substrate on said first surface of said substrate via a single attachment point; and means for protecting said semiconductor chip on said first surface of said substrate at least protecting said semiconductor chip laterally.

Abstract: A flip chip package generally includes a substrate, a flip chip die, and a heat spreader. The flip chip die is coupled to the substrate. The heat spreader is coupled to the flip chip die. The heat spreader can include one or more walls. Generally, the one or more walls at least partially laterally surround the flip chip die and/or the substrate. The walls can completely laterally surround the flip chip die to define a cavity in the heat spreader. The flip chip package can further include an encapsulate. For example, the encapsulate can be injected between the one or more walls of the heat spreader and the flip chip die and/or other components of the flip chip package. The encapsulate and/or the one or more walls of the heat spreader can protect one or more components of the flip chip package against moisture, corrosives, heat, or radiation, to provide some examples.

Abstract: Heat dissipation apparatus applies to a package device on a substrate. The package device has an upper surface, a bottom surface, and a sidewall between the upper and bottom surfaces, in which the bottom surface thermally contacts the substrate through multitudes of conductive bumps. For dissipating heat from the bottom surface, the heat dissipation apparatus includes a first heat-dissipating structure contacting a portion of the bottom surface and a second heat-dissipating structure on the upper surface. With the surrounding association of the first and the second heat-dissipating structures, these structures release heats from the sidewall of the die. Such a heat dissipation apparatus is capable of discharging heat at three dimensions, preventing the conductive bumps from collapsing, and enhancing reliability.

Abstract: A connecting element for electrically connecting a semiconductor chip and a superordinate circuit board includes an elastic metal strip that is bent forming two metal limbs with flattened limb ends, thus forming a base between the metal limbs which is suitable for contacting and providing electrical connectivity to a plurality of contact pads of a superordinate circuit board. At least one of the two limb ends is electrically connected to the contact areas of a semiconductor chip, while the other limb end is elastically supported on the top side of the semiconductor chip, thereby enabling the connecting element to be self supporting.

Abstract: A semiconductor sensor device includes a sensor chip. The sensor chip includes a sensor region and contact areas on its upper side and is further arranged in a cavity housing. The cavity housing includes side walls, a housing bottom, a cavity, external contacts on the outside of the cavity and contact pads on an upper side of the housing bottom facing the cavity. The sensor chip is embedded into a rubber-elastic plastic composition within the cavity of the cavity housing such that the sensor region of the sensor chip faces the housing bottom and the contact areas of the sensor chip are electrically connected to the contact pads on the housing bottom via elastic flip-chip contacts.

Abstract: An optical device according to the present invention includes a device substrate, a translucent member, an optical element chip and a conductive portion. On a surface of the device substrate, an opening is provided so as to extend substantially in the vertical direction with respect to a surface of the device substrate and pass through the device substrate, the translucent member is provided so as to cover a first opening mouth of the opening, and the optical element chip is provided so as to cover the other opening mouth thereof. Part of the conductive portion is buried in the device substrate. The outline of the first opening mouth has a point-asymmetrical shape with respect to an approximate center point of the first opening mouth.

Abstract: The present invention provides a heat spreader with a bypass capacitor to provide substantially instant power and/or to control simultaneous switching noise (SSN). The present invention also provides a semiconductor device package incorporating this heat spreader. In addition, fabrication methods for such heat spreaders and packages are provided. Generally, the heat spreaders and packages of the present invention include an embedded bypass capacitor that can provide decoupling capacitance in order to deliver near instant power to the die and/or minimize SSN. In a preferred embodiment, the embedded bypass capacitor is connected to terminals integrated with the heat spreader (e.g., lid; stiffener) and/or to a package plane (e.g., power plane or ground plane) in the package substrate for connection via the flip chip package's power delivery system to a power source and/or component.

Abstract: A method for assembling a power semiconductor module with reduced partial discharge behavior is described. The method includes steps of bonding an insulating substrate onto a bottom plate; disposing a first conductive layer on a portion of said insulating substrate, so that at least one peripheral top region of said insulating substrate remains uncovered by the first conductive layer; bonding a semiconductor chip onto said first conductive layer; disposing a precursor of a first insulating material in a first corner formed by the first conductive layer and the peripheral region of the insulating substrate; polymerizing the precursor of the first insulating material to form the first insulating material; and covering the semiconductor chip, said substrate, the first conductive layer, and the first insulating material at least partially with a second insulating material. The precursor of the first insulating material can be a low viscosity monomer or oligomer, preferably a polyimide.