Comprising Group Iii-v Or Ii-vi Compound, Or Of Se, Te, Or Oxide Semiconductor (epo) Patents (Class 257/E29.296)
  • Publication number: 20120153277
    Abstract: A channel layer is formed on a substrate by using an oxide semiconductor and then a sacrificial layer of an oxide containing In, Zn and Ga and representing an etching rate greater than the etching rate of the oxide semiconductor is formed on the channel layer. Thereafter, a source electrode and a drain electrode are formed on the sacrificial layer and the sacrificial layer exposed between the source electrode and the drain electrode is removed by means of wet etching.
    Type: Application
    Filed: December 15, 2011
    Publication date: June 21, 2012
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Seiichiro Yaginuma, Tatsuya Iwasaki, Ryo Hayashi, Hideya Kumomi, Masaya Watanabe
  • Patent number: 8203143
    Abstract: A thin film field effect transistor has at least a gate electrode 2, a gate insulating layer 3, an active layer 4, a source electrode 5-1 and a drain electrode 5-2 on a substrate 1. The active layer includes an amorphous oxide semiconductor including at least In and Zn, a first interface layer 61 is disposed between the gate insulating layer and the active layer such that it is adjacent to at least the active layer, and a second interface layer is disposed on the opposite side of the active layer with respect to the first interface layer such that it is adjacent to the active layer. A content of Ga or Al in the amorphous oxide semiconductor of each of the first interface layer and the second interface layer is higher than a content of Ga or Al in the amorphous oxide semiconductor of the active layer.
    Type: Grant
    Filed: August 11, 2009
    Date of Patent: June 19, 2012
    Assignee: FUJIFILM Corporation
    Inventor: Shinji Imai
  • Publication number: 20120132903
    Abstract: A highly reliable semiconductor device is manufactured by giving stable electric characteristics to a transistor in which an oxide semiconductor film is used for a channel. An oxide semiconductor film which can have a first crystal structure by heat treatment and an oxide semiconductor film which can have a second crystal structure by heat treatment are formed so as to be stacked, and then heat treatment is performed; accordingly, crystal growth occurs with the use of an oxide semiconductor film having the second crystal structure as a seed, so that an oxide semiconductor film having the first crystal structure is formed. An oxide semiconductor film formed in this manner is used for an active layer of the transistor.
    Type: Application
    Filed: November 16, 2011
    Publication date: May 31, 2012
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei YAMAZAKI, Masahiro TAKAHASHI, Tetsunori MARUYAMA
  • Publication number: 20120132904
    Abstract: An object to provide a material suitably used for used for a semiconductor included in a transistor, a diode, or the like, with the use of a sputtering method. Specifically, an object is to provide a manufacturing process an oxide semiconductor film having high crystallinity. By intentionally adding nitrogen to the oxide semiconductor, an oxide semiconductor film having a wurtzite crystal structure that is a hexagonal crystal structure is formed. In the oxide semiconductor film, the crystallinity of a region containing nitrogen is higher than that of a region hardly containing nitrogen or a region to which nitrogen is not intentionally added. The oxide semiconductor film having high crystallinity and having a wurtzite crystal structure is used as a channel formation region of a transistor.
    Type: Application
    Filed: November 16, 2011
    Publication date: May 31, 2012
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventor: Shunpei YAMAZAKI
  • Publication number: 20120132905
    Abstract: An object is to provide a transistor in which the state of an interface between an oxide semiconductor layer and an insulating film (gate insulating layer) in contact with the oxide semiconductor layer is favorable; and a method for manufacturing the transistor. In order to obtain the transistor, nitrogen is added to a region of the oxide semiconductor layer in the vicinity of the interface with the gate insulating layer. Specifically, a concentration gradient of nitrogen is formed in the oxide semiconductor layer, and a region containing much nitrogen is provided at the interface with the gate insulating layer. By the addition of nitrogen, a region with high crystallinity can be formed in the region of the oxide semiconductor layer in the vicinity of the interface with the gate insulating layer, so that a stable interface state can be obtained.
    Type: Application
    Filed: November 16, 2011
    Publication date: May 31, 2012
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventor: Shunpei YAMAZAKI
  • Patent number: 8188467
    Abstract: In a field effect transistor, a channel layer of the field effect transistor is composed of an amorphous oxide including In, Zn, N and O, an atomic composition ratio of N to N and O (N/(N+O)) in the amorphous oxide is equal to or larger than 0.01 atomic percent and equal to or smaller than 3 atomic percent, and the amorphous oxide does not include Ga, or, in a case where the amorphous oxide includes Ga, the number of Ga atoms contained in the amorphous oxide is smaller than the number of N atoms.
    Type: Grant
    Filed: May 22, 2008
    Date of Patent: May 29, 2012
    Assignee: Canon Kabushiki Kaisha
    Inventors: Naho Itagaki, Tatsuya Iwasaki
  • Publication number: 20120126223
    Abstract: An oxide transistor includes: a channel layer formed of an oxide semiconductor; a source electrode contacting a first end portion of the channel layer; a drain electrode contacting a second end portion of the channel layer; a gate corresponding to the channel layer; and a gate insulating layer disposed between the channel layer and the gate. The oxide semiconductor includes hafnium-indium-zinc-oxide (HfInZnO). An electrical conductivity of a back channel region of the channel layer is lower than an electrical conductivity of a front channel region of the channel layer.
    Type: Application
    Filed: June 9, 2011
    Publication date: May 24, 2012
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Wan-joo MAENG, Myung-kwan RYU, Tae-sang KIM, Joon-seok PARK
  • Publication number: 20120112183
    Abstract: An object is to provide a semiconductor device including an oxynitride semiconductor whose carrier density is controlled. By introducing controlled nitrogen into an oxide semiconductor layer, a transistor in which an oxynitride semiconductor having desired carrier density and on characteristics is used for a channel can be manufactured. Further, with the use of the oxynitride semiconductor, even when a low resistance layer or the like is not provided between an oxynitride semiconductor layer and a source electrode and between the oxynitride semiconductor layer and a drain electrode, favorable contact characteristics can be exhibited.
    Type: Application
    Filed: October 27, 2011
    Publication date: May 10, 2012
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Yuta ENDO, Toshinari SASAKI, Kosei NODA
  • Publication number: 20120112180
    Abstract: The instant disclosure relates to a metal oxide thin film transistor having a threshold voltage modification layer. The thin film transistor includes a gate electrode, a dielectric layer formed on the gate electrode, an active layer formed on the dielectric layer, a source electrode and a drain electrode disposed separately on the active layer, and a threshold voltage modulation layer formed on the active layer in direct contact with the back channel of the transistor. The threshold voltage modulation layer and the active layer have different work functions so that the threshold voltage modulation layer modulates the threshold voltage of devices and improve the performance of the transistor.
    Type: Application
    Filed: December 2, 2010
    Publication date: May 10, 2012
    Applicant: NATIONAL CHIAO TUNG UNIVERSITY
    Inventors: HSIAO-WEN ZAN, CHUANG-CHUANG TSAI, WEI-TSUNG CHEN, HSIU-WEN HSUEH
  • Publication number: 20120112184
    Abstract: A semiconductor device having a novel structure or a method for manufacturing the semiconductor device is provided. For example, the reliability of a transistor which is driven at high voltage or large current is improved. For improvement of the reliability of the transistor, a buffer layer is provided between a drain electrode layer (or a source electrode layer) and an oxide semiconductor layer such that the end portion of the buffer layer is beyond the side surface of the drain electrode layer (or the source electrode layer) when seen in a cross section, whereby the buffer layer can relieve the concentration of electric field. The buffer layer is a single layer or a stacked layer including a plurality of layers, and includes, for example, an In—Ga—Zn—O film containing nitrogen, an In—Sn—O film containing nitrogen, an In—Sn—O film containing SiOx, or the like.
    Type: Application
    Filed: October 31, 2011
    Publication date: May 10, 2012
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei Yamazaki, Yusuke Nonaka, Takatsugu Omata, Tatsuya Honda, Akiharu Miyanaga, Hiroki Ohara
  • Patent number: 8174021
    Abstract: An object is to provide a semiconductor device provided with a thin film transistor having excellent electric characteristics using an oxide semiconductor layer. An In—Sn—O-based oxide semiconductor layer including SiOX is used for a channel formation region. In order to reduce contact resistance between the In—Sn—O-based oxide semiconductor layer including SiOX and a wiring layer formed from a metal material having low electric resistance, a source region or drain region is formed between a source electrode layer or drain electrode layer and the In—Sn—O-based oxide semiconductor layer including SiOX. The source region or drain region and a pixel region are formed using an In—Sn—O-based oxide semiconductor layer which does not include SiOX.
    Type: Grant
    Filed: January 28, 2010
    Date of Patent: May 8, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshiaki Oikawa, Hotaka Maruyama, Hiromichi Godo, Daisuke Kawae, Shunpei Yamazaki
  • Publication number: 20120104386
    Abstract: As a display device has a higher definition, the number of pixels, gate lines, and signal lines are increased. When the number of the gate lines and the signal lines are increased, there occurs a problem that it is difficult to mount an IC chip including a driver circuit for driving the gate and signal lines by bonding or the like, whereby manufacturing cost is increased. A pixel portion and a driver circuit for driving the pixel portion are provided over the same substrate, and at least part of the driver circuit includes a thin film transistor using an oxide semiconductor interposed between gate electrodes provided above and below the oxide semiconductor. The pixel portion and the driver portion are provided over the same substrate, whereby manufacturing cost can be reduced.
    Type: Application
    Filed: January 5, 2012
    Publication date: May 3, 2012
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Hidekazu MIYAIRI, Takeshi OSADA, Kengo AKIMOTO, Shunpei YAMAZAKI
  • Publication number: 20120104385
    Abstract: A semiconductor device includes a first gate electrode; a gate insulating layer covering the first gate electrode; an oxide semiconductor layer that overlaps with the first gate electrode; oxide semiconductor layers having high carrier density covering end portions of the oxide semiconductor layer; a source electrode and a drain electrode in contact with the oxide semiconductor layers having high carrier density; an insulating layer covering the source electrode, the drain electrode, and the oxide semiconductor layer; and a second gate electrode that is in contact with the insulating layer. Each of the oxide semiconductor layers is in contact with part of each of an upper surface, a lower surface, and a side surface of one of the end portions of the oxide semiconductor layer and part of an upper surface of the gate insulating layer.
    Type: Application
    Filed: October 24, 2011
    Publication date: May 3, 2012
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Hiromichi GODO, Satoshi KOBAYASHI
  • Publication number: 20120104384
    Abstract: A thin-film transistor (TFT) includes a gate electrode, an oxide semiconductor pattern, a source electrode, a drain electrode and an etch stopper. The gate electrode is formed on a substrate. The oxide semiconductor pattern is disposed in an area overlapping with the gate electrode. The source electrode is partially disposed on the oxide semiconductor pattern. The drain electrode is spaced apart from the source electrode, faces the source electrode, and is partially disposed on the oxide semiconductor pattern. The etch stopper has first and second end portions. The first end portion is disposed between the oxide semiconductor pattern and the source electrode, and the second end portion is disposed between the oxide semiconductor pattern and the drain electrode. A sum of first and second overlapping length is between about 30% and about 99% of a total length of the etch stopper.
    Type: Application
    Filed: July 28, 2011
    Publication date: May 3, 2012
    Inventors: Young-Joo CHOI, Jae-Won SONG, Xun ZHU, Sang-Wan JIN, Woo-Geun LEE
  • Publication number: 20120097942
    Abstract: It is an object of an embodiment of the present invention to reduce leakage current between a source and a drain in a transistor including an oxide semiconductor. As a first gate film in contact with a gate insulating film, a compound conductor which includes indium and nitrogen and whose band gap is less than 2.8 eV is used. Since this compound conductor has a work function of greater than or equal to 5 eV, preferably greater than or equal to 5.5 eV, the electron concentration in an oxide semiconductor film can be maintained extremely low. As a result, the leakage current between the source and the drain is reduced.
    Type: Application
    Filed: October 17, 2011
    Publication date: April 26, 2012
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Yuki Imoto, Tetsunori Maruyama, Takatsugu Omata, Yusuke Nonaka, Tatsuya Honda, Akiharu Miyanaga
  • Publication number: 20120097943
    Abstract: A TFT including a gate, a gate insulation layer, an oxide semiconductor layer, a translucent layer, a source, and a drain. The gate insulation layer covers the gate. The oxide semiconductor layer is disposed on the gate insulation layer and located above the gate. The oxide semiconductor layer includes an oxide channel layer and two ohmic contact layers. The ohmic contact layers are respectively located beside the oxide channel layer and connected with the oxide channel layer. The translucent layer is located above the oxide channel layer. The source and the drain are disposed on the gate insulation layer and the ohmic contact layers. The source and the drain are electrically insulated from each other.
    Type: Application
    Filed: December 28, 2011
    Publication date: April 26, 2012
    Applicant: AU OPTRONICS CORPORATION
    Inventors: Wu-Hsiung Lin, Ming-Wei Sun
  • Publication number: 20120096928
    Abstract: A method manufactures a sensor device for sensing a gaseous substance and includes a thin film transistor, which includes a source electrode, a drain electrode and a gate electrode; and an element sensitive to the gaseous substance. In particular, the method includes: forming a first metallic layer on a substrate; defining and patterning the first metallic layer for realizing the gate electrode; depositing a dielectric layer above the gate electrode; depositing a second metallic layer above the layer of dielectric material, defining and patterning the second metallic layer for realizing the source electrode and the drain electrode, and forming the sensitive element by filling a channel region of the thin film transistor with an active layer sensitive to the gaseous substance.
    Type: Application
    Filed: October 21, 2011
    Publication date: April 26, 2012
    Applicant: STMICROELECTRONICS S.R.L.
    Inventor: Luigi Giuseppe Occhipinti
  • Publication number: 20120097958
    Abstract: A field emission pixel includes a cathode on which a field emitter emitting electrons is formed, an anode on which a phosphor absorbing electrons from the field emitter is formed, and a thin film transistor (TFT) having a source connected to a current source in response to a scan signal, a gate receiving a data signal, and a drain connected to the field emitter. The field emitter is made of carbon material such as diamond, diamond like carbon, carbon nanotube or carbon nanofiber. The cathode may include multiple field emitters, and the TFT may include multiple transistors having gates to which the same signal is applied, sources to which the same signal is applied, and drains respectively connected to the field emitters. An active layer of the TFT is made of a semiconductor film such as amorphous silicon, micro-crystalline silicon, polycrystalline silicon, wide-band gap material like ZnO, or an organic semiconductor.
    Type: Application
    Filed: September 23, 2011
    Publication date: April 26, 2012
    Applicant: ELECTRONICS AND TELECOMMUNICATION RESEARCH INSTITUTE
    Inventors: Yoon Ho SONG, Dae Jun Kim, Jin Woo Jeong, Jin Ho Lee, Kwang Yong Kang
  • Publication number: 20120091452
    Abstract: The present invention provides an oxide semiconductor capable of achieving a thin film transistor having stable transistor characteristics, a thin film transistor having a channel layer formed of the oxide semiconductor and a production method thereof, and a display device equipped with the thin film transistor. The oxide semiconductor of the present invention is an oxide semiconductor for a thin film transistor. The oxide semiconductor includes indium, gallium, zinc, and oxygen as constituent atoms, and the oxygen content of the oxide semiconductor is 87% to 95% of the stoichiometric condition set as 100%, in terms of atomic units.
    Type: Application
    Filed: March 10, 2010
    Publication date: April 19, 2012
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Yoshifumi Ohta, Go Mori, Hirohiko Nishiki, Yoshimasa Chikama, Tetsuya Aita, Masahiko Suzuki, Okifumi Nakagawa, Michiko Takei, Yoshiyuki Harumoto, Takeshi Hara
  • Patent number: 8158976
    Abstract: Example embodiments relate to thin-film transistors (TFT) and methods for fabricating the same. A thin-film transistor according to example embodiments may include a gate, a gate insulation layer, a channel layer including a first oxide semiconductor layer and a second oxide semiconductor layer, and a source and drain on opposite sides of the channel layer. The first oxide semiconductor layer may have relatively large crystal grains compared to the second oxide semiconductor layer.
    Type: Grant
    Filed: February 26, 2010
    Date of Patent: April 17, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyoung-seok Son, Jang-yeon Kwon, Hyoung-sub Kim, Hoo-jeong Lee, Mi-ran Moon, Kyung Park
  • Patent number: 8158978
    Abstract: An inverter, a logic circuit including the inverter and method of fabricating the same are provided. The inverter includes a load transistor of a depletion mode, and a driving transistor of an enhancement mode, which is connected to the load transistor. The load transistor may have a first oxide layer as a first channel layer. The driving transistor may have a second oxide layer as a second channel layer.
    Type: Grant
    Filed: July 16, 2010
    Date of Patent: April 17, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-wook Kim, Young-soo Park, Jae-chul Park
  • Publication number: 20120074399
    Abstract: Certain example embodiments relate to methods of making oxide thin film transistor arrays (e.g., IGZO, amorphous or polycrystalline ZnO, ZnSnO, InZnO, and/or the like), and devices incorporating the same. Blanket layers of an optional barrier layer, semiconductor, gate insulator, and/or gate metal are disposed on a substrate. These and/or other layers may be deposited on a soda lime or borosilicate substrate via low or room temperature sputtering. These layers may be later patterned and/or further processed in making a TFT array according to certain example embodiments. In certain example embodiments, all or substantially all TFT processing may take place at a low temperature, e.g., at or below 150 degrees C., until a post-annealing activation step, and the post-anneal step may take place at a relatively low temperature (e.g., 200-250 degrees C.).
    Type: Application
    Filed: September 29, 2010
    Publication date: March 29, 2012
    Applicant: Guardian Industries Corp.
    Inventor: Willem Den Boer
  • Patent number: 8143115
    Abstract: A thin film transistor is manufactured by forming a gate electrode on a substrate, forming a first insulating film on the gate electrode, forming an oxide semiconductor layer on the first insulating film with an amorphous oxide, patterning the first insulating film, patterning the oxide semiconductor layer, forming a second insulating film on the oxide semiconductor layer in an oxidative-gas-containing atmosphere, patterning the second insulating film to expose a pair of contact regions, forming an electrode layer on the pair of contact regions, and patterning the electrode layer to for a source electrode and a drain electrode.
    Type: Grant
    Filed: November 29, 2007
    Date of Patent: March 27, 2012
    Assignee: Canon Kabushiki Kaisha
    Inventors: Hideyuki Omura, Ryo Hayashi, Nobuyuki Kaji, Hisato Yabuta
  • Patent number: 8143093
    Abstract: The present invention generally relates to thin film transistors (TFTs) and methods of making TFTs. The active channel of the TFT may comprise one or more metals selected from the group consisting of zinc, gallium, tin, indium, and cadmium. The active channel may also comprise nitrogen and oxygen. To protect the active channel during source-drain electrode patterning, an etch stop layer may be deposited over the active layer. The etch stop layer prevents the active channel from being exposed to the plasma used to define the source and drain electrodes. The etch stop layer and the source and drain electrodes may be used as a mask when wet etching the active material layer that is used for the active channel.
    Type: Grant
    Filed: March 17, 2009
    Date of Patent: March 27, 2012
    Assignee: Applied Materials, Inc.
    Inventor: Yan Ye
  • Patent number: 8138548
    Abstract: A thin film transistor array substrate includes a substrate, a gate layer, a gate insulating layer, a source/drain layer, a patterned protective layer, an oxide semiconductor layer, a resin layer and a pixel electrode. The gate layer is disposed on the substrate. The gate insulating layer is disposed on the gate layer and the substrate. The source/drain layer is disposed on the gate insulating layer. The patterned protective layer is disposed on the source/drain layer and exposes a portion of the source/drain layer. The oxide semiconductor layer is disposed on the patterned protective layer and electrically connected to the source/drain layer. The resin layer is disposed on the oxide semiconductor layer and covers the oxide semiconductor layer. The pixel electrode is disposed on the resin layer and connects to the source/drain layer. The present invention also provides a method for making the thin film transistor array substrate. The thin film transistor array substrate can prevent leakage current.
    Type: Grant
    Filed: July 16, 2010
    Date of Patent: March 20, 2012
    Assignee: E Ink Holdings Inc.
    Inventors: Sung-Hui Huang, Wei-Chou Lan, Ted-Hong Shinn
  • Publication number: 20120061668
    Abstract: As a display device has a higher definition, the number of pixels, gate lines, and signal lines are increased. When the number of the gate lines and the signal lines are increased, a problem of higher manufacturing cost, because it is difficult to mount an IC chip including a driver circuit for driving of the gate and signal lines by bonding or the like. A pixel portion and a driver circuit for driving the pixel portion are provided over the same substrate, and at least part of the driver circuit includes a thin film transistor using an oxide semiconductor interposed between gate electrodes provided above and below the oxide semiconductor. Therefore, when the pixel portion and the driver portion are provided over the same substrate, manufacturing cost can be reduced.
    Type: Application
    Filed: November 22, 2011
    Publication date: March 15, 2012
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Hidekazu MIYAIRI, Takeshi OSADA, Shunpei YAMAZAKI
  • Publication number: 20120061665
    Abstract: A photolithography step and an etching step for forming an island-shaped semiconductor layer is omitted, and a liquid crystal display device is manufactured through the following four photolithography steps: a step for forming a gate electrode (including a wiring or the like formed from the same layer), a step for forming a source electrode and a drain electrode (including a wiring or the like formed from the same layer), a step for forming a contact hole (including removal of an insulating layer or the like in a region other than the contact hole), and a step for forming a pixel electrode (including a wiring or the like formed from the same layer). In the step of forming the contact hole, a groove portion in which the semiconductor layer is removed is formed, so that formation of parasitic channels is prevented.
    Type: Application
    Filed: September 7, 2011
    Publication date: March 15, 2012
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Hiroyuki Miyake, Ryo Arasawa, Koji Kusunoki
  • Publication number: 20120056173
    Abstract: A staggered thin film transistor and a method of forming the staggered thin film transistor are provided. The thin film transistor includes an annealed layer stack including an oxide containing layer, a copper alloy layer deposited on the conductive oxide layer, a copper containing oxide layer, and a copper containing layer.
    Type: Application
    Filed: September 10, 2010
    Publication date: March 8, 2012
    Applicant: APPLIED MATERIALS, INC.
    Inventor: Fabio PIERALISI
  • Patent number: 8129717
    Abstract: It is an object to provide a semiconductor device including a thin film transistor with favorable electric properties and high reliability, and a method for manufacturing the semiconductor device with high productivity. In an inverted staggered (bottom gate) thin film transistor, an oxide semiconductor film containing In, Ga, and Zn is used as a semiconductor layer, and a buffer layer formed using a metal oxide layer is provided between the semiconductor layer and a source and drain electrode layers. The metal oxide layer is intentionally provided as the buffer layer between the semiconductor layer and the source and drain electrode layers, whereby ohmic contact is obtained.
    Type: Grant
    Filed: July 29, 2009
    Date of Patent: March 6, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hidekazu Miyairi, Kengo Akimoto, Kojiro Shiraishi
  • Patent number: 8129718
    Abstract: There is provided an amorphous oxide semiconductor including hydrogen and at least one element of indium (In) and zinc (Zn), the amorphous oxide semiconductor containing one of hydrogen atoms and deuterium atoms of 1×1020 cm?3 or more to 1×1022 cm?3 or less, and a density of bonds between oxygen and hydrogen except bonds between excess oxygen (OEX) and hydrogen in the amorphous oxide semiconductor being 1×1018 cm?3 or less.
    Type: Grant
    Filed: August 3, 2009
    Date of Patent: March 6, 2012
    Assignee: Canon Kabushiki Kaisha
    Inventors: Ryo Hayashi, Hideyuki Omura, Hideya Kumomi, Yuzo Shigesato
  • Patent number: 8125032
    Abstract: A semiconductor process and apparatus includes forming first and second metal gate electrodes (151, 161) over a hybrid substrate (17) by forming the first gate electrode (151) over a first high-k gate dielectric (121) and forming the second gate electrode (161) over at least a second high-k gate dielectric (122) different from the first gate dielectric (121). By forming the first gate electrode (151) over a first SOI substrate (90) formed by depositing (100) silicon and forming the second gate electrode (161) over an epitaxially grown (110) SiGe substrate (70), a high performance CMOS device is obtained which includes high-k metal PMOS gate electrodes (161) having improved hole mobility.
    Type: Grant
    Filed: April 9, 2009
    Date of Patent: February 28, 2012
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Olubunmi O. Adetutu, Mariam G. Sadaka, Ted R. White, Bich-Yen Nguyen
  • Publication number: 20120037906
    Abstract: A thin film transistor array substrate capable of reducing degradation of a device due to degradation of an oxide semiconductor pattern and a method of fabricating the same are provided. The thin film transistor array substrate may include an insulating substrate on which a gate electrode is formed, a gate insulating film formed on the insulating substrate, an oxide semiconductor pattern disposed on the gate insulating film, an anti-etching pattern formed on the oxide semiconductor pattern, and a source electrode and a drain electrode formed on the anti-etching pattern. The oxide semiconductor pattern may include an edge portion positioned between the source electrode and the drain electrode, and the edge portion may include at least one conductive region and at least one non-conductive region.
    Type: Application
    Filed: May 24, 2011
    Publication date: February 16, 2012
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hye-Young RYU, Woo-Geun LEE, Young-Joo CHOI, Kyoung-Jae CHUNG, Jin-Won LEE, Seung-Ha CHOI, Hee-Jun BYEON, Pil-Sang YUN
  • Publication number: 20120032163
    Abstract: The electric characteristics of a semiconductor device including an oxide semiconductor change by irradiation with visible light or ultraviolet light. In view of the above problem, one object is to provide a semiconductor device including an oxide semiconductor film, which has stable electric characteristics and high reliability. Over an oxide insulating layer, a first oxide semiconductor layer is formed to a thickness greater than or equal to 1 nm and less than or equal to 10 nm and crystallized by heat treatment, so that a first crystalline oxide semiconductor layer is formed. A second crystalline oxide semiconductor layer with a greater thickness than the first crystalline oxide semiconductor layer is formed thereover.
    Type: Application
    Filed: July 29, 2011
    Publication date: February 9, 2012
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventor: Shunpei YAMAZAKI
  • Publication number: 20120032165
    Abstract: Provided are an aqueous solution composition for fluorine doped metal oxide semiconductor, a method for manufacturing a fluorine doped metal oxide semiconductor using the same, and a thin film transistor including the same. The aqueous solution composition for fluorine doped metal oxide semiconductor includes: a fluorine compound precursor made of one or two or more selected from the group consisting of a metal compound containing fluorine and an organic material containing fluorine; and an aqueous solution containing water or catalyst. The method for manufacturing a fluorine doped metal oxide semiconductor, includes: preparing an aqueous solution composition for fluorine doped metal oxide semiconductor, coating a substrate with the aqueous solution composition; and performing heat treatment on the coated substrate to form the fluorine doped metal oxide semiconductor.
    Type: Application
    Filed: August 4, 2011
    Publication date: February 9, 2012
    Applicant: KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Byeong-Soo BAE, Jun-Hyuck JEON
  • Publication number: 20120025187
    Abstract: Transistors, methods of manufacturing the transistors, and electronic devices including the transistors. The transistor may include an oxide channel layer having a multi-layer structure. The channel layer may include a first layer and a second layer that are sequentially arranged from a gate insulation layer. The first layer may be a conductor, and the second layer may be a semiconductor having a lower electrical conductivity than that of the first layer. The first layer may become a depletion region according to a gate voltage condition.
    Type: Application
    Filed: March 24, 2011
    Publication date: February 2, 2012
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Kyung-bae Park, Hyun-suk Kim, Myung-kwan Ryu, Sang-yoon Lee, Kwang-hee Lee, Tae-sang Kim, Eok-su Kim, Kyoung-seok Son, Wan-joo Maeng, Joon-seok Park
  • Publication number: 20120025191
    Abstract: A method for manufacturing a semiconductor device, which enables miniaturization and reduction of defect, is provided. It includes forming an oxide semiconductor layer, and source and drain electrodes in contact with the oxide semiconductor layer, over an insulating surface; forming insulating layers over the source electrode and the drain electrode; forming a gate insulating layer over the oxide semiconductor layer, the source and drain electrodes, and the insulating layer; forming a conductive layer over the gate insulating layer; forming an insulating film covering the conductive layer; processing the insulating film so that at least part of a region of the conductive layer, which overlaps with the source electrode or the drain electrode, is exposed; and etching the exposed region of the conductive layer to form a gate electrode overlapping with at least part of the region sandwiched between the source electrode and the drain electrode, in a self-aligned manner.
    Type: Application
    Filed: July 27, 2011
    Publication date: February 2, 2012
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventor: Shunpei Yamazaki
  • Patent number: 8106400
    Abstract: As a display device has a higher definition, the number of pixels, gate lines, and signal lines are increased. When the number of the gate lines and the signal lines are increased, there occurs a problem that it is difficult to mount an IC chip including a driver circuit for driving the gate and signal lines by bonding or the like, whereby manufacturing cost is increased. A pixel portion and a driver circuit for driving the pixel portion are provided over the same substrate, and at least part of the driver circuit includes a thin film transistor using an oxide semiconductor interposed between gate electrodes provided above and below the oxide semiconductor. The pixel portion and the driver portion are provided over the same substrate, whereby manufacturing cost can be reduced.
    Type: Grant
    Filed: October 20, 2009
    Date of Patent: January 31, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hidekazu Miyairi, Takeshi Osada, Kengo Akimoto, Shunpei Yamazaki
  • Publication number: 20120018720
    Abstract: A display substrate includes a gate line extending in a first direction on a base substrate, a data line on the base substrate and extending in a second direction crossing the first direction, a gate insulating layer on the gate line, a thin-film transistor and a pixel electrode. The thin-film transistor includes a gate electrode electrically connected the gate line, an oxide semiconductor pattern, and source and drain electrodes on the oxide semiconductor pattern and spaced apart from each other. The oxide semiconductor pattern includes a first semiconductor pattern including indium oxide and a second semiconductor pattern including indium-free oxide. The pixel electrode is electrically connected the drain electrode.
    Type: Application
    Filed: July 7, 2011
    Publication date: January 26, 2012
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae-Woo PARK, Dong-Hoon LEE, Sung-Haeng CHO, Woo-Geun LEE, Hye-Young RYU, Young-Joo CHOI
  • Patent number: 8101949
    Abstract: Embodiments of the present invention generally include TFTs and methods for their manufacture. The gate dielectric layer in the TFT may affect the threshold voltage of the TFT. By treating the gate dielectric layer prior to depositing the active channel material, the threshold voltage may be improved. One method of treating the gate dielectric involves exposing the gate dielectric layer to N2O gas. Another method of treating the gate dielectric involves exposing the gate dielectric layer to N2O plasma. Silicon oxide, while not practical as a gate dielectric for silicon based TFTs, may also improve the threshold voltage when used in metal oxide TFTs. By treating the gate dielectric and/or using silicon oxide, the threshold voltage of TFTs may be improved.
    Type: Grant
    Filed: June 29, 2009
    Date of Patent: January 24, 2012
    Assignee: Applied Materials, Inc.
    Inventor: Yan Ye
  • Publication number: 20120012836
    Abstract: When a transistor having bottom gate bottom contact structure is manufactured, for example, a conductive layer constituting a source and a drain has a three-layer structure and two-step etching is performed. In the first etching process, an etching method in which the etching rates for at least the second film and the third film are high is employed, and the first etching process is performed until at least the first film is exposed. In the second etching process, an etching method in which the etching rate for the first film is higher than that in the first etching process and the etching rate for a “layer provided below and in contact with the first film” is lower than that in the first etching process is employed. The side wall of the second film is slightly etched when a resist mask is removed after the second etching process.
    Type: Application
    Filed: July 1, 2011
    Publication date: January 19, 2012
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shinya SASAGAWA, Hitoshi NAKAYAMA, Masashi TSUBUKU, Daigo SHIMADA
  • Publication number: 20120012840
    Abstract: In at least some embodiments, a thin-film transistor (TFT) includes a gate electrode and a gate dielectric covering the gate dielectric. The TFT also includes a source electrode and a drain electrode adjacent the gate dielectric. The TFT also includes a bi-layer channel between the source electrode and the drain electrode, the bi-layer channel having a zinc indium oxide (ZIO) layer positioned adjacent the gate dielectric and a zinc tin oxide (ZTO) layer that covers the ZIO layer.
    Type: Application
    Filed: March 31, 2009
    Publication date: January 19, 2012
    Inventors: Vincent Korthuis, Randy Hoffman
  • Publication number: 20120012835
    Abstract: A top gate and bottom gate thin film transistor (TFT) are provided with an associated fabrication method. The TFT is fabricated from a substrate, and an active metal oxide semiconductor (MOS) layer overlying the substrate. Source/drain (S/D) regions are formed in contact with the active MOS layer. A channel region is interposed between the S/D regions. The TFT includes a gate electrode, and a gate dielectric interposed between the channel region and the gate electrode. The active MOS layer may be ZnOx, InOx, GaOx, SnOx, or combinations of the above-mentioned materials. The active MOS layer also includes a primary dopant such as H, K, Sc, La, Mo, Bi, Ce, Pr, Nd, Sm, Dy, or combinations of the above-mentioned dopants. The active MOS layer may also include a secondary dopant.
    Type: Application
    Filed: July 14, 2010
    Publication date: January 19, 2012
    Inventors: Gregory Herman, Jer-shen Maa, Kanan Puntambekar, Apostolos T. Voutsas
  • Patent number: 8093589
    Abstract: In a thin film transistor (1), a gate insulating layer (4) is formed on a gate electrode (3) formed on an insulating substrate (2). Formed on the gate insulating layer (4) is a semiconductor layer (5). Formed on the semiconductor layer (5) are a source electrode (6) and a drain electrode (7). A protective layer (8) covers them, so that the semiconductor layer (5) is blocked from an atmosphere. The semiconductor layer (5) (active layer) is made of, e.g., a semiconductor containing polycrystalline ZnO to which, e.g., a group V element is added. This allows practical use of a semiconductor device which has an active layer made of zinc oxide and which includes an protective layer for blocking the active layer from an atmosphere.
    Type: Grant
    Filed: June 14, 2004
    Date of Patent: January 10, 2012
    Assignees: Sharp Kabushiki Kaisha
    Inventors: Toshinori Sugihara, Hideo Ohno, Masashi Kawasaki
  • Publication number: 20120001170
    Abstract: An object is to provide a semiconductor device including an oxide semiconductor, which has stable electrical characteristics and improved reliability. In a transistor including an oxide semiconductor film, insulating films each including a material containing a Group 13 element and oxygen are formed in contact with the oxide semiconductor film, whereby the interfaces with the oxide semiconductor film can be kept in a favorable state. Further, the insulating films each include a region where the proportion of oxygen is higher than that in the stoichiometric composition, so that oxygen is supplied to the oxide semiconductor film; thus, oxygen defects in the oxide semiconductor film can be reduced. Furthermore, the insulating films in contact with the oxide semiconductor film each have a stacked structure so that films each containing aluminum are provided over and under the oxide semiconductor film, whereby entry of water into the oxide semiconductor film can be prevented.
    Type: Application
    Filed: June 28, 2011
    Publication date: January 5, 2012
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventor: Shunpei YAMAZAKI
  • Publication number: 20120001167
    Abstract: A thin film transistor allowed to suppress a failure caused by an interlayer insulating film and improve reliability of a self-alignment structure, and a display device including this thin film transistor are provided. The thin film transistor includes: a gate electrode; an oxide semiconductor film having a channel region facing the gate electrode, and having a source region on one side of the channel region, and a drain region on the other side of the channel region; an interlayer insulating film provided in contact with the oxide semiconductor film as well as having a connection hole, and including an organic resin film; and a source electrode and a drain electrode connected to the source region and the drain region, respectively, via the connection hole.
    Type: Application
    Filed: June 2, 2011
    Publication date: January 5, 2012
    Applicant: SONY CORPORATION
    Inventor: Narihiro Morosawa
  • Publication number: 20120001168
    Abstract: In a transistor including an oxide semiconductor, hydrogen in the oxide semiconductor leads to degradation of electric characteristics of the transistor. Thus, an object is to provide a semiconductor device having good electrical characteristics. An insulating layer in contact with an oxide semiconductor layer where a channel region is formed is formed by a plasma CVD method using a silicon halide. The insulating layer thus formed has a hydrogen concentration less than 6×1020 atoms/cm3 and a halogen concentration greater than or equal to 1×1020 atoms/cm3; accordingly, hydrogen diffusion into the oxide semiconductor layer can be prevented and hydrogen in the oxide semiconductor layer is inactivated or released from the oxide semiconductor layer by the halogen, whereby a semiconductor device having good electrical characteristics can be provided.
    Type: Application
    Filed: June 21, 2011
    Publication date: January 5, 2012
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Mitsuhiro ICHIJO, Toshiya ENDO, Kunihiko SUZUKI, Yasuhiko TAKEMURA
  • Publication number: 20110315983
    Abstract: A method of manufacturing an IGZO active layer includes depositing ions including In, Ga, and Zn from a first target, and depositing ions including In from a second target having a different atomic composition from the first target. The deposition of ions from the second target may be controlled to adjust an atomic % of In in the IGZO layer to be about 45 atomic % to about 80 atomic %.
    Type: Application
    Filed: September 12, 2011
    Publication date: December 29, 2011
    Applicant: SAMSUNG MOBILE DISPLAY CO., LTD.
    Inventors: Jong-han JEONG, Jae-kyeong JEONG, Jin-seong PARK, Yeon-gon MO, Hui-won YANG, Min-kyu KIM, Tae-kyung AHN, Hyun-soo SHIN, Hun jung LEE
  • Publication number: 20110315980
    Abstract: Provided are a Thin Film Transistor (TFT) and a method of manufacturing the same. The TFT includes a gate electrode; a source electrode and a drain electrode spaced from the gate electrode in a vertical direction and spaced from each other in a horizontal direction; a gate insulation layer disposed between the gate electrode and the source and drain electrodes; and an active layer disposed between the gate insulation layer and the source and drain electrodes. The active layer is formed of a conductive oxide layer and comprises at least two layers having different conductivities according to an impurity doped into the conductive oxide layer.
    Type: Application
    Filed: June 21, 2011
    Publication date: December 29, 2011
    Inventor: Jae Ho Kim
  • Publication number: 20110309355
    Abstract: An object is to provide a semiconductor device having good electrical characteristics. A gate insulating layer having a hydrogen concentration less than 6×1020 atoms/cm3 and a fluorine concentration greater than or equal to 1×1020 atoms/cm3 is used as a gate insulating layer in contact with an oxide semiconductor layer forming a channel region, so that the amount of hydrogen released from the gate insulating layer can be reduced and diffusion of hydrogen into the oxide semiconductor layer can be prevented. Further, hydrogen present in the oxide semiconductor layer can be eliminated with the use of fluorine; thus, the hydrogen content in the oxide semiconductor layer can be reduced. Consequently, the semiconductor device having good electrical characteristics can be provided.
    Type: Application
    Filed: June 10, 2011
    Publication date: December 22, 2011
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Mitsuhiro ICHIJO, Toshiya ENDO, Kunihiko SUZUKI
  • Publication number: 20110309353
    Abstract: A semiconductor device includes, in a first region over a semiconductor substrate, a first insulating layer, a first wiring, a second insulating layer, a third insulating layer, and a via and a second wiring embedded in the second insulating layer and the third insulating layer through a barrier metal, and includes, in a second region, the first insulating layer, a gate electrode, the second insulating layer, a semiconductor layer located, the third insulating layer, and a first electric conductor and a second electric conductor embedded in the third insulating layer so as to sandwich the gate electrode in a position overlapped with the semiconductor layer in a plan view through a barrier metal and coupled to the semiconductor layer through the barrier metal.
    Type: Application
    Filed: May 27, 2011
    Publication date: December 22, 2011
    Applicant: Renesas Electronics Corporation
    Inventors: Kishou Kaneko, Naoya Inoue, Yoshihiro Hayashi