Comprising Group Iii-v Or Ii-vi Compound, Or Of Se, Te, Or Oxide Semiconductor (epo) Patents (Class 257/E29.296)
  • Patent number: 8389996
    Abstract: A method for forming a SnO-containing semiconductor film includes a first step of forming a SnO-containing film; a second step of forming an insulator film composed of an oxide or a nitride on the SnO-containing film to provide a laminated film including the SnO-containing film and the insulator film; and a third step of subjecting the laminated film to a heat treatment.
    Type: Grant
    Filed: March 1, 2010
    Date of Patent: March 5, 2013
    Assignee: Canon Kabushiki Kaisha
    Inventors: Hisato Yabuta, Nobuyuki Kaji, Ryo Hayashi
  • Publication number: 20130048977
    Abstract: To provide a semiconductor device including an oxide semiconductor, which has stable electric characteristics and has high reliability. To provide a method for manufacturing the semiconductor device. The semiconductor device includes a gate electrode, a gate insulating film formed over the gate electrode, an oxide semiconductor film formed over the gate insulating film, a source electrode and a drain electrode formed over the oxide semiconductor film, and a protective film. The protective film includes a metal oxide film, and the metal oxide film has a film density of higher than or equal to 3.2 g/cm3.
    Type: Application
    Filed: August 23, 2012
    Publication date: February 28, 2013
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Masahiro WATANABE, Mitsuo MASHIYAMA, Takuya HANDA, Kenichi OKAZAKI
  • Publication number: 20130052583
    Abstract: Devices having a thin film or laminate structure comprising hafnium and/or zirconium oxy hydroxy compounds, and methods for making such devices, are disclosed. The hafnium and zirconium compounds can be doped, typically with other metals, such as lanthanum. Examples of electronic devices or components that can be made include, without limitation, insulators, transistors and capacitors. A method for patterning a device using the materials as positive or negative resists or as functional device components also is described. For example, a master plate for imprint lithography can be made. An embodiment of a method for making a device having a corrosion barrier also is described. Embodiments of an optical device comprising an optical substrate and coating also are described. Embodiments of a physical ruler also are disclosed, such as for accurately measuring dimensions using an electron microscope.
    Type: Application
    Filed: October 26, 2012
    Publication date: February 28, 2013
    Applicant: State of Oregon acting by and through the State Board of Higher Education on behalf of Oregon
    Inventor: State of Oregon acting by and through the State
  • Patent number: 8384079
    Abstract: An object is to provide a semiconductor device having a structure in which parasitic capacitance between wirings can be efficiently reduced. In a bottom gate thin film transistor using an oxide semiconductor layer, an oxide insulating layer used as a channel protection layer is formed above and in contact with part of the oxide semiconductor layer overlapping with a gate electrode layer, and at the same time an oxide insulating layer covering a peripheral portion (including a side surface) of the stacked oxide semiconductor layer is formed. Further, a source electrode layer and a drain electrode layer are formed in a manner such that they do not overlap with the channel protection layer. Thus, a structure in which an insulating layer over the source electrode layer and the drain electrode layer is in contact with the oxide semiconductor layer is provided.
    Type: Grant
    Filed: July 29, 2010
    Date of Patent: February 26, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Miyuki Hosoba, Junichiro Sakata, Hideaki Kuwabara
  • Publication number: 20130043466
    Abstract: A semiconductor device including an oxide semiconductor and including a more excellent gate insulating film is provided. A highly reliable and electrically stable semiconductor device having a small number of changes in the film structure, the process conditions, the manufacturing apparatus, or the like from a mass production technology that has been put into practical use is provided. A method for manufacturing the semiconductor device is provided. The semiconductor device includes a gate electrode, a gate insulating film formed over the gate electrode, and an oxide semiconductor film formed over the gate insulating film. The gate insulating film includes a silicon nitride oxide film, a silicon oxynitride film formed over the silicon nitride oxide film, and a metal oxide film formed over the silicon oxynitride film. The oxide semiconductor film is formed over and in contact with the metal oxide film.
    Type: Application
    Filed: August 13, 2012
    Publication date: February 21, 2013
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Masafumi NOMURA, Kenichi OKAZAKI, Toshiyuki MIYAMOTO, Takashi HAMOCHI, Shunpei YAMAZAKI
  • Patent number: 8378342
    Abstract: Provided are an oxide semiconductor and an oxide thin film transistor including the oxide semiconductor. The oxide semiconductor may be formed of an indium (In)-zinc (Zn) oxide in which hafnium (Hf) is contained, wherein In, Zn, and Hf are contained in predetermined or given composition ratios.
    Type: Grant
    Filed: March 23, 2010
    Date of Patent: February 19, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tae-sang Kim, Sang-yoon Lee, Jang-yeon Kwon, Kyoung-seok Son, Ji-sim Jung, Kwang-hee Lee
  • Patent number: 8378343
    Abstract: A semiconductor device is provided in which a pixel portion and a driver circuit each including a thin film transistor are provided over one substrate; the thin film transistor in the pixel portion includes a gate electrode layer, a gate insulating layer, an oxide semiconductor layer having an end region with a small thickness, an oxide insulating layer in contact with part of the oxide semiconductor layer, source and drain electrode layers, and a pixel electrode layer; the thin film transistor in the pixel portion has a light-transmitting property; and source and drain electrode layers of the thin film transistor in the driver circuit portion are formed using a conductive material having lower resistance than a material of the source and drain electrode layer in the pixel portion.
    Type: Grant
    Filed: July 13, 2010
    Date of Patent: February 19, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Junichiro Sakata, Hiroyuki Miyake, Hideaki Kuwabara, Mari Terashima
  • Patent number: 8377742
    Abstract: In a manufacturing method for thin film transistors, the following procedure is taken: a sacrifice layer comprised of a metal oxide semiconductor is formed over a conductive layer comprised of a metal oxide semiconductor; a metal film is formed over the sacrifice layer; the metal film is processed by dry etching; and the portion of the sacrifice layer exposed by this dry etching is subjected to wet etching.
    Type: Grant
    Filed: July 27, 2010
    Date of Patent: February 19, 2013
    Assignee: Hitachi, Ltd.
    Inventors: Tetsufumi Kawamura, Hiroyuki Uchiyama, Hironori Wakana, Mutsuko Hatano
  • Publication number: 20130037797
    Abstract: There is such an issue with a TFT using an oxide semiconductor film that oxygen deficit is generated in a surface region of the oxide semiconductor film after performing plasma etching of a source-drain electrode, and the off-current becomes increased. Disclosed is the TFT which includes: a gate electrode on an insulating substrate as a substrate; a gate insulating film on the gate electrode; an oxide semiconductor film on the gate insulating film; and a source/drain electrode on the oxide semiconductor film. It is the characteristic of the TFT that a surface layer containing at least either fluorine or chlorine exists in a part of the oxide semiconductor film where the source/drain electrode is not superimposed.
    Type: Application
    Filed: August 10, 2012
    Publication date: February 14, 2013
    Applicant: NLT TECHNOLOGIES, LTD.
    Inventor: Kazushige TAKECHI
  • Publication number: 20130037798
    Abstract: A thin-film transistor with a fluorinated channel and fluorinated source and drain regions and methods of fabrication are provided. The thin-film transistor includes: a substrate; a semiconductor active layer of fluorine-doped metal-oxide formed on the substrate; fluorine-doped source and drain regions disposed adjacent to the semiconductor active layer; a gate electrode disposed over the semiconductor active layer, configured to induce a continuous conduction channel between the source and drain regions; and a gate dielectric material separating the gate electrode and the channel.
    Type: Application
    Filed: August 10, 2012
    Publication date: February 14, 2013
    Applicant: THE HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY
    Inventors: Man WONG, Hoi Sing KWOK, Zhi YE
  • Publication number: 20130037793
    Abstract: This disclosure provides systems, methods and apparatus for fabricating thin film transistor devices. In one aspect, a substrate having a source area, a drain area, and a channel area is provided. The substrate also includes an oxide semiconductor layer, a first dielectric layer overlying the channel area of the substrate, and a first metal layer on the dielectric layer. Hydrogen ions are implanted with a plasma-immersion ion implantation process in the oxide semiconductor layer overlying the source area and the drain area of the substrate. The hydrogen ion implantation forms a doped n-type oxide semiconductor in the oxide semiconductor layer overlying the source area and the drain area of the substrate.
    Type: Application
    Filed: August 11, 2011
    Publication date: February 14, 2013
    Applicant: QUALCOMM MEMS TECHNOLOGIES, INC.
    Inventors: Yaoling PAN, Cheonhong KIM, Tallis Young CHANG
  • Patent number: 8372485
    Abstract: A gallium ink is provided, comprising, as initial components: a gallium component comprising gallium; a stabilizing component; an additive; and, a liquid carrier; wherein the gallium ink is a stable dispersion. Also provided are methods of preparing the gallium ink and for using the gallium ink in the preparation of semiconductor films (e.g., in the deposition of a CIGS layer for use in photovoltaic devices).
    Type: Grant
    Filed: February 18, 2011
    Date of Patent: February 12, 2013
    Assignee: Rohm and Haas Electronic Materials LLC
    Inventors: David Mosley, David Thorsen
  • Publication number: 20130032796
    Abstract: A method of fabricating MOTFTs on transparent substrates by positioning opaque gate metal on the substrate front surface and depositing gate dielectric material overlying the gate metal and a surrounding area and metal oxide semiconductor material on the dielectric material. Depositing selectively removable etch stop material on the semiconductor material and photoresist on the etch stop material to define an isolation area in the semiconductor material. Removing uncovered portions of the etch stop. Exposing the photoresist from the substrate rear surface using the gate metal as a mask and removing exposed portions leaving the etch stop material overlying the gate metal covered. Etching the semiconductor material to isolate the TFT. Selectively etching the etch stop layer to leave a portion overlying the gate metal defining a channel area. Depositing and patterning conductive material to form source and drain areas on opposed sides of the channel area.
    Type: Application
    Filed: August 2, 2012
    Publication date: February 7, 2013
    Inventors: Chan-Long Shieh, Gang Yu, Fatt Foong
  • Publication number: 20130032797
    Abstract: The present invention achieves a formation of a metal oxide film of a thin film transistor with a simplified process. The present invention is concerned with a method for manufacturing a field-effect transistor comprising a gate electrode, a source electrode, a drain electrode, a channel layer and a gate insulating layer wherein the channel layer is formed by using a metal salt-containing composition comprising a metal salt, a polyvalent carboxylic acid having a cis-form structure of —C(COOH)?C(COOH)—, an organic solvent and a water wherein a molar ratio of the polyvalent carboxylic acid to the metal salt is in the range of 0.5 to 4.0.
    Type: Application
    Filed: December 19, 2011
    Publication date: February 7, 2013
    Inventors: Koichi Hirano, Shingo Komatsu, Yasuteru Saito, Naoki Ike
  • Patent number: 8368067
    Abstract: A phenomenon of change of a contact resistance between an oxide semiconductor and a metal depending on an oxygen content ratio in introduced gas upon depositing an oxide semiconductor film made of indium gallium zinc oxide, zinc tin oxide, or others in an oxide semiconductor thin-film transistor. A contact layer is formed with an oxygen content ratio of 10% or higher in a region from a surface, where the metal and the oxide semiconductor are contacted, down to at least 3 nm deep in depth direction, and a region to be a main channel layer is further formed with an oxygen content ratio of 10% or lower, so that a multilayered structure is formed, and both of ohmic characteristics to the electrode metal and reliability such as the suppression of threshold potential shift are achieved.
    Type: Grant
    Filed: December 8, 2009
    Date of Patent: February 5, 2013
    Assignee: Hitachi, Ltd.
    Inventors: Hiroyuki Uchiyama, Tetsufumi Kawamura, Hironori Wakana
  • Patent number: 8357963
    Abstract: A semiconductor device includes a material with which off-state current of a transistor can be sufficiently small; for example, an oxide semiconductor material is used. Further, transistors of memory cells of the semiconductor device, which include an oxide semiconductor material, are connected in series. Further, the same wiring (the j-th word line (j is a natural number greater than or equal to 2 and less than or equal to m)) is used as a wiring electrically connected to one of terminals of a capacitor of the j-th memory cell and a wiring electrically connected to a gate terminal of a transistor, in which a channel is formed in an oxide semiconductor layer, of the (j?1)-th memory cell. Therefore, the number of wirings per memory cell and the area occupied by one memory cell are reduced.
    Type: Grant
    Filed: July 19, 2011
    Date of Patent: January 22, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kiyoshi Kato, Takanori Matsuzaki
  • Publication number: 20130015438
    Abstract: One embodiment of the present invention is to achieve high mobility in a device using an oxide semiconductor and provide a highly reliable display device. An oxide semiconductor layer including a crystal region in which c-axis is aligned in a direction substantially perpendicular to a surface is formed and an oxide insulating layer is formed over and in contact with the oxide semiconductor layer. Oxygen is supplied to the oxide semiconductor layer by third heat treatment. A nitride insulating layer containing hydrogen is formed over the oxide insulating layer and fourth heat treatment is performed, so that hydrogen is supplied at least to an interface between the oxide semiconductor layer and the oxide insulating layer.
    Type: Application
    Filed: September 14, 2012
    Publication date: January 17, 2013
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei YAMAZAKI
  • Patent number: 8354670
    Abstract: Provided are a transistor, a method of manufacturing the transistor, and an electronic device including the transistor. The transistor may include a gate insulator of which at least one surface is treated with plasma. The surface of the gate insulator may be an interface that contacts a channel layer. The interface may be treated with plasma by using a fluorine (F)-containing gas, and thus may include fluorine (F). The interface treated with plasma may suppress the characteristic variations of the transistor due to light.
    Type: Grant
    Filed: June 14, 2010
    Date of Patent: January 15, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-wook Kim, Sun-il Kim, Chang-jung Kim, Jae-chul Park
  • Publication number: 20130009149
    Abstract: An object of an embodiment of the present invention is to provide a semiconductor device which includes a transistor including an oxide semiconductor with high field-effect mobility, a small variation in threshold voltage, and high reliability. The semiconductor device includes a transistor which includes an insulating substrate from which oxygen is released by heat treatment and an oxide semiconductor film over the insulating substrate. A channel is formed in the oxide semiconductor film. The insulating substrate from which oxygen is released by heat treatment can be manufactured by implanting oxygen ions into at least a region of an insulating substrate on the side provided with the oxide semiconductor film.
    Type: Application
    Filed: July 2, 2012
    Publication date: January 10, 2013
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Yuta ENDO, Junichi KOEZUKA, Yuichi SATO
  • Patent number: 8350261
    Abstract: The object is to suppress deterioration in electrical characteristics in a semiconductor device comprising a transistor including an oxide semiconductor layer. In a transistor in which a channel layer is formed using an oxide semiconductor, a p-type silicon layer is provided in contact with a surface of the oxide semiconductor layer. Further, the p-type silicon layer is provided in contact with at least a region of the oxide semiconductor layer, in which a channel is formed, and a source electrode layer and a drain electrode layer are provided in contact with regions of the oxide semiconductor layer, over which the p-type silicon layer is not provided.
    Type: Grant
    Filed: February 4, 2010
    Date of Patent: January 8, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Junichiro Sakata, Hiromichi Godo, Takashi Shimazu
  • Publication number: 20130001573
    Abstract: A thin film transistor including a gate electrode, a semiconductor layer, a gate insulating layer, a source electrode, a drain electrode and a graphene pattern. The semiconductor layer overlaps with the gate electrode. The gate insulating layer is disposed between the gate electrode and the semiconductor layer. The source electrode overlaps with the semiconductor layer. The drain electrode overlaps with the semiconductor layer. The drain electrode is spaced apart from the source electrode. The graphene pattern is disposed between the semiconductor layer and at least one of the source electrode and the drain electrode.
    Type: Application
    Filed: March 12, 2012
    Publication date: January 3, 2013
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yong-Su LEE, Yoon-Ho KHANG, Se-Hwan YU, Su-Hyoung KANG
  • Patent number: 8344387
    Abstract: An object is, in a thin film transistor in which an oxide semiconductor is used as an active layer, to prevent change in composition, film quality, an interface, or the like of an oxide semiconductor region serving as an active layer, and to stabilize electrical characteristics of the thin film transistor. In a thin film transistor in which a first oxide semiconductor region is used as an active layer, a second oxide semiconductor region having lower electrical conductivity than the first oxide semiconductor region is formed between the first oxide semiconductor region and a protective insulating layer for the thin film transistor, whereby the second oxide semiconductor region serves as a protective layer for the first oxide semiconductor region; thus, change in composition or deterioration in film quality of the first oxide semiconductor region can be prevented, and electrical characteristics of the thin film transistor can be stabilized.
    Type: Grant
    Filed: November 24, 2009
    Date of Patent: January 1, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kengo Akimoto, Toshinari Sasaki, Hideaki Kuwabara
  • Patent number: 8343800
    Abstract: The invention provides a thin film transistor comprising an active layer, the active layer comprising an IGZO-based oxide material, the IGZO-based oxide material being represented by a composition formula of In2-xGaxZnO4-?, where 0.75<x<1.10 and 0<??1.29161×exp(?x/0.11802)+0.00153 and being formed from a single phase of IGZO having a crystal structure of YbFe2O4, and a method of producing the thin film transistor.
    Type: Grant
    Filed: June 15, 2010
    Date of Patent: January 1, 2013
    Assignee: FUJIFILM Corporation
    Inventors: Kenichi Umeda, Masayuki Suzuki, Atsushi Tanaka, Yuki Nara
  • Patent number: 8344373
    Abstract: To achieve, in an oxide semiconductor thin layer transistor, both the stability of threshold voltage against electric stress and suppression of variation in the threshold voltage in a transfer characteristic. A thin film transistor includes an oxide semiconductor layer and a gate insulating layer disposed so as to be in contact with the oxide semiconductor layer, wherein the oxide semiconductor layer contains hydrogen atoms and includes at least two regions that function as active layers of the oxide semiconductor and have different average hydrogen concentrations in the layer thickness direction; and when the regions functioning as the active layers of the oxide semiconductor are sequentially defined as, from the side of the gate insulating layer, a first region and a second region, the average hydrogen concentration of the first region is lower than the average hydrogen concentration of the second region.
    Type: Grant
    Filed: September 27, 2010
    Date of Patent: January 1, 2013
    Assignee: Canon Kabushiki Kaisha
    Inventors: Ayumu Sato, Hideya Kumomi, Ryo Hayashi, Tomohiro Watanabe
  • Publication number: 20120326149
    Abstract: In transistor structures such as thin film transistors (TFTs) in an array of cells, a layer of semiconducting oxide material that includes a channel is protected by a protective layer that includes low-temperature encapsulant material. The semiconducting oxide material can be a transition metal oxide material such as zinc oxide, and can be in an active layered substructure that also includes channel end electrodes. The low-temperature encapsulant can, for example, be an organic polymer such as poly(methyl methacrylate) or parylene, deposited on an exposed region of the oxide layer such as by spinning, spincasting, evaporation, or vacuum deposition or an inorganic polymer deposited such as by spinning or liquid deposition. The protective layer can include a lower sublayer of low-temperature encapsulant on the exposed region and an upper sublayer of inorganic material on the lower sublayer. For roll-to-roll processing, a mechanically flexible, low-temperature substrate can be used.
    Type: Application
    Filed: September 4, 2012
    Publication date: December 27, 2012
    Applicant: PALO ALTO RESEARCH CENTER INCORPORATED
    Inventors: Tse Nga Ng, Michael L. Chabinyc
  • Patent number: 8338827
    Abstract: In a thin film transistor which uses an oxide semiconductor, buffer layers containing indium, gallium, zinc, oxygen, and nitrogen are provided between the oxide semiconductor layer and the source and drain electrode layers.
    Type: Grant
    Filed: November 4, 2009
    Date of Patent: December 25, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Junichiro Sakata, Tetsunori Maruyama, Yuki Imoto, Yuji Asano, Junichi Koezuka
  • Patent number: 8338226
    Abstract: An object is to provide a thin film transistor including an oxide semiconductor layer, in which the contact resistance between the oxide semiconductor layer and source and drain electrode layers is reduced and whose electric characteristics are stabilized. Another object is to provide a method for manufacturing the thin film transistor. The thin film transistor including an oxide semiconductor layer is formed in such a manner that buffer layers whose conductivity is higher than that of the oxide semiconductor layer are formed and the oxide semiconductor layer and the source and drain electrode layers are electrically connected to each other through the buffer layers. In addition, the buffer layers whose conductivity is higher than that of the oxide semiconductor layer are subjected to reverse sputtering treatment and heat treatment in a nitrogen atmosphere.
    Type: Grant
    Filed: March 29, 2010
    Date of Patent: December 25, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yuji Asano, Junichi Koezuka
  • Publication number: 20120319113
    Abstract: At least part of the oxide semiconductor layer which serves as the channel formation region is thinned by etching and the thickness of the channel formation region is adjusted by the etching. Further, a dopant containing phosphorus (P) or boron (B) is introduced into a thick region of the oxide semiconductor layer to form a source region and a drain region in the oxide semiconductor layer, so that the contact resistance between the source and drain regions and the channel formation region which are connected to each other is reduced.
    Type: Application
    Filed: May 31, 2012
    Publication date: December 20, 2012
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventor: Shunpei YAMAZAKI
  • Publication number: 20120319101
    Abstract: A first insulating film in contact with an oxide semiconductor film and a second insulating film are stacked in this order over an electrode film of a transistor including the oxide semiconductor film, an etching mask is formed over the second insulating film, an opening portion exposing the electrode film is formed by etching a portion of the first insulating film and a portion of the second insulating film, the opening portion exposing the electrode film is exposed to argon plasma, the etching mask is removed, and a conductive film is formed in the opening portion exposing the electrode film. The first insulating film is an insulating film whose oxygen is partly released by heating. The second insulating film is less easily etched than the first insulating film and has a lower gas-permeability than the first insulating film.
    Type: Application
    Filed: May 31, 2012
    Publication date: December 20, 2012
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shinya SASAGAWA, Hiroshi FUJIKI, Yoshinori IEDA
  • Publication number: 20120319105
    Abstract: Methods of forming transparent zinc-tin oxide structures are described. Devices that include transparent zinc-tin oxide structures as at least one of a channel layer in a transistor or a transparent film disposed over an electrical device that is at a substrate.
    Type: Application
    Filed: August 27, 2012
    Publication date: December 20, 2012
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Publication number: 20120319102
    Abstract: An object is to provide a structure of a transistor which has a channel formation region formed using an oxide semiconductor and a positive threshold voltage value, which enables a so-called normally-on switching element. The transistor includes an oxide semiconductor stack in which at least a first oxide semiconductor layer and a second oxide semiconductor layer with different energy gaps are stacked and a region containing oxygen in excess of its stoichiometric composition ratio is provided.
    Type: Application
    Filed: June 5, 2012
    Publication date: December 20, 2012
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei YAMAZAKI, Tatsuya HONDA
  • Publication number: 20120319106
    Abstract: An object is to manufacture and provide a highly reliable semiconductor device including a thin film transistor with stable electric characteristics. In a method for manufacturing a semiconductor device including a thin film transistor in which a semiconductor layer including a channel formation region serves as an oxide semiconductor film, heat treatment for reducing impurities such as moisture (heat treatment for dehydration or dehydrogenation) is performed after an oxide insulating film serving as a protective film is formed in contact with an oxide semiconductor layer. Then, the impurities such as moisture, which exist not only in a source electrode layer, in a drain electrode layer, in a gate insulating layer, and in the oxide semiconductor layer but also at interfaces between the oxide semiconductor film and upper and lower films which are in contact with the oxide semiconductor layer, are reduced.
    Type: Application
    Filed: August 28, 2012
    Publication date: December 20, 2012
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei YAMAZAKI, Hiroki OHARA, Junichiro SAKATA, Toshinari SASAKI, Miyuki HOSOBA
  • Publication number: 20120313092
    Abstract: A method of forming ohmic source/drain contacts in a metal oxide semiconductor thin film transistor includes providing a gate, a gate dielectric, a high carrier concentration metal oxide semiconductor active layer with a band gap and spaced apart source/drain metal contacts in a thin film transistor configuration. The spaced apart source/drain metal contacts define a channel region in the active layer. An oxidizing ambient is provided adjacent the channel region and the gate and the channel region are heated in the oxidizing ambient to reduce the carrier concentration in the channel area. Alternatively or in addition each of the source/drain contacts includes a very thin layer of low work function metal positioned on the metal oxide semiconductor active layer and a barrier layer of high work function metal is positioned on the low work function metal.
    Type: Application
    Filed: June 8, 2011
    Publication date: December 13, 2012
    Inventors: Chan-Long Shieh, Gang Yu, Fatt Foong
  • Publication number: 20120313055
    Abstract: By using a coating method, which is a simple method of manufacturing a transparent conductive film at low cost, a transparent conductive film formed with heating at a low temperature, in particular, lower than 300° C. with both of excellent transparency and conductivity and also with excellent film strength and a method of manufacturing this transparent conductive film are provided.
    Type: Application
    Filed: February 15, 2011
    Publication date: December 13, 2012
    Applicant: SUMITOMO METAL MINING CO.LTD.
    Inventors: Masaya Yukinobu, Takahito Nagano, Yoshihiro Otsuka
  • Patent number: 8330155
    Abstract: Semiconductor devices include a gate electrode, a gate insulation layer, a first channel layer pattern, a second channel layer pattern and first and second metallic patterns. The gate electrode is on a substrate. The gate insulation layer is on the gate electrode. The first channel layer pattern is on the gate insulation layer, and has a first conductivity level. The second channel layer pattern is on the first channel layer pattern, and has a second conductivity level that is lower than the first conductivity level. The first and second metallic patterns are on the gate insulation layer and contact respective sidewalls of the first and second channel layer patterns.
    Type: Grant
    Filed: October 29, 2009
    Date of Patent: December 11, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Hun Jeon, Moon-Sook Lee
  • Publication number: 20120298987
    Abstract: An offset transistor and a non-offset transistor each including an oxide semiconductor are formed over one substrate. An oxide semiconductor layer, a gate insulator, and first layer wirings which serve as gate wirings are formed. After that, the offset transistor is covered with a resist and impurities are mixed into the oxide semiconductor layer, so that an n-type oxide semiconductor region is formed. Then, second layer wirings are formed. Through the above steps, the offset transistor and the non-offset transistor (e.g., aligned transistor) can be formed.
    Type: Application
    Filed: May 23, 2012
    Publication date: November 29, 2012
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventor: Junichiro SAKATA
  • Publication number: 20120299003
    Abstract: An object is to obtain a semiconductor device having a high sensitivity in detecting signals and a wide dynamic range, using a thin film transistor in which an oxide semiconductor layer is used. An analog circuit is formed with the use of a thin film transistor including an oxide semiconductor which has a function as a channel formation layer, has a hydrogen concentration of 5×1019 atoms/cm3 or lower, and substantially functions as an insulator in the state where no electric field is generated. Thus, a semiconductor device having a high sensitivity in detecting signals and a wide dynamic range can be obtained.
    Type: Application
    Filed: August 7, 2012
    Publication date: November 29, 2012
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei YAMAZAKI, Jun KOYAMA, Atsushi HIROSE, Masashi TSUBUKU, Kosei NODA
  • Publication number: 20120300150
    Abstract: A protective circuit includes a non-linear element which includes a gate electrode, a gate insulating layer covering the gate electrode, a first oxide semiconductor layer overlapping with the gate electrode over the gate insulating layer, and a first wiring layer and a second wiring layer whose end portions overlap with the gate electrode over the first oxide semiconductor layer and in which a conductive layer and a second oxide semiconductor layer are stacked. Over the gate insulating layer, oxide semiconductor layers with different properties are bonded to each other, whereby stable operation can be performed as compared with Schottky junction. Thus, the junction leakage can be reduced and the characteristics of the non-linear element can be improved.
    Type: Application
    Filed: August 6, 2012
    Publication date: November 29, 2012
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei YAMAZAKI, Kengo AKIMOTO, Shigeki KOMORI, Hideki UOCHI, Tomoya FUTAMURA, Takahiro KASAHARA
  • Publication number: 20120298983
    Abstract: A semiconductor structure and an organic electroluminescence device applying the same are provided. A gate insulating layer covers a gate electrode disposed on a substrate. A channel layer has a channel length L along a channel direction and has a first side and a second side opposite to the first side. The channel layer is located on the gate insulating layer over the gate electrode. A source electrode and a drain electrode are located at and electrically connected to the first side and the second side of the channel layer, respectively. A conductive light-shielding pattern layer is disposed on a dielectric layer covering the source electrode, the drain electrode and the channel layer, and is overlapped to a portion of the source electrode and a portion of the channel layer in a vertical projection. The conductive light-shielding pattern layer and the channel layer have an overlapping length d1, and 0.3?d1/L?0.85.
    Type: Application
    Filed: August 12, 2011
    Publication date: November 29, 2012
    Applicant: AU OPTRONICS CORPORATION
    Inventors: Chih-Pang Chang, Hsing-Hung Hsieh
  • Patent number: 8318551
    Abstract: A gate electrode layer over a substrate; a gate insulating layer over the gate electrode layer; a first source electrode layer and a first drain electrode layer over the gate insulating layer; an oxide semiconductor layer over the gate insulating layer; and a second source electrode layer and a second drain electrode layer over the oxide semiconductor layer. A first part, a second part, and a third part of a bottom surface are in contact with the first source electrode layer, the first drain electrode layer, and the gate insulating layer respectively. A first part and a second part of the top surface are in contact with the second source electrode layer and the second drain electrode layer respectively. The first source electrode layer and the first drain electrode layer are electrically connected to the second source electrode layer and the second drain electrode layer respectively.
    Type: Grant
    Filed: November 30, 2009
    Date of Patent: November 27, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kengo Akimoto, Toshinari Sasaki
  • Patent number: 8319218
    Abstract: An object is to provide an oxide semiconductor layer having a novel structure which is preferably used for a semiconductor device. Alternatively, another object is to provide a semiconductor device using an oxide semiconductor layer having the novel structure. An oxide semiconductor layer includes an amorphous region which is mainly amorphous and a crystal region containing crystal grains of In2Ga2ZnO7 in a vicinity of a surface, in which the crystal grains are oriented so that the c-axis is almost vertical with respect to the surface. Alternatively, a semiconductor device uses such an oxide semiconductor layer.
    Type: Grant
    Filed: October 4, 2010
    Date of Patent: November 27, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masayuki Sakakura, Akiharu Miyanaga, Masahiro Takahashi, Takuya Hirohashi, Takashi Shimazu
  • Publication number: 20120292615
    Abstract: A memory cell therein includes a first transistor and a capacitor and stores data corresponding to a potential held in the capacitor. The first transistor includes a pair of electrodes, an insulating film in contact with side surfaces of the electrodes, a first gate electrode provided between the electrodes with the insulating film provided between the first gate electrode and each electrode and whose top surface is at a lower level than top surfaces of the electrodes, a first gate insulating film over the first gate electrode, an oxide semiconductor film in contact with the first gate insulating film and the electrodes, a second gate insulating film at least over the oxide semiconductor film, and a second gate electrode over the oxide semiconductor film with the second gate insulating film provided therebetween. The capacitor is connected to the first transistor through one of the electrodes.
    Type: Application
    Filed: May 15, 2012
    Publication date: November 22, 2012
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventor: Toshihiko Saito
  • Publication number: 20120292610
    Abstract: An oxide semiconductor device includes a gate electrode on a substrate, a gate insulation layer on the substrate, the gate insulation layer having a recess structure over the gate electrode, a source electrode on a first portion of the gate insulation layer, a drain electrode on a second portion of the gate insulation layer, and an active pattern on the source electrode and the drain electrode, the active pattern filling the recess structure.
    Type: Application
    Filed: September 9, 2011
    Publication date: November 22, 2012
    Inventors: Seong-Min Wang, Ki-Wan Ahn, Joo-Sun Yoon, Ki-Hong Kim
  • Publication number: 20120286265
    Abstract: A thin film transistor using an amorphous oxide thin film for an active layer, wherein: the amorphous oxide thin film includes, as main components, indium (In), oxygen (O), and a metal element (M) selected from the group consisting of silicon (Si), aluminum (Al), germanium (Ge), tantalum (Ta), magnesium (Mg) and titanium (Ti); an atomic ratio of M to In in this amorphous oxide thin film is 0.1 or more and 0.4 or less; and carrier density in the amorphous oxide thin film is 1×1015 cm?3 or more and 1×1019 cm?1 or less.
    Type: Application
    Filed: February 1, 2011
    Publication date: November 15, 2012
    Inventors: Kazushige Takechi, Mitsuru Nakata
  • Publication number: 20120286259
    Abstract: Exemplary embodiments of the present invention provide a display substrate including a gate electrode, an oxide semiconductor pattern, a source electrode, a drain electrode, and an etch stop pattern. The gate electrode may be disposed on a base substrate. The oxide semiconductor pattern may be disposed over the gate electrode. The source electrode may be disposed on the oxide semiconductor pattern. The drain electrode may be disposed on the oxide semiconductor pattern and spaced apart from the source electrode. The etch stop pattern may be disposed over the gate electrode, the etch stop pattern may be overlapping a space between the source electrode and the drain electrode and may include a metal oxide. The reliability of the display substrate may, therefore, be improved.
    Type: Application
    Filed: March 27, 2012
    Publication date: November 15, 2012
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae-Woo PARK, Dong-Hoon LEE, Sung-Haeng CHO, Woo-Geun LEE, Kap-Soo YOON
  • Publication number: 20120286278
    Abstract: In a thin film transistor, an increase in off current or negative shift of the threshold voltage is prevented. In the thin film transistor, a buffer layer is provided between an oxide semiconductor layer and each of a source electrode layer and a drain electrode layer. The buffer layer includes a metal oxide layer which is an insulator or a semiconductor over a middle portion of the oxide semiconductor layer. The metal oxide layer functions as a protective layer for suppressing incorporation of impurities into the oxide semiconductor layer. Therefore, in the thin film transistor, an increase in off current or negative shift of the threshold voltage can be prevented.
    Type: Application
    Filed: July 26, 2012
    Publication date: November 15, 2012
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Toshikazu KONDO, Hideyuki KISHIDA
  • Patent number: 8309179
    Abstract: A selenium/Group 1b ink comprising, as initial components: a selenium component comprising selenium, an organic chalcogenide component having a formula selected from RZ—Z?R? and R2—SH, a Group 1b component and a liquid carrier; wherein Z and Z? are each independently selected from sulfur, selenium and tellurium; wherein R is selected from H, C1-20 alkyl group, a C6-20 aryl group, a C1-20 alkylhydroxy group, an arylether group and an alkylether group; wherein R? and R2 are selected from a C1-20 alkyl group, a C6-20 aryl group, a C1-20 alkylhydroxy group, an arylether group and an alkylether group; and wherein the selenium/Group 1b ink is a stable dispersion.
    Type: Grant
    Filed: September 28, 2009
    Date of Patent: November 13, 2012
    Assignee: Rohm and Haas Electronics Materials LLC
    Inventors: Kevin Calzia, David W. Mosley, Charles R. Szmanda, David L. Thorsen
  • Patent number: 8309986
    Abstract: Semiconductor structures include a trench formed proximate a substrate including a first semiconductor material. A crystalline material including a second semiconductor material lattice mismatched to the first semiconductor material is formed in the trench. Process embodiments include removing a portion of the dielectric layer to expose a side portion of the crystalline material and defining a gate thereover. Defects are reduced by using an aspect ratio trapping approach.
    Type: Grant
    Filed: May 13, 2011
    Date of Patent: November 13, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Anthony J. Lochtefeld
  • Publication number: 20120280241
    Abstract: A thin film transistor substrate with reduced interlayer short-circuit defects in a capacitor, and a display device having the thin film transistor substrate. The thin film transistor substrate includes: a substrate; a thin film transistor having, over the substrate, a gate electrode, a gate insulating film, an oxide semiconductor layer, and a source-drain electrode in order; and a capacitor having, over the substrate, a bottom electrode, a capacitor insulating film, and a top electrode made of oxide semiconductor in order.
    Type: Application
    Filed: July 17, 2012
    Publication date: November 8, 2012
    Applicant: SONY CORPORATION
    Inventor: Toshiaki Arai
  • Publication number: 20120280229
    Abstract: There is provided a method for manufacturing a flexible semiconductor device. The method of the present invention comprises the steps of: (A) providing a metal foil; (B) forming an insulating layer on the metal foil, the insulating layer having a portion serving as a gate insulating film; (C) forming a supporting substrate on the insulating layer; (D) etching away a part of the metal foil to form a source electrode and a drain electrode therefrom; (E) forming a semiconductor layer in a clearance portion located between the source electrode and the drain electrode by making use of the source and drain electrodes as a bank member; and (F) forming a resin film layer over the insulating layer such that the resin film layer covers the semiconductor layer, the source electrode and the drain electrode. In the step (F), a part of the resin film layer interfits with the clearance portion located between the source and drain electrodes.
    Type: Application
    Filed: April 22, 2011
    Publication date: November 8, 2012
    Inventors: Takeshi Suzuki, Koichi Hirano