Abstract: A phase noise measurement module (PNMM), system and method for measuring phase noise improve accuracy of phase noise measurements of a signal under test (SUT) using a spectrum analyzer. The PNMM comprises an RF to IF frequency converter and a selectable frequency divider. The system comprises the PNMM connected to the spectrum analyzer and employs an LO signal from a tunable LO in the spectrum analyzer. The method comprises directly converting an input SUT to an IF signal having either a second or a third IF frequency that is applied to a corresponding frequency conversion stage of the spectrum analyzer before the phase noise is measured. The present invention bypasses a first conversion stage, and typically a second conversion stage as well, of the spectrum analyzer and directly converts the SUT to either the second or third IF frequency, thereby reducing phase noise added to the SUT.

Abstract: Apparatus and methods for measuring the polarization of a received signal. The horizontal and vertical signal components of the incoming signal are coupled to a plurality of channels operating in parallel, each channel having predetermined phase shift values and combining the phase-shifted components so as to produce output signals. One or more parameters of the output signals from each channel are supplied to a processor which determines values of the phase shifts which would yield a null condition, and thereby estimates the polarization of the received signal.

Abstract: An apparatus for detecting shaking of stroke of a linear compressor and a method are provided. A linear compressor mis-operates due to change in an external voltage or noise because the shaking of the stroke is detected by the amounts of change in the stroke or current.

Abstract: A servo controller for correcting a read position of a head when reading data recorded on a recording medium. In accordance with the amplitude ratio of data signals read from each segment of a servo section defined on a recording medium, the servo controller generates an AGC signal corresponding to the next segment before reading the next segment. The data signal read from a phase detection segment of the servo section is amplified to an amplitude greater than the predetermined determination range. The amplified data signal is converted to a two-value digital signal in accordance with the determination range. The phase used during servo control is calculated in accordance with the digital signal.

Abstract: The invention provides a structure, method and means for receiving a reference frequency and a variable frequency, differentiating the frequencies, and generating a logic pulse in response to a first frequency leading a second frequency, the frequencies having a small phase difference. In an aspect, the invention maintains a signal when the reference frequency and the variable frequency transition. In another aspect, the invention provides additional timing balance to prevent early generation of the logic pulses. In another aspect, the logic pulses drive a charge pump used in one of a phase-locked loop and a delay-locked loop.

Abstract: A pulse detector detects if a clock pulse signal is in phase with a reference clock pulse signal in an efficient manner with very high accuracy. The pulse detector includes a first delay unit adapted to receive an input clock pulse signal and to delay the input clock pulse signal by a first pre-specified delay for output as output clock pulse signal, and a second delay unit adapted to delay the output clock pulse signal by a second pre-specified delay. A sampling unit is adapted to sample the input clock pulse signal and the output of the second delay unit at a sampling time defined by a reference clock pulse signal and to output the samples for phase delay indication.

Abstract: A signal to be measured is waveform-formatted to a square waveform that retains the frequency, duty ratio and jitter component of the original signal, and the leading (or trailing) edge of the waveform-formatted output is sampled by a sampling clock of a frequency slightly different from 1/N of the frequency fM of the signal to be measured. The samples are converted by an A/D converter to digital data Vn(t), which is stored in a memory. The difference between the stored digital data Vn(t) and the rise-up characteristic line V′(t) is calculated to detect jitter J′n(t).

Abstract: A phase comparator for calculating the phase difference between a test wave form and an output wave form in a disk drive includes a phase converter, a first multiplier, a first integrator, a second multiplier, a second integrator and a phase angle calculator. The phase converter for delaying the test wave form for a specific time based on the frequency thereof. The first multiplier electrically coupled to the phase converter for performing a first operation by multiplying the delayed test wave form with the output wave form. The first integrator electrically coupled to the first multiplier for integrating the result of the first operation for a period to generate a first weighted value. The second multiplier for performing a second operation by multiplying the test wave form with the output wave form. The second integrator electrically coupled to the second multiplier for integrating the result of the second operation for the same period to generate a second weighted value.

Abstract: The error compensating system and method is used in electric power monitoring systems, e.g. protective relays, and includes a test unit for applying a test signal to the front end of a data acquisition section of the power monitoring system and a phase reference module which converts the test signal to a square wave having falling and rising edges corresponding to transitions between the positive and negative portions of the test signal. A programmable logic device determines the zero crossings of the sampled digital signal from the data acquisition system and then determines the time difference between a falling edge of the module output signal and the zero crossing of the sampled digital signal. The time difference is representative of the phase shift produced by the data acquisition components. A compensation circuit adjusts the digitally sampled signals with the amount of the determined phase shift.

Abstract: A non-invasive method and apparatus accurately measures the time difference between two signal edges by optically detecting the emission from a ‘beacon device’ that is modulated as a function of time difference. Through the use of this modulation it is possible to perform timing measurement accurately. Embodiments of a voltage modulator circuit modulate timing information into emission intensity. The method and system of the present invention can be used in applications such as clock skew and pulse width measurements.

Abstract: A xerographic charging device corona current is determined by forming a first signal across a sense resistor in series with the charging device power supply, forming a second signal using a resistive voltage divider network across the power supply, and forming a third signal using a resistor-capacitor charging circuit across the power supply, and then processing the first, second and third signals to form an output signal that is based on the corona current.

Abstract: A phase detector which determines the phase based upon the output signals from a power coupler. The power coupler outputs a first signal and a second signal. The first and second signals are input to a magnitude detector which determines the magnitude of the relative phase between the first and second signals. The first and second signals are also input to a sign discriminator which determines the sign of the phase between the first and second signals.

Abstract: An engagement detection circuit for a clock recovery circuit consisting of a phase detector (3), a counter element (6) and a flip-flop (8). By employing a low-pass element (12) and a trigger element (13) connected downstream, a preliminary and a final engagement of a phase control circuit can be detected with the engagement detection circuit. This provides a clock recovery circuit for controlling a phase control loop with a phase detector (20), a loop filter (21), a voltage-controlled oscillator (22) and a controllable frequency divider (23).

Abstract: A phase difference to duty-cycle circuit converts a phase shifted signal and a reference signal into a single signal having a duty cycle that is a function of the phase difference between the two signals. The single signal may be further converted to a single direct current (DC) value before being transmitted to external measurement circuitry. The external measurement circuitry, by simply measuring the magnitude of the DC signal, can determine the phase difference between the phase shifted signal and the reference signal. In an alternate embodiment, the phase shift in the target bit of a bit pattern is determined based on measurements of the DC voltage value of the shifted target bit pattern, the DC voltage value of first bit pattern comprising a non-shifted bit pattern representing a zero phase shift of the target bit, and a DC voltage value of a bit pattern comprising a non-shifted bit pattern representing a 100% phase shift of the target bit.

Abstract: A universal booster amplifier for a Coriolis flowmeter. The booster amplifier receives drive signals from a flowmeter electronics and extends conditioned drive signals to a driver for flow tubes of flowmeter sensor. The booster amplifier includes phase shift circuitry to provide improved drive signals for flowmeters having curved and straight flow tube geometries. The booster amplifier includes offline switching power circuitry which operates on a plurality of standard AC voltages. The booster amplifier combines environmentally innocuous housing and barrier circuitry to meet numerous regulatory agency safety standards for operating environments including explosive environments and increase the ease of installation and service of the booster amplifier.

Abstract: A digital frequency detector (10) and method for digitally detecting arbitrarily small phase changes between a signal waveform and a reference waveform. Both the reference waveform and the signal waveform are sampled at a rate related to the clock frequency fc, and separately fed into two arrays of simple frequency detectors (12, 14). Each simple frequency detector in each array has a different starting phase with respect to the reference waveform and the signal waveform respectively. Phase slips between the reference waveform and the sampling frequency and phase slips between the signal waveform and the sampling frequency are measured by the detector arrays (12, 14). These phase slips, called “slip events”, are combined in circuit (16) which produces an output indicative of phase slips between the reference waveform and the signal waveform. Using this phase slip information, the instantaneous frequency difference between the signal and reference waveforms can be determined.

Abstract: A phase meter measures the phase of a first signal with respect to a second signal, where the first and second signals have different frequencies and the frequency of the first signal is higher than the frequency of the second signal. The phase meter samples the first signal using the second signal to produce a plurality of samples, where each sample has a sample phase and value. The phase meter permutes the plurality of sample phases to place their phase positions in phase order, and determines, for each permuted sample phase if the sample phase is within a phase range corresponding to a predetermined phase bin. If the sample is within a phase range for a phase bin, a bin counter for that bin in incremented. The phase of the faster signal is determined based on the counts in each of the phase bins.

Abstract: A phasing and indicator arrangement is provided for switchgear or the like that responds to electrical sources and provides voltage indicator functions, phasing determinations, and self-test features. Phasing provisions are responsive to two or more voltage sensors proximate respective electrical sources to provide an output that represents the phase difference, i.e. time relationship, between the electrical sources as an alternating-current voltage measurable by a voltmeter. The output is relatively independent of the voltage of the electrical sources. The indicator arrangement is operable in a test mode to test the integrity of one or more voltage indicators while clearly identifying that the indicator arrangement is in a test mode. In a preferred arrangement, the indicator arrangement in the self-test mode is powered by a photocell.

Abstract: Resolver systems are described that generate an estimate &phgr; of a rotatable member's position angle &thgr; and provide fault signals which monitor the reliability and accuracy of the estimate. The fault signals are formed from a monitor signal which multiplies resolver and estimate signals to derive information on the absolute and relative levels of resolver sense signals. At least one fault signal is formed from a loop error signal of the system servo loop. The fault signals report on, for example, mismatched sense signals, out-of-range sense signals and loss of position tracking to thereby enhance accuracy and safety in various resolver applications.

Abstract: An apparatus for detecting shaking of stroke of a linear compressor and a method are provided. A linear compressor mis-operates due to change in an external voltage or noise because the shaking of the stroke is detected by the amounts of change in the stroke or current.

Abstract: Method and apparatus for accurately determining the presence of voltage at capacitive test points and for determining the phase angle relationship between two capacitive points. The detection of the presence of the voltage at the capacitive test points is independent of the voltage range in the systems, independent of the contamination or defects that may occur in the capacitive test point systems. The phase angle relationship is determined based on the actual phase angle difference between the voltage waveforms at the capacitive test points independent of the capacitive divider ratio difference and the capacitive test point voltage accuracy.

Abstract: The method of correcting measurements is intended to limit the risk of unnecessary tripping of a differential phase current protection system that computes the vector sum of the currents of an area to determine the differential current between the inputs and outputs of said area in the course of regular tests. It is based on a statistical balancing method using measured current vectors each obtained from a measurement of the real current vector supplied at the time of each test by a current transformer, and it uses at the time of at least one test an iterative convergence algorithm for determining from the erroneous differential current vector formed by the sum of the measured current vectors the correction vector to be applied to each measured current vector in order to correct statistically the erroneous differential current vector.

Abstract: A frequency estimator for estimating the frequency of a digital input signal (x(k)) includes a phase device (2) for determining the phase (&phgr;(k)) of the input signal (x(k)), a differentiator (3) for generating the phase difference (&phgr;diff1(k)) between adjacent samples of the phase (&phgr;(k), &phgr;(k−1)) and a filter (4) for averaging the phase difference (&phgr;diff(k)) and having a trapezoidal pulse response (hM(k)). The trapezoidal pulse response (hM(k)) is generated by superimposing a first triangular pulse response with a second triangular pulse response which is offset in time with respect to the first triangular pulse response.

Abstract: A frequency monitor includes an edge detector which produces a pulse for each rising or falling edge of an error signal. The error signal itself has a frequency that is responsive to a difference between frequencies of two input signals. A switched capacitor circuit has an effective average resistance that depends on the rate or frequency of the edge detector output pulses. A capacitor holds a charge that depends on the effective average resistance of the resistive circuit. Finally, comparator produces an output based on the charge held by the capacitor. The comparator output indicates whether the difference between the two input signal frequencies is less than some predetermined amount. A selector, responsive to the comparator, selects from a data phase detector circuit and a frequency acquisition circuit to control an oscillator. The oscillator produces a clock signal at a sampling frequency, which is used by the detector circuit to receive data.

Abstract: A method and arrangement for determining the phase difference between two timing signals provides that the first timing signal is ed to a delay line multiple times, whereby the number of passes through the delay line is obtained. The phase difference is determined in that a first transit time information is determined that corresponds to that number of delay elements of the delay line that are passed through by the first timing signal during a differential time-span between the two timing signals. Second transit time information is further obtained corresponding to that number of delay elements passed through by the first timing signal during a timing pulse period of time second timing signal. The determination of the first and second transit time information occurs dependent on the number of total passes of the first timing signal through the delay line, respectively, which is obtained at the respective determination time.

Abstract: A phase difference to duty-cycle circuit converts a phase shifted signal and a reference signal into a single signal having a duty cycle that is a function of the phase difference between the two signals. The single signal may be further converted to a single direct current (DC) value before being transmitted to external measurement circuitry. The external measurement circuitry, by simply measuring the magnitude of the DC signal, can determine the phase difference between the phase shifted signal and the reference signal. In an alternate embodiment, the phase shift in the target bit of a bit pattern is determined based on measurements of the DC voltage value of the shifted target bit pattern, the DC voltage value of first bit pattern comprising a non-shifted bit pattern representing a zero phase shift of the target bit, and a DC voltage value of a bit pattern comprising a non-shifted bit pattern representing a 100% phase shift of the target bit.