Abstract: A semiconductor integrated circuit includes a CMOS controlled inverter consisting of series-connected PMOS and NMOS transistors. The source of the NMOS transistor is coupled to a ground line through an additional NMOS transistor for power gating of voltage VSS. The source of the PMOS transistor can be coupled to a power supply line through an additional PMOS transistor for power gating of voltage VDD. The inverter receives an input signal IN and its complementary version that has transitioned earlier than the input signal. In response to the input signal, the inverter produces an output signal. A NAND gate that receives the output signal and the complementary input signal controls the power gating NMOS transistor. A NOR gate that receives the output signal and the complementary input signal controls the power gating PMOS transistor.

Abstract: A tapered chain of delay elements. The chain of delay elements includes a plurality of delay elements comprising a plurality of smaller sized stacked inverter delay elements each configured to implement a first delay, and a plurality of larger sized stacked inverter delay elements each configured to implement a second delay larger than the first delay. A switch circuit is coupled to the plurality of delay elements and is configured to select at least one of the plurality of delay elements to create a delay signal path having an amount of delay in accordance with a number of delay elements comprising the delay signal path. An input is coupled to a first delay element of the delay signal path to receive an input signal. An output is coupled to the switch circuit, wherein the output is coupled to the delay signal path to receive a delayed version of the input signal after propagating through the delay signal path.

Abstract: Circuit with enhanced mode and normal mode is provided and described. In one embodiment, switches are set to a first switch position to operate the circuit in the enhanced mode. In another embodiment, switches are set to a second switch position to operate the circuit in the normal mode.

Abstract: An object of the present invention is to provide a technique of reducing the leakage current of a drive circuit for driving a circuit that must retain a potential (or information) when in its standby state. A semiconductor integrated circuit device of the present invention includes a drive circuit for driving a circuit block. This drive circuit is made up of a double gate transistor with gates having different gate oxide film thicknesses. When the circuit block is in its standby state, the gate of the double gate transistor having a thinner gate oxide film is turned off and that having a thicker gate oxide film is turned on. This arrangement allows a reduction in the leakage currents of both the circuit block and the drive circuit while allowing the drive circuit to deliver or cut off power to the circuit block.

Abstract: A storage circuit has an input for receiving and storing data, a first power terminal coupled to a first conductor for receiving a first power supply voltage, and a second power terminal coupled to a second conductor. A power gate device has a first terminal coupled to the second conductor, a control terminal for receiving a bias voltage in response to a control signal, and a second terminal coupled to a terminal for receiving a second power supply voltage. A shorting device selectively electrically short circuits the first terminal of the power gate device to the control terminal of the power gate device in response to the control signal, thereby converting the power gate device from a transistor into a diode-connected device. The shorting device is smaller in size than the power gate device.

Abstract: Circuits using four terminal junction field effect transistors (JFETs) are disclosed. Such circuits can include various static and dynamic logic circuits, flip-flops, multiplexer, tri-state driver, phase detector, logic having variable speeds of operation, and/or analog circuit with such four terminal JFETs operating in a linear or nonlinear mode.

Abstract: Some embodiments provide dynamic circuits with dynamic nodes that may float during a disable mode to reduce leakage.

Abstract: A low-voltage differential signal driver for high-speed digital transmission includes a first converter operable to receive a signal in a first type and convert the signal into a second type, and a cascode current mirror coupled to the first converter. The cascode current mirror provides an impedance level that increases a differential output voltage.

Abstract: An integrated circuit that includes a gate control voltage generator that supplies a current control gate voltage to a plurality of current control devices of a corresponding plurality of dynamic logic circuits each having a keeper circuit. The gate control voltage generator provides, via current control gate voltage, global control of the amount of keeper current flowing through the keeper circuits so as to enhance the performance of the dynamic logic circuits.

Abstract: A method for using an inverter with a pair of complementary junction field effect transistors (CJFET) with a small linewidth is provided. The method includes having an input capacitance for said CJFET inverter to be less than the corresponding input capacitance of a CMOS inverter of similar linewidth. The CJFET operates at a power supply with a lesser value than the voltage drop across a forward-biased diode having a reduced switching power as compared to said CMOS inverter and having a propagation delay for said CJFET inverter that is at least comparable to the corresponding delay of said CMOS inverter.

Abstract: A current mode logic digital circuit is provided comprising a logic circuit component having at least one data input node and at least one output node. A load is coupled between a power supply node and the output node. The load comprises a folded active inductor coupled to the output node.

Abstract: Disclosed is a logic circuit including first and second input terminals, supplied with respective logic signals, and first and second MOS transistors, having sources respectively connected to associated ones of the first and second input terminals and gates cross-connected to the second and first input terminals. The drains of the first and second MOS transistors are connected in common. The logic circuit also includes a MOS transistor, connected between a first power supply and a common node of the drains of the first and second MOS transistors and having a gate supplied with a reset signal so that the MOS transistor is turned on at the time of resetting. The logic circuit further includes an inverter having an input end connected to the common node.

Abstract: The invention discloses new and advantageous uses for carbon/graphene nanoribbons (GNRs), which includes, but is not limited to, electronic components for integrated circuits such as NOT gates, OR gates, AND gates, nano-capacitors, and other transistors. More specifically, the manipulation of the shapes, sizes, patterns, and edges, including doping profiles, of GNRs to optimize their use in various electronic devices is disclosed.

Abstract: Circuitry for preventing damage to differentially coupled input JFETs in an integrated circuit amplifier includes first (J2) and second (J4) differentially coupled input JFETs. A first input signal (Vin+) is applied to a gate of the first input JFET (J2), and second input signal (Vin?) is applied to a gate of the second input JFET. Needed amounts of drain current are supplied to the first and second input JFETs. A separator JFET (J1) having a drain coupled to a source of the first input JFET and a source coupled to the source of the second input JFET is operated to control an amount of electrical isolation between the drain and source of the separator JFET so as to limit an amount of reverse bias voltage across a gate-source junction of one of the first and second input JFETs to a value less than a gate-source junction breakdown voltage of that the first and second input JFETs.

Abstract: An inverter circuit (500) having a drive transistor (102) that operably couples to a voltage bias input (101) (and where that drive transistor controls the inverter circuit output by opening and closing a connection between the output (105) and ground (104)) is further operably coupled to a feedback switch (401). In a preferred approach the feedback switch is itself also operably coupled to the voltage bias input and the output and preferably serves, when the drive transistor is switched “off,” to responsively couple the voltage bias input to the drive transistor in such a way as to cause a gate terminal of the drive transistor to have its polarity relative to a source terminal of the drive transistor reversed and hence permit the inverter circuit to operate across a substantially full potential operating range of the drive transistor.

Abstract: The disclosure relates to a logic cell for an integrated circuit, including two redundant outputs, a first output equipped with an output transistor of type P and a second output equipped with an output transistor of type N. Such a cell includes isolation element connecting the first and second outputs and forming an isolation resistance.

Abstract: A semiconductor integrated circuit device may include a first internal circuit operating at a first voltage higher than a power supply voltage of the device, and a second internal circuit operating at a second voltage lower than the first voltage. An interface circuit may be provided to restrict a voltage transferred from the first internal circuit to the second internal circuit. The first internal circuit may include a metal oxide semiconductor (MOS) transistor having a relatively thick gate insulation layer, and the second internal circuit may have a MOS transistor having a relatively thin gate insulation layer. The interface circuit, by restricting voltage, may reduce an electric field applied to the gate insulation layer of the second MOS transistor in an effort to prevent a reduction in turn-on speed of the second MOS transistor.

Abstract: A logic gate includes a first driver connected to a first power source, a first control transistor connected between a first node and a second power source to control a voltage of the first node, a second driver connected between a gate electrode of the first control transistor and the second power source, a third driver connected between the first power source and the second power source, a second control transistor connected between the third driver and the second power source, and having a first electrode connected to an output terminal, and a fourth driver arranged between a gate electrode of the second control transistor and the second power source, wherein the first control transistor, the second control transistor and each transistor of the first driver, the second driver, the third driver and the fourth driver are PMOS transistors.

Abstract: A first current source generating a current I0+I when a control signal is in ‘H’ level and a current I0 when it is in ‘L’ level, a current mirror circuit transferring a current generated in the first current source and composed of first and second MOS transistors, and a second current source connected to the second transistor and generating I0+I are provided. Further, a node branched from a connection node between the second transistor and the second current source is formed, and a logic unit including a flip-flop circuit formed of a differential amplifier is driven through the node. The logic unit is in an active state when the control signal is in ‘H’ level and it is in an inactive state when the signal is in ‘L’ level. When the logic unit is in an active state, it processes a data input signal to generate data output signal.

Abstract: Various systems and methods for implementing dynamic logic are disclosed herein. For example, some embodiments of the present invention provide dynamic logic devices with a logic circuit that includes an inverting output buffer, a logic function, a bias transistor, and a current circuit. An input of the logic function is electrically coupled to a logic input, an output of the logic function is electrically coupled to an input of the inverting output buffer, and the logic function exhibits a leakage current. The gate of the bias transistor is electrically coupled to an output of the inverting buffer, and a first leg of the bias transistor is electrically coupled to the input of the inverting buffer. The current circuit supplies a current corresponding to the to a second leg of the bias transistor. In some cases, an improved performance may be achieved for a given leakage, or a reduced leakage may be achieved for a given performance.

Abstract: The invention provides a low cost and high performance functional circuit by reducing time required for the repetition of logic synthesis and routing of layout in a functional circuit design. A standard cell used for the logic synthesis and the routing of layout is configured by a logic circuit on an output side and a logic circuit on an input side and a driving capacity of the logic circuit on the output side is made large while gate input capacitance of the logic circuit on the input side is made small. By forming the standard cell in this manner, a ratio that the gate delay occupies in the delay time of a functional circuit can be relatively increased. Therefore, even when wiring capacitance after the routing of layout is not estimated at high precision in advance, an operating frequency can be obtained at high precision in the logic synthesis as long as a gate delay of each standard cell can be estimated at high precision.

Abstract: A semiconductor integrated circuit comprises logic cones having a structure in which substrates thereof are isolated from each other and substrate potentials can be controlled, and a potential switching section for supplying a substrate voltage from any of a first substrate bias supply potential and a second substrate bias supply potential to the logic cone. A signal output by a logic cone previous to a logic cone whose substrate potential is controlled is input as a trigger signal to the substrate supply potential switching section.

Abstract: An output driver of a semiconductor memory device that operates in a differential mode and in a single mode is disclosed. The output driver includes a current supplying circuit that operates as a resistor in a single mode and as a current source in a differential mode. Accordingly, the semiconductor memory device including the output driver can have high test efficiency, since the number of test pins utilized during a test operation can be selectively reduced for low frequency tests.

Abstract: The present invention is directed to a circuit and a method that features selectively isolating a logic device from a source of power implementing a counter circuit to transmit a signal to a voltage control device to isolate a source of power from a logic device, coupled to a plurality of switching elements, with the voltage control device being coupled to allocate power to the logic device in response to activation of one of said plurality of switching elements. The logic device is typically a programmable logic device. In one embodiment, the voltage control device is a field effect transistor. In another embodiment the voltage control device is a voltage regulator.

Abstract: A power gated semiconductor integrated circuit comprises: (1) logic circuit to be power gated, said logic circuit having a virtual ground rail; (2) footer device disposed between said virtual ground rail and a ground rail for reducing power consumption of said logic circuit; and (3) virtual rail voltage clamp disposed electrically in parallel with said footer device for limiting the voltage at the virtual ground rail, the virtual rail voltage clamp comprising at least one NFET. A total of Nf NFETs are connected to the virtual ground rail of the integrated circuit for use as both virtual rail voltage clamps and footer devices. A quantity of Nmax-VC NFETs are scanned and perform the function of voltage clamps and the remaining (Nf?Nmax-VC) NFETs perform power gating. Manufacturing variability immunity and tuning of the variability immunity is achieved by adjusting the quantity Nmax-VC based upon testing of the manufactured integrated circuit.

Abstract: A method for using an inverter with a pair of complementary junction field effect transistors (CJFET) with a small linewidth is provided. The method includes having an input capacitance for said CJFET inverter to be less than the corresponding input capacitance of a CMOS inverter of similar linewidth. The CJFET operates at a power supply with a lesser value than the voltage drop across a forward-biased diode having a reduced switching power as compared to said CMOS inverter and having a propagation delay for said CJFET inverter that is at least comparable to the corresponding delay of said CMOS inverter.

Abstract: The invention includes an error correcting logic system that allows critical circuits to be hardened with only one redundant unit and without loss of circuit performance. The system provides an interconnecting gate that suppresses a fault in one of at least two redundant dynamic logic gates that feed to the interconnecting gate. The system is applicable to dynamic or static logic systems. The system prevents propagation of a fault, and addresses not only soft errors, but noise-induced errors.

Abstract: A design structure for an integrated circuit that includes a gate control voltage generator that supplies a current control gate voltage to a plurality of current control devices of a corresponding plurality of dynamic logic circuits each having a keeper circuit. The gate control voltage generator provides, via current control gate voltage, global control of the amount of keeper current flowing through the keeper circuits so as to enhance the performance of the dynamic logic circuits.

Abstract: The logic gate of the present invention is of a configuration that includes a first transistor, a second transistor, and a connection-switching unit. The first transistor receives a first voltage at its source, a first input signal at its gate, and supplies a first output signal from its drain. The second transistor receives a second voltage that is lower than the first voltage at its source, receives a second input signal at its gate, and supplies a second output signal from its drain. The connection-switching unit is connected between the drains of the first transistor and the second transistor for connecting and cutting off the first transistor and the second transistor.

Abstract: Embodiments of the invention provide an interface circuit that is capable of reducing the power consumption, which may be increased by a shoot-through current, and provide an electronic device having such an interface circuit. In one embodiment, an interface circuit exchanges signals with another electronic device via a signal transmission line. The interface circuit includes a switch for pulling up the signal transmission line and a switch for pulling down the signal transmission line. While a pull-up or pull-down is performed, the interface circuit detects the potential level of the signal transmission line to determine whether the signal transmission line is pulled down or pulled up by the other electronic device. If the signal transmission line is not pulled down/pulled up by the other electronic device, the interface circuit exercises pull-down/pull-up control.

Abstract: In some embodiments, a transmitter includes a first circuit coupled to an input port of the transmitter, and a second circuit coupled to the first circuit and to an output port of the transmitter, wherein the first circuit is sized with respect to the second circuit such that for a pulse signal applied to the input port, the transmitter generates an output signal having a rise-time and a fall-time that are substantially equal at the output port.

Abstract: The present invention implements structures and method for non-delayed clock dynamic logic circuit configurations with output and/or complementary output with reduced glitch and/or mitigating adverse charge-sharing effects for Complementary Oxide Semiconductor (CMOS) and/or mitigating parasitic bipolar action in Strained/Unstrained Silicon-On-Insulator (SOI) circuits, where insulator may be oxide, nitride of Silicon and the like or Sapphire and the like including a method of synthesis.

Abstract: A nonvolatile programmable logic circuit using a ferroelectric memory performs a nonvolatile memory function and an operation function without additional memory devices, thereby reducing power consumption. Also, a nonvolatile ferroelectric memory is applied to a FPGA (Field Programmable Gate Array), thereby preventing leakage of internal data and reducing the area of a chip.

Abstract: A power gated semiconductor integrated circuit comprises: (1) logic circuit to be power gated, said logic circuit having a virtual ground rail; (2) footer device disposed between said virtual ground rail and a ground rail for reducing power consumption of said logic circuit; and (3) virtual rail voltage clamp disposed electrically in parallel with said footer device for limiting the voltage at the virtual ground rail, the virtual rail voltage clamp comprising at least one NFET. A total of Nf NFETs are connected to the virtual ground rail of the integrated circuit for use as both virtual rail voltage clamps and footer devices. A quantity of Nmax-VC NFETs are scanned and perform the function of voltage clamps and the remaining (Nf-Nmax-VC) NFETs perform power gating. Manufacturing variability immunity and tuning of the variability immunity is achieved by adjusting the quantity Nmax-VC based upon testing of the manufactured integrated circuit.

Abstract: A dynamic and differential CMOS logic style is disclosed in which a gate uses a fixed amount of energy per evaluation event. The gate switches its output at every event and loads a constant capacitance. The logic style is a Dynamic and Differential Logic (DDL) style. The DDL style logic typically has one charging event per clock cycle and the charging event does not depend on the input signals. The differential feature masks the in-put value because a precharged output nodes is discharged during the evaluation phase. The dynamic feature breaks the input sequence: the discharged node is charged during the subsequent precharge phase.

Abstract: A method and system for automatically detecting and optimally compensating a wide range of die leakage currents in dynamic circuits is presented. A self-adaptive keeper tracks the leakage and reduces the leakage effects by optimally controlled compensation current. The self-adaptive keeper utilizes a 2-stage embedded current mirror circuit, a dummy cell and a keeper transistor to compensate leakage current. The load impact of the self-adaptive keeper on the dynamic circuit components (for example, the impact on memory cells) is minimized by a dummy cell which detects and matches the instant leakage current. Amplification in the 2-stage embedded current mirror circuit provides an optimal current strength in the keeper transistor. The optimally amplified leakage current is utilized to compensate for a leakage induced voltage drop at the circuit's output. Thus, the self-adaptive keeper ensures the robustness of the circuit in real time and does not create any negative trade-off on read latency.

Abstract: A circuit capable of reducing a consumption current is provided for a digital display device composed of unipolar TFTs. There is provided a latch circuit for holding a digital video signal. According to the latch circuit, when the digital video signal is inputted to an input electrode of a TFT (101), a non-inverting output signal is outputted from an output electrode of the TFT (101) and an inverting output signal is outputted from output electrodes of TFTs (102 and 103). Two line outputs of non-inversion and inversion are obtained. Thus, when a buffer located in a subsequent stage is operated, a period for which a direct current path is produced between a high potential and a low potential of a power source can be shortened, thereby contributing to reduction in a consumption current.

Abstract: A semiconductor integrated circuit device has a combinational logic circuit including one or plural logic cells connected in series.

Abstract: A complementary pass-transistor logic includes input nodes provided with first complementary signals; intermediate nodes for outputting complementary intermediate signals; a logic network comprised of NMOS transistors, the network being connected between the input nodes and the intermediate nodes, and the conduction states of the transistors being controlled by second complementary input signals to output a logical operation result of the first and second input signals to the intermediate nodes; and inverters for inverting the intermediate signals and producing complementary output signals, wherein the NMOS transistors of the logic network are configured as a depletion-type NMOS.

Abstract: The logic gate of the present invention is of a configuration that includes a first transistor, a second transistor, and a connection-switching unit. The first transistor receives a first voltage at its source, a first input signal at its gate, and supplies a first output signal from its drain. The second transistor receives a second voltage that is lower than the first voltage at its source, receives a second input signal at its gate, and supplies a second output signal from its drain. The connection-switching unit is connected between the drains of the first transistor and the second transistor for connecting and cutting off the first transistor and the second transistor.

Abstract: A threshold voltage of a transistor is fluctuated because of fluctuation in film thickness of a gate insulating film or in gate length and gate width caused by differences of used substrates or manufacturing steps. In order to solve the problem, according to the present invention, there is provided a clocked inverter including a first transistor and a second transistor connected in series, and a compensation circuit including a third transistor and a fourth transistor connected in series.

Abstract: In accordance with some embodiments, logical circuits comprising carbon nanotube field effect transistors are disclosed herein.

Abstract: A CML digital circuit includes a load coupled between a power supply node and at least one output node and a logic circuit component coupled to the output node. The logic circuit component has at least one data input node. The logic circuit component comprises a first circuit module and a second circuit module. A first tail current source is coupled to the first circuit module. A second tail current source is coupled to the second circuit module. A first switch is coupled between the power supply node and the first tail current source. A second switch is coupled between the power supply node and the second tail current source, wherein the first switch is triggered to deactivate the first circuit module when the second circuit module is operating and the second switch is triggered to deactivate the second circuit module when the first circuit module is operating.

Abstract: A buffer circuit has a first transistor and a second transistor in a cascode, and a buffer switch coupled from an output of the buffer to a gate of the second transistor. The buffer circuit is bootstrapped by a bootstrap capacitor, a diode circuit, and a bootstrap switch. The bootstrap capacitor is coupled from the output to the gate of the second transistor through the bootstrap switch. A potential difference is set up across the bootstrap capacitor through the diode circuit. When a low input is given to the buffer circuit, the second transistor turns off and the output goes to a high bias voltage through the first transistor. When a high input is given, the first transistor turns off, the second transistor turns on, and as the output goes low, the gate of the second transistor is bootstrapped to drop the output completely down to a low bias voltage.

Abstract: Techniques for employing multi-gate field effect transistors (FETS) in logic circuits formed from logic gates are provided. Double-gate transistors that conduct only when both transistor gates are active can be used to reduce the number of devices hitherto required in series or “stacked” portions of logic gates. Circuit area can be reduced and performance can be enhanced.

Abstract: An SOI structure semiconductor integrated circuit is disclosed that reduces the number of power supply wires setting substrate potential of a semiconductor element and reduces power consumption. With an SOI structure semiconductor integrated circuit, a first circuit block 51 does not include a critical path and a second circuit block 61 does include a critical path. First power supply wiring 28 supplies a first power supply and second power supply wiring 29 supplies a second power supply of a high-voltage compared to the first power supply. A wiring section 71 (P-channel first substrate power supply wiring and P-channel first power supply wiring) supplies the first power supply as a substrate power supply for P-channel elements of the first circuit block 51 and a source power supply.

Abstract: A switching model to create stable binary sequential devices comprised of one or more logic functions with feedback of which an output signal is uniquely related to an input signal is applied to possible binary logic functions. Static latches of commutative and non-commutative binary functions are designed by using the switching model. Latches can be realized by individually controlled gates sometimes with inverters. Optical and electro-optical latches are disclosed. The application of transmission gates to realize latches is also disclosed.

Abstract: Method and apparatus for analog compensation of driver output signal slew rate against device impedance variation. The method includes a signal termination device coupled to a driver output pad. In one embodiment, driver includes a pull-up circuit having at least one pull-up device and a pull-down circuit including at least one pull-down device. In one embodiment, the pull-up circuit and the pull-down circuit including corresponding pull-up and pull-down compensation resistive elements. Accordingly, the pull-up and pull-down compensation resistive elements provide analog compensation of a driver output signal slew rate against device impedance variation. In one embodiment, a slew rate of the driver output signal is within a predetermined slew rate range to avoid uncontrolled fast switching as well as unnecessarily slow switching in the driver output signal. Other embodiments are described and claimed.

Abstract: A complementary logic circuit contains a first logic input, a second logic input, a first dedicated logic terminal, a second dedicated logic terminal, a first logic block, and a second logic block. The first logic block consists of a network of p-type transistors for implementing a predetermined logic function. The p-type transistor network has an outer diffusion connection, a first network gate connection, and an inner diffusion connection. The outer diffusion connection of the p-type transistor network is connected to the first dedicated logic terminal, and the first network gate connection of the p-type transistor network is connected to the first logic input. The second logic block consists of a network of n-type transistors which implements a logic function complementary to the logic function implemented by the first logic block. The n-type transistor network has an outer diffusion connection, a first network gate connection, and an inner diffusion connection.

Abstract: A circuit for calculating a logical combination of two input operands includes a first input for receiving a first dual rail signal having data values of the first input in a calculation cycle and precharge values in a precharge cycle, a second input for receiving a second dual rail signal having data values of the second input in the calculation cycle and precharge values in the precharge cycle, and an output for outputting a third dual rail signal having result values in the calculation cycle and precharge values in the precharge cycle.