Abstract: The invention includes digital logic devices with extremely skewed trip points and reset circuitry for rapidly propagating signal edges. Embodiments of skewed logic devices in accordance with the present invention include inverters, buffers, NOR gates and NAND gates for rapidly propagating a selected “fast” edge of an input signal. Additional embodiments include pulse stretchers, memory devices, substrates, computer systems and methods incorporating the skewed logic devices of the present invention. Each embodiment of a skewed logic device of the present invention is configured to propagate either a fast rising edge or fast falling edge of an output signal, i.e., the “fast” edge, at rates comparable to those of domino logic. An advantage of the skewed logic devices of the present invention over conventional CMOS logic devices is rapid edge propagation. Additionally, virtually all of the input gate loading is devoted to the fast edge being propagated.

Abstract: The invention includes digital logic devices with extremely skewed trip points and reset circuitry for rapidly propagating signal edges. Embodiments of skewed logic devices in accordance with the present invention include inverters, buffers, NOR gates and NAND gates for rapidly propagating a selected “fast” edge of an input signal. Additional embodiments include pulse stretchers, memory devices, substrates, computer systems and methods incorporating the skewed logic devices of the present invention. Each embodiment of a skewed logic device of the present invention is configured to propagate either a fast rising edge or fast falling edge of an output signal, i.e., the “fast” edge, at rates comparable to those of domino logic. An advantage of the skewed logic devices of the present invention over conventional CMOS logic devices is rapid edge propagation. Additionally, virtually all of the input gate loading is devoted to the fast edge being propagated.

Abstract: A CMOS output cell with multiple output modes is disclosed. In one embodiment, the cell drives a differential output signal on two output pads in one mode and two single-ended output signals on the two output pads in another mode. Differential and single-ended driver transistors are included for this purpose. A logic circuit disables unused driver transistors, and supplies appropriate drive signals to those transistors for each mode. When disabled, the driver transistors serve an electrostatic discharge (ESD) protection function, at least partially alleviating the need for ESD-specific devices in the cell. The diminished need for ESD-specific devices allows the cell to offer a highly flexible chip interface, with little or no increase in circuit area over a conventional cell that offers only single-ended or differential output.

Abstract: A technique provides an on-chip voltage to a core portion of an integrated circuit by way of a conversion transistor. The on-chip voltage may be a reduced internal voltage, less than the VCC of the integrated circuit. In an embodiment, the layout (or physical structure) of the conversion transistor is distributed surrounding the core portion. By providing the core with a reduced voltage, the integrated circuit may interface with other integrated circuits compatible with different voltage levels.

Abstract: An amplifier includes differential input transistors, first switches arranged between each gates and source of the differential input transistors, a second switch arranged to turn on/off a current source that gives the bias of the differential input transistors, and a drive circuit arranged to turn off the second switch and turns on the first switches when the current of the current source is not supplied to the differential input transistors.

Abstract: A method and apparatus for operating logic circuitry with recycled energy. Logic circuitry is used which has a node for storing energy and a return node that is connected to energy storage circuitry. The logic circuitry operates, using energy stored on the node, to determine a logic output based on a logic input during a first phase. The energy storage circuitry capture a portion of the stored energy during the operation of the logic circuitry and transfers a portion of the captured energy back to the node during a second phase. In one embodiment, the logic circuitry and the energy storage circuitry form a resonant circuit and the logic circuitry operates synchronously to a clock. In another embodiment, the energy storage circuitry includes a resonant circuit configured to oscillate with a determinable period. The resonant circuit is tunable so that its oscillations can be synchronized to a clock.

Abstract: A prebuffer circuit configured to generate one or more output control signals in response to one or more current sources and an input signal. The one or more output control signals may reduce a process dependent charge to discharge skew.

Abstract: A reduced-leakage current dynamic circuit (10) is disclosed that includes a logic circuit (30), a pre-charge transistor (32), and a standby transistor (40). The logic circuit (30) is coupled to an internal output node (50). The logic circuit (30) includes a plurality of logic transistors (60 and 62) having a low threshold voltage. The pre-charge transistor (32) is coupled to the internal output node (50). The pre-charge transistor (32) is operable to provide a pre-charge voltage at the internal output node (50) and has a standard threshold voltage. The standby transistor (40) is coupled to the internal output node (50). The standby transistor (40) is operable to provide a standby voltage at the internal output node (50).

Abstract: A method for improving the speed of conventional CMOS logic families is disclosed. When applied to static CMOS, OPL retains the restoring character of the logic family, including its high noise margins. Speedups of 2× to 3× over (optimized) conventional static CMOS are demonstrated for a variety of circuits, ranging from chains of gates, to datapath circuits, and to random logic benchmarks. Such speedups are obtained using identical netlists without remapping. When applied to pseudo-nMOS and dynamic families, in combination with remapping to wide-input NORs, OPL yields speedups of 4× to 5× over static CMOS. Since OPL applied to static CMOS is faster than conventional domino logic, and since it has higher noise margins than domino logic, we believe it will scale much better than domino with future processing technologies.

Abstract: A pre-buffer circuit configured to generate one or more output control signals in response to a bandgap reference based control circuit. The one or more output control signals control output ON resistance and slew rate so as to limit variations in ringing and skew.

Abstract: An inverter circuit is disclosed that prevents flow of a large feedthrough current. The inverter circuit includes depletion type MOS transistor combined with a resistor to impose a current limitation when a feedthrough current flows.

Abstract: One embodiment of a complimentary input buffer uses six symmetrically arranged inverters. A pair of inverters are coupled between a respective input terminal and a respective output terminal with the input of the inverters coupled to the input terminals and the output of the inverter coupled to the output terminals. The input and output of an inverter are also coupled to each of the output terminals. Finally, a pair of inverters are connected in parallel with each other in opposite directions between the output terminals. In another embodiment, a pair of inverters are also coupled between a respective input terminal and a respective output terminal. However, the output of a respective inverter is coupled to each output terminal, and the inputs of the inverters are coupled to a voltage divider circuit connected between the output terminals.

Abstract: Very high speed operation and reduction of power consumption are realized simultaneously in a two-wire type logical circuit having a halt value and an effective value as signal values. Signal rise transition delay time and signal fall transition delay time are purposely designed asymmetrically and an effective value propagation delay is shortened, thereby accelerating an operating speed of the logical circuit. By eliminating a clock signal from a DOMINO circuit, power consumption is reduced. An architecture for concealing a halt value propagation delay is employed.

Abstract: A circuit for providing a control signal for a load includes a first switch having a first and a second state, a second switch having a first and a second state coupled to said first switch, a load connected to said first and second switches, protection circuitry for protecting said load from excessive voltage and circuitry for switching said first switch. The circuit is arranged so that when the first switch is in the first state current flows from the load to the first switch and the switching circuitry is arranged to switch the first switch to the second state when the voltage across the load reaches a predetermined value.

Abstract: To speed up the operation of a decoder circuit, reduce the power consumption of the decoder circuit and increase the cycle, each circuit such as a buffer, a predecoder and a main decoder in the decoder circuit is composed by a semiconductor logic circuit wherein the number of columns of transistors for pulling down at an output node is small even if the number of inputs is many and the true and a complementary output signal having approximately the same delay time are acquired and the output pulse length of each circuit in the decoder circuit is reduced.

Abstract: A stack device is provided to obtain a stack effect. The stack device includes at least first and second active components. The first and second active components have first and second device widths, respectively. The first and second device widths are then selected to provide a desired leakage current and gate delay time for the stack device. The selection includes adjusting the first and second device widths while keeping a sum of the device widths constant.

Abstract: A combination NAND and flip-flop circuit includes a pre-NAND scan circuit operable to receive a plurality of input signals and produce first and second output signals for receipt by a NAND gate. The plurality of signals comprises signals indicative of a first data signal, a second data signal, a scan-in signal, and a scan-enable signal. These circuits include a NAND gate having first and second inputs operable to receive the first and second output signals of the pre-NAND scan circuit. They also include a first transmission gate and a first inverter. The transmission gate receives the output of the NAND gate and the inverter receives the output of the transmission gate. The pre-NAND scan circuit is operable to produce the first and second output signals based on the plurality of input signals such that the first and second output signals are defined as described below.

Abstract: Zero-power logic cells are implemented in CMOS technology for forming part of programmable logic devices with minimized static power dissipation. The zero-power logic cells are implemented with stacked P-channel and N-channel field effect transistors. The respective gate of each of such P-channel and N-channel transistors are coupled to one of a first input signal, a second input signal, an output of a first memory cell, or an output of a second memory cell. The output node of the logic cell is one of a logic cell input signal, a complement of the logic cell input signal, the logical high state, or the logical low state depending on the outputs of the memory cells in a functional mode. In addition, such zero-power logic cells may be used to verify the respective output of each of the first and second memory cells in a verify mode.

Abstract: A domino logic circuit includes an n-channel clock transistor coupled between a dynamic output node and a high voltage connection, the gate of the clock transistor further coupled to receive an inverse clock signal. A first inverter has an input connected to the dynamic output node. A second inverter with an input connected to the dynamic output node comprises a static CMOS circuit stage, the output of which is the output of the domino logic circuit. A p-channel level keeper transistor is connected between the dynamic output node and the high voltage connection, and the gate of the level keeper transistor is connected to the output of the first inverter. A pull-down circuit is connected between the dynamic output node and a low-voltage connection. A pull-up circuit is connected between the static CMOS circuit output and the high voltage connection.

Abstract: One embodiment of the present invention provides a system that asynchronously distributes data to a plurality of destinations within a digital circuit. Upon receiving a data item to be distributed, the system monitors asynchronous control signals associated with the destinations, wherein a given asynchronous control signal indicates that a given destination is free to receive the data item. For each destination that is free to receive the data item, the system forwards the data item to the destination asynchronously without waiting for a system clock signal, and also changes an asynchronous control signal associated with the destination to indicate that the destination is not free to receive a subsequent data item.

Abstract: One embodiment of a complimentary input buffer uses six symmetrically arranged inverters. A pair of inverters are coupled between a respective input terminal and a respective output terminal with the input of the inverters coupled to the input terminals and the output of the inverter coupled to the output terminals. The input and output of an inverter are also coupled to each of the output terminals. Finally, a pair of inverters are connected in parallel with each other in opposite directions between the output terminals. In another embodiment, a pair of inverters are also coupled between a respective input terminal and a respective output terminal. However, the output of a respective inverter is coupled to each output terminal, and the inputs of the inverters are coupled to a voltage divider circuit connected between the output terminals.

Abstract: A transmission side circuit and a reception side circuit are connected to each other via a signal transfer path. An output transistor of the transmission side circuit has an open drain type structure, and the reception side circuit is provided with a reception transistor that is connected to the signal transfer path. There are provided a precharge transistor for supplying a voltage to a node extending from the reception transistor to an internal circuit, and a selector circuit connected to the gate of the reception transistor. The selector circuit receives a bias voltage Vbi and a ground voltage Vss, and switches the voltage to be applied to the gate of the reception transistor between the bias voltage Vbi and the ground voltage Vss according to the mode switching signal Smd. It is possible to suppress the voltage amplitude of a signal along the signal transfer path, and thus to reduce the electromagnetic interference occurring along the signal transfer path.

Abstract: A level shifter uses a current mirror as a current switch connected to the drains of two oppositely-driven FETs. A switch selectively connects the current mirror to its power supply so that no quiescent DC current flows.

Abstract: An MOS-type semiconductor integrated circuit has two MOS transistors of the opposite conductivity channel types connected in series between a high-voltage potential terminal and a ground potential terminal. Those two MOS transistors constitute an inverter and their gates are connected together to an input node. As output nodes, first and second nodes are provided with a current path in between which includes transistors whose gates are connected to the high-voltage potential terminal. A current path including the first transistor which constitutes a switch is inserted between the first node and the output node, and a current path including the second transistor and a barrier transistor is inserted between the second node and the output node. The gates of the first and second transistors are respectively connected with complementary clock signals. The bate of the barrier transistor is connected to the high-voltage potential terminal.

Abstract: A dynamic wide NOR gate with improved precharge node capacitance and leakage. This improves speed for many applications. Two precharge nodes are used instead of one. During the evaluate phase of the dynamic gate, the state of the two precharge nodes may be changed by a number of pulldown FETs. The state of these two precharge nodes are combined by a logic function that is enabled during the evaluate phase of the gate to produce a signal that is latched to produce the wide NOR gate output. This latched signal is also used to provide feedback to the precharge nodes to keep them from discharging due to parasitic effects such as the leakage current.

Abstract: A circuit and a method to realize a programmable delay between two adjacent signal paths, each having a different timing domain. In a preferred embodiment, each signal path is a stage of domino logic and the programmable delay is positioned at the boundary to adjust the timing between the two stages. The delay is programmed depending upon the value of an input signal to be either a static delay and hence part of the first stage of domino logic; or a dynamic delay to be part of a subsequent stage of domino logic. Critical paths can easily be balanced after fabrication, either at wafer test or once the circuit is mounted on an integrated chip and then tested, with the programmable gate as disclosed herein.

Abstract: A semiconductor integrated circuit device comprises a plurality of MIS transistors, and an integrated circuit unit including logic gate circuits configured by a combination of the plurality of MIS transistors. Each of the MIS transistors has a gate including a circuit element represented by an equivalent circuit in which a capacitance and resistance are parallel-connected.

Abstract: A P channel MOS transistor and an N channel MOS transistor turned on/off in response to an input signal in an active state as well as an N channel MOS transistor connected between an output node and the N channel MOS transistor and turned on/off in response to a control signal are provided. The input signal is at the L level in a standby state. The control signal is at the L level in the standby state and at the H level in the active state. This suppresses the effect of hot carriers in the active state and decreases a subthreshold current in the standby state.

Abstract: An interface circuit has a load, a driving circuit, and a bias circuit and outputs an output signal in accordance with an input signal between both ends of a load resistor. The driving circuit has a first MOS transistor which supplies a first constant current and a bridge circuit which supplies the first constant current to the load switchingly. The bias circuit has a fixed resistor, a second MOS transistor which is connected with the fixed resistor and which is operable with the first transistor under a Miller effect; and a differential amplifier whose non-inverting input terminal receives a predetermined voltage whose inverting input terminal receives a voltage of a connection node between the second transistor and the fixed resistor, and an output terminal which applies an output voltage at the control terminals of the first and second transistor.

Abstract: A CMOS buffer circuit for preventing a short circuit current of an output buffer transistor that drives a load including a pre-driving stage, formed of even-numbered inverters connected in series, and the respective inverters are preferably designed to exponentially increase the driving capability; an output buffer driving stage, including a pull-up PMOS driving stage, which outputs a first signal, in response to an output signal of the pre-driving stage and an output signal of the pull-down NMOS driving stage and a pull-down NMOS driving stage, which outputs a second signal, in response to an output signal of the pre-driving stage and an output signal of the pull-up PMOS driving stage; and an output stage, an inverter formed of the pull-up PMOS transistor driven by the first signal and a pull-down NMOS transistor driven by the second signal, which drives a load connected to an output of the inverter.

Abstract: An article of manufacture describes and simulates a logic device that detects the all-zero scenario for an n-bit word. The n-bit word has a selected bit that is defined using a high-inactive convention, and (n−1) non-selected bits that are defined using a high-active convention. The article of manufacture is embodied as a computer useable medium configured to store computer program codes that describe and simulate the logic device. The logic device described by the computer program codes includes an output FET, a pre-charging circuit, a first evaluation circuit, and (n−1) second evaluation circuits. The pre-charging circuit charges the output FET gate, drain, and source to a pre-charge voltage during a low clock cycle. During a high clock cycle, the first evaluation circuit evaluates the selected bit and discharges the pre-charge voltage on the output FET source if the selected bit is a voltage high.

Abstract: The present invention provides a bidirectional bus repeater controller comprising: a bidirectional bus line for bidirectional transmissions of signals; at least a bidirectional repeater on the bidirectional bus line for controlling bidirectional transmissions of signals on the bidirectional bus line; at least a bus driver connected to the bidirectional bus line for transmitting inputted signals to the bidirectional bus line in accordance with a bus driver control signal; at least a bus receiver connected to the bidirectional bus line for receiving signals from the bidirectional bus line; and a logic circuit extending along the bidirectional bus line and being connected to the at least bidirectional repeater for transmitting bidirectional bus repeater control signals to the at least bidirectional repeater upon input of the bus driver control signal.

Abstract: The present invention is a dynamic logic propagation delay targeting tool that includes a gate target delay initializer 90, a levelizer 82, a backward logic scanner 94, a forward logic scanner 96, a gate target delay incrementor 97, and a gate target delay comparator 97 that together calculates the propagation delay of a signal in a specified block of dynamic logic.

Abstract: A logic circuit performs a predetermined logic operation by supplying charge to an external load or pulling out charge therefrom according to a combination of the states of a plurality of externally inputted binary signals. The logic circuit includes a first transistor for supplying charge through an output terminal to the external load and a second transistor for pulling out the charge from the load through the output terminal. One of the first and second transistors is constituted by a MOS field-effect transistor having a drain connected to the output terminal. The MOS field-effect transistor has a source receiving an inverse signal inverse to a signal combined for logic operation with an input signal inputted to a gate of the MOS field-effect transistor. The number of the series transistors is reduced, resulting in an increase of the current capacity and in a reduction of the layout area.

Abstract: A switching circuit device has a first FET and a second FET, and operates with single control terminal. The device also has a common input terminal connected to the drain or source electrode of the two FETs, a first output terminal and a second output terminal connected to the source or the drain electrode of the respective FET, a bias element applying an bias to the first output terminal, a first connection connecting the control terminal to the second FET, a second connection connecting the gate of the second FET to the ground, and a direct current isolation element placed between the two FETs.

Abstract: An improved sense amplifier ad method for sensing signals in a silicon-on-insulator (SOI) integrated circuit improve the performance of semiconductor memories and other circuits implemented in SOI technology. The bodies of amplifier transistors within the sense amplifier and bodies of input transistors to the sense amplifier are coupled to corresponding input signals, eliminating the history dependance that would result from unconnected bodies, while achieving faster switching times due to a dynamically produced difference in threshold voltage of the input transistors and amplifier transistors. The switching time is improved over circuits using input transistors and amplifier transistors having statically biased bodies.

Abstract: In order to produce a logic circuit excellent in circuit characteristics which are area, delay time and power consumption by combining pass transistor logic circuits and CMOS logic circuits, a binary decision diagram is created from a Boolean function, and respective nodes of the diagram are mapped into 2-input, 1-output, 1-control input pass transistor selectors to synthesize a pass transistor logic circuit. In the pass transistor logic circuit, a pass transistor selector operating as a NAND or NOR logic with any one of its two inputs excluding the control input being fixed to a logical constant “1” or “0” is replaced with a CMOS gate operating as a NAND or NOR logic logically equivalent to the pass transistor selector if the value of a predetermined circuit characteristic obtained by the replacement is closer to an optimal value (if the resulting logic circuit is smaller in area, delay time or power consumption than the original pass transistor logic circuit).

Abstract: A semiconductor integrated circuit includes a first transistor of a first conductivity-type having a source connected to a first source line and a drain; a second transistor of a second conductivity-type having a source connected to a second source line and a drain; and a plurality of third transistors of the second conductivity-type connected in series between the drain of the first transistor and the drain of said second transistor, each of said third transistors having a gate for receiving an input signal. The second transistor and at least one and not all of the third transistors have a threshold voltage lower than a threshold voltage of the others of the third transistors.

Abstract: A logic circuit (200) having a critical path input signal (C2) that can have a reduced input capacitance and a logic output (D2) that can have a reduced voltage swing is disclosed. According to one embodiment, the logic circuit may include an input circuit (210), a driver circuit (220), and a load circuit (230). Driver circuit (220) can include stacked transistors (N4 and N5) of the same conductivity type, which can generate a logic output (D2) that can have a reduced voltage swing. Driver circuit (220) can generate a feedback signal that can control the impedance of a load circuit (230). Load circuit (230) can be actively controlled to improve the response of a logic evaluation node (V2).

Abstract: A dynamic logic system is disclosed that uses transmission gates coupled between the inputs and output of inverting CMOS logic gates creating a “vented” CMOS logic gate (VCMOS). A clock is used to turn the transmission gates on during a pre-charge or “vent” cycle which causes the inputs and output of the VCMOS to go to an intermediate or vented state between a logic one and a logic zero. During an evaluation phase, inputs are applied to the VCMOS gate which will evaluate to a logic one or zero depending on the states of the inputs and the logic of the VCMOS gate. A family of vented CMOS gates are constructed by adding transmission gates in series with inputs or outputs to create input VCMOS (IVCMOS) and output VCMOS (OVCMOS) which are used to construct vented dynamic logic blocks (VDLB). A VDLB comprises groups of VCMOS gates which may be vented and isolated from other gates during venting.

Abstract: An enhanced 2.5V LVDS driver with 1.8V technology for 1.25 GHz provides high speed performance for off chip drivers. Level shifting is accomplished in predriver circuits with buffer amplifier circuits operating at the on chip operating voltage level driving differential amplifiers operating at the higher driver circuit operating voltage level. An enhancement circuit is interposed between the level shifting circuits and the output stage, and this enhancement circuit speeds up the switching times of the signals input to the output stage. The enhancement circuit comprises first and second complementary transistors connected in cascode between the higher driver circuit operating voltage and a third transistor connected between the node of a predriver circuit and the higher supply voltage. The gate of the third transistor is connected to a common node between the first and second transistors.

Abstract: A new self clocking family of dynamic logic gates which replace footless or subsequent stage dynamic logic gates in multi-stage domino logic circuits. In a preferred embodiment, a multi-stage logic circuit is designed having a first stage which utilizes a traditional dynamic logic gate and a second stage which includes a new self-clocking dynamic logic gate. The output from the first stage is coupled to the input of the second stage such that the second stage is not dependent upon any type of clock signal for precharging. Instead, the second stage includes a dual transistor arrangement on the inter-stage inputs (i.e. the outputs from one stage which are input to subsequent stages) in order to precharge the output node at the second stage such that no type of clock signal is needed during precharge. Accordingly, the output from the second stage is efficiently precharged without using a delayed clock signal or any customized delay circuitry while minimizing through current by design.

Abstract: A ratio logic gate has a current mirror controlled by the pull-down transistors and supplying a half size pull-down transistor. When one or more of the input pull-down transistors is on, the mirror current overcomes the output pull-down transistor to provide a high potential output. Process tolerances between p and n type devices is thus avoided.

Abstract: This application proposes a new logic circuit including the 1st selector (S1) in which the control input S is controlled by the first input signal (IN1), the input I1 or I0 is controlled by the second input signal (IN2), and the output O is connected to the first node (N1), and the 3rd selector (S3) in which the control input S is controlled by the first node (N1), the input I1 is controlled by the third input signal (IN3), the input I0 is controlled by the first input signal (IN1), and the output is connected to the first output signal (OUT1).

Abstract: A programmable logic array (PLA) includes at least one AND plane including an array of transistors arranged in rows and columns. The transistors belonging to a same column may be connected in series with each other. Two end conduction terminals of the series connected transistors may be coupled to a supply voltage rail and to a reference, respectively. The transistors of the first and last rows of the array may have their control terminals coupled to respective opposite enabling/disabling potentials. Except for the first and last rows, first, second, and third control lines are associated with each row of the array. Except for the first and last rows, each transistor of each row may have its control terminal connected to one of the three control lines associated with its row. The PLA may alternatively include at least one OR plane.

Abstract: A method which allows for a more efficient pre-emphasis of a high frequency inter-chip signal. The method uses a single predriver stage to equalize a signal when a transition in value of a digital signal is detected. The method equalizes the signal with decreased power and area requirements for greater efficiency.

Abstract: A method and a device for maintaining logic state stored in a storage device are described. For one embodiment, the device precharges at least two complimentary nodes in a storage device during the precharge cycle. During the evaluation cycle, the device receives an input data. After receipt of the input data, device stores at least one logic state at a storage node according to the input data. The device includes at least one conducting path to limit one store per each evaluation stage.

Abstract: For the relation between the first and second pass-transistor circuits (PT1, PT2), the output signal of the preceding-stage is supplied to the gate of the succeeding-stage, and for the relation between the second and third pass-transistor circuits (PT2, PT3), the output signal of the preceding-stage is supplied to the source-drain path of the succeeding-stage. The first pass-transistor circuit (PT1) receives on its first input node (In1) and second input node (In2) the first input signal and the second input signal that are logically independent from each other. This logic circuit requires a smaller number of transistors and is capable of reducing the power consumption and delay and accomplishing an intricate logic function.

Abstract: A method for reducing static power dissipation in a semiconductor device is provided. The method is characterized in that utilizing a simple control device connecting with a MOS device, serving for a drain voltage controller, instead of the conventional voltage supply directly connected with the drain. The control device comprises two input terminals and an output terminal. One of the two input terminals is connected with a voltage supply, the other of the two input terminals is connected with a control signal. The output terminal of the control device is connected to the drain of the MOS device. When the control signal is activated, the output terminal of the control device is grounded and thus the drain is grounded. Thereby, all of the possible leakage paths induced by the drain voltage are inhibited. While the control signal is un-activated, the output terminal of the control device provides a supply voltage to the drain.

Abstract: Disclosed is a semiconductor integrated circuit device constructed of MOSFETs in which there is attained a harmony between increase in consumption power due to a leakage current and operating speed of the MOSFETs in a suitable manner, and among a plurality of signal paths in the semiconductor integrated circuit device, a path which has a margin in delay is constructed with MOSFETs each with a high threshold voltage, while a path which has no margin in delay is constructed with MOSFETs each with a low threshold voltage which has a large leakage current but a high operating speed, in light of a delay with which a signal is transmitted along a signal path.