Abstract: A system and method that use a first clock to digitally generate a second clock, wherein the ratio of the frequency of the first clock to the frequency of the second clock is a non-integer. Circuitry may be used to ensure that the first clock, or input clock, has a frequency at least equal to the highest of the desired output frequencies. The input clock may be used to generate several output clocks with different frequencies. If one of the output clocks has the same frequency as the input clock, the circuitry can be bypassed. The different clocks may be used to drive parts of a system, each of which may require a different frequency.

Abstract: Data from the orthogonal data generator is quantized by the vector data converter to become, for example, a binary value of 0 and a real number in magnitude. The output of the vector converter is modulated by the modulator, and is inputted to the amplifier. In the amplifier, the envelope of the signal to be inputted is quantized. That is, the signal of a constant envelope becomes a signal which is turned ON and OFF, so that a highly efficient nonlinear amplifier can be used. The filter removes the quantization noise generated in the vector data converter and then the signal of a low distortion and a low noise is outputted from the output terminal. The isolation unit is connected between the amplifier and the filter, avoiding effects on the output impedance of the amplifier from the filter, so that a signal of a low distortion can be outputted.

Abstract: A method and apparatus provides for the generation and recovery of a stable clock signal having harmonic emission suppressions using dual spread spectrum clock signals. The transmission frequencies of non-mixed, spread spectrum lower frequency clock signals may be varied and, upon receipt of these non-mixed signals, they are mixed into sum and difference signals. The sum signal thus generated is representative of the desired clock signal to be recovered. Such conditioning of the non-mixed signals need only occur within the receiver, thereby allow the channel that transmits the non-mixed lower frequency clock signals to the receiver to be lower bandwidth than would be required to carry the final, recovered, and higher frequency clock signal produced by the receiver.

Abstract: The present invention is to provide a method and circuit for producing spread spectrum and over clock, which includes a primary circuit and a secondary circuit, wherein the primary circuit uses a frequency division technique based on phase swallow to achieve a high frequency resolution clock signal, and the secondary circuit multiplies the frequency of the output clock signal of the primary circuit, so as to expand its frequency range.

Abstract: A wireless communication device is described having a transmitter that generates electromagnetic interference when operating in a transmit mode. The wireleess communication device comprises a clock circuit including a first clock element configured to generate a first clock output, and a second clock element configured to generat a second clock output. Also included is a controller configured to switch between the first clock output and the second clock output when the transmitter is operating in the transmit mode.

Abstract: An object is to provide a clock supply circuit capable of supplying a clock signal with a short oscillation stabilization waiting time. There is provided a clock supply circuit having a filter removing from a first clock signal pulses having a shorter pulse width than a threshold value and passing pulses having a longer pulse width than the threshold value to thereby output a second clock signal; and a divider dividing the second clock signal to thereby output a third clock signal.

Abstract: A circuit includes a clock generator to provide a clock signal, and a clock distribution circuit coupled to the clock generator and a plurality of pairs of outputs. The clock distribution circuit includes a plurality of adjustment circuits to generate a plurality of pairs of clock signals in accordance with the clock signal. A respective adjustment circuit in the plurality of adjustment circuits is to provide a respective pair of clock signals in the plurality of pairs of clock signals to a respective pair of outputs in the plurality of pairs of outputs. The respective pair of clock signals includes a first clock signal and a second clock signal. The first clock signal is a complement of the second clock signal and duty-cycle and skew errors in the first clock signal and the second clock signal are less than corresponding pre-determined values.

Abstract: A clock and data distribution network is proposed that distributes clock and data signals without buffers, thus achieving very low jitter, skew, loose timing requirements, and energy consumption. Such network uses resonant drivers and is generally applicable to architectures for programmable logic devices (PLDs) such as field programmable gate arrays (FPGAs), as well as other semiconductor devices with multiple clock networks operating at various clock frequencies, and high-performance and low-power clocking requirements such as microprocessors, applications specific integrated circuits (ASICs), and Systems-on-a-Chip (SOCs).

Abstract: Disclosed is a novel design of a fully integrated UWB transmitter. The transmitter includes a pulse generator, a pulse modulator, and an ultra-wideband drive amplifier. A new low voltage low power pulse generator circuit is disclosed which can be fully integrated in CMOS or BiCMOS process. This circuit includes a squaring stage, an exponential stage, and a second-order derivative stage. Based on this, PPM, BPSK and PAM pulse modulator circuits and system are disclosed. The modulated pulse is symmetrical second-order derivative Gaussian pulses with a bandwidth up to 5 GHz and having sufficient swing for UWB applications. An ultra-wideband driver amplifier is proposed to amplify the modulator output and drive the antenna. For the driver amplifier, common source resistor and inductor shunt feedback with current reuse technique is employed to achieve the ultra-wideband bandwidth, high gain, and providing matching for the antenna simultaneously.

Abstract: A clock distribution network, structure, and method for providing balanced loading is disclosed. In particular, a clock distribution network may be formed of one or more clock fanout distribution levels. Each respective distribution level may include an equal number of buffer circuits and wiring routes that have substantially identical physical and electrical properties. Additionally, a final distribution level may include wiring routes that have substantially identical physical and electrical properties connecting buffer circuits to one or more logic leaf connection nodes.

Abstract: A semiconductor device transfers first data to a circuit block. The semiconductor device is provided with a storage circuit configured to store the first data, a shift register configured to set the first data, a transfer circuit configured to transfer the first data from the shift register to the circuit block, a first input terminal configured to receive a first signal indicating the end of a transfer operation, a resetting signal-generating circuit configured to generate a resetting signal for resetting the shift register based on the first signal, a setting signal-generating circuit configured to generate a setting signal for setting the first data in the shift register again after the shift register is reset, and an output circuit configured to externally output the first data that has been set again.

Abstract: A data clock control apparatus includes a bias voltage generator configured to receive a plurality of test mode signals and a plurality of fuse signals and to generate a bias voltage to secure a predetermined potential difference from an external driving power supply, and a clock signal controller configured to receive the bias voltage and to buffer an external clock signal and outputs a data output clock signal.

Abstract: A high power electric pulse generator includes a charge storage device, a high voltage source for charging the charge storage device, a first photoconductor element connected to the reference potential and to the storage device, a second photoconductor element connected to the storage device and to a useful load, a first light source for delivering a pulse of light to the first photoconductor, a second light source for delivering a pulse of light to the second photoconductor and a synchronization device for synchronizing the emission delay between the first light source and the second light source. The first photoconductor and the second photoconductor are passive semiconductor elements with a linear regime forming photosensitive switches, with the first and second photoconductors being doped silicon photoconductors.

Abstract: A flip-flop includes a functional latch and a retention latch. The functional latch is configured to maintain a logic state of the flip-flop in a power-up mode and the retention latch is configured to maintain the logic state of the flip-flop in a power-down mode. The retention latch is selectively coupled to the functional latch and the retention latch is configured to maintain the logic state in the power-down mode irrespective of a level of an associated clock signal when the power-down mode is entered. A clock pulse that clocks the flip-flop is derived from the associated clock signal.

Abstract: A synchronization circuit includes a first level-shifting unit receiving an input reference signal having a first swing voltage and generating a first level change signal having a second swing voltage and a second level change signal having a third swing voltage, and a synchronization unit generating first and second output signals by synchronizing the first level change signal with the second level change signal.

Abstract: A frequency generator apparatus and a control circuit thereof are provided. The frequency generator apparatus comprises the control circuit and a frequency generator, wherein the control circuit contains an electric fuse (efuse). The control circuit outputs an enabling signal according to the state of the efuse. The frequency generator is coupled to the control circuit, receives the enabling signal, and decides to output a frequency signal or not according to the enabling signal.

Abstract: There is provided a signal generation circuit for generating an output signal including jitter injected thereto. The signal generation circuit includes a jitter output section that outputs a first jitter signal and a second jitter signal which have different frequencies from each other, a carrier output section that outputs a carrier signal having a frequency positioned in substantially the middle between the frequencies of the first and second jitter signals, and an adding section that adds together the first jitter signal, second jitter signal and carrier signal so as to generate the output signal.

Abstract: A pulse-width control loop (PWCL) for clock with any pulse-width ratio within a wide range is provided. A differential programmable charge pump is employed to stabilize the current source by complementary connection. The differential programmable charge pump has a pair of differential charge pumps and a current source module to adjust the ratio of charge to discharge, so as to accelerate the range of the adjustable pulse-width ratio of the output clock and increase the output resolution. Further, a ratioless input control stage is employed to simplify the circuit design and avoid static power consumption. Moreover, the control stage adjusts rising pulse width and dropping pulse width at one period, thereby accelerating the lock speed and the range of the adjustable pulse-width ratio (i.e., duty cycle) of the input clock.

Abstract: A transmitter has a peak reducing part carrying out peak reduction processing; an OFDM signal generating part generating an OFDM signal from an input information signal; a cyclic shifting part generating a signal obtained from cyclically shifting the OFDM signal; and an adding part adding the OFDM signal and the cyclically shifted signal together.

Abstract: A power consumption reduction circuit for reducing power consumed by a clock tree network including a transmission control circuit. The power consumption reduction circuit includes a transmission control circuit for controlling transmission of the clock signal to the buffer circuit group so as to selectively provide and interrupt the clock signal. A switch circuit disconnects the buffer circuit group from a power supply when the transmission control circuit interrupts the clock signal.

Abstract: Spurious noise that occurs in the vicinity of a carrier can be removed even when a high-resolution cycle is set, thereby realizing low jitters in a high-precision variable clock signal. Cycle data that is set by a pattern generator 10 in a waveform generation apparatus (a semiconductor test apparatus) 1 is corrected in such a manner that spurious noise that occurs in a carrier of a high-precision variable clock is produced at a position far from the carrier. As a result, the spurious noise can be assuredly removed by a PLL 50, thereby realizing low jitters in the high-precision variable clock signal.

Abstract: There is provided an electric circuit that outputs a timing signal and a recovered clock.

Abstract: A synchronous clock generation apparatus including a multiplier for multiplying a horizontal synchronizing signal by a horizontal synchronizing pulse signal to generate multiplication data, a gain variable digital LPF for extracting only DC components from the multiplication data and capable of performing gain adjustment, and a controller for calculating gain adjustment data, lock center frequency setting data, and LPF gain adjustment data based on the correction data. The controller detects an amount of deviation from the lock center frequency and an amount of variation, displaces the lock center frequency and shifts the lock range along the frequency axis to enlarge the apparent lock range when the amount of deviation is large, and reduces the gain to improve lock precision when the amount of variation is small, without expanding bits in the circuit configuration.

Abstract: A system for providing signal trigger pulses comprises an equivalent time sampling unit providing transmit and receive trigger pairs, and a control unit controlling the equivalent time sampling unit to provide pseudorandom delay length variations between the trigger pairs.

Abstract: Disclosed is a clock generation circuit for generating a clock-out signal that has a fixed latency with respect to a clock-input signal. When multiple such clock generation circuits are utilized to feed clock signals to different digital logic circuits within an integrated circuit structure, differences in delay time, referred to as skew, are minimized. An embodiment of the clock generation circuit incorporates a waveform generator and a timing-improved deskewer. The waveform generator is clocked by a clock-in signal. The deskewer comprises a flip-flop, a level-sensitive latch, and a multiplexer. The flip-flop and latch are connected in parallel and each receives waveform signals from the waveform generator as well as the clock-in signal in order to generate output signals. The multiplexer gates the flip-flop and latch output signals with the clock-in signal in order to generate the clock-out signal. A testable deskewer for edge-sensitive multiplexer scan designs is also disclosed.

Abstract: Systems and methods are disclosed herein to provide improved clock, delay, and skew techniques. For example, in accordance with an embodiment of the present invention, an integrated circuit includes a clock generator to provide a bias signal and a clock signal, with control logic providing a delay control signal based on the bias signal and the control signal. A delay circuit provides a delay to the clock signal based on the delay control signal.

Abstract: A pulse width modulation circuit 1 of the present invention changes the voltage of a first integration circuit C1 during the first period T1 of the clock signal MCLK based on a current based on an audio signal eS, changes the voltage of the first integration circuit C1 based on a constant bias current in the opposite direction while changing the voltage of a second integration circuit C2 during the second period T2, and changes the voltage of the second integration circuit C2 based on the bias current during the third period T3. The amount of time from the start of the second period T2 until the voltage of the first integration circuit C1 reaches the reference voltage Vth is detected, and the amount of time from the start of the third period T3 until the voltage of the second integration circuit C2 reaches the reference voltage Vth is detected.

Abstract: In at least some embodiments, a method comprises receiving an external card detection signal that indicates that a hot-pluggable card is coupled to a computer system and activating at least one reference clock signal of a scalable reference clock platform based on the external card detection signal. The method further comprises synchronizing clock signals embedded in data packets transmitted between the hot-pluggable card and the computer system with another clock signal bases on the at least one reference clock signal.

Abstract: Provided is a multi-phase clock generator which is not influenced by a mismatch and of which a maximum frequency is not limited. The multi-phase clock generator includes a first delay line, a second delay line, a phase detector, and an up/down counter. The first delay line generates a first clock signal by delaying an input clock for a first delay time. The second delay line generates a second clock signal by delaying the input clock for a second delay time in response to a control signal. The phase detector detects a phase difference between the first and second clock signals. The up/down counter generates the control signal in response to an output of the phase detector.

Abstract: A semiconductor circuit for an inverter device, comprising a pulse generator for generating a pulse signal upon receiving the input signal for controlling the high-voltage switching device of the inverter device, a driver circuit for driving the high-voltage switching device, and a signal transfer circuit for transferring the pulse signal generated by the pulse generator to the driver circuit, wherein a wide band-gap semiconductor device is used in the signal transfer circuit

Abstract: A clock distribution circuit having plural stages of buffers disposed along branch paths for dividing up a clock signal and configured in a manner that outputs of a plurality of buffers in a final stage and/or a middle stage are short-circuited, includes in relation to at least one buffer of a plurality of buffers in the same stage on a branch path, a selector for receiving an output of an adjacent buffer located upstream in terms of chain-connection along which the plurality of buffers are connected in testing, and a signal at a branch node corresponding to the at least one buffer by a first input and a second input respectively, selecting one of the first input and the second input based on a select control signal, and supplying the selected input to the one buffer.

Abstract: A DC-to-DC converter comprises a converter section and a controller section. The converter section comprises a primary section and a secondary section. The primary and secondary section includes MOSFET switches. The controller section is coupled to the converter section and comprises a pulse width modulation (PWM) section and a delay section. The PWM section comprises an error amplifier configured to generate an error signal representative of a variance between an output voltage of the converter section and a reference voltage and a PWM configured to produce a PWM signal based on the error signal. The delay section comprises of delay circuits configured to generate delayed output signals from the PWM signal and power switching device drivers coupled to the delay circuits and configured to receive the delay output signals and generate a controlled signals to control the on/off state of the MOSFET switches.

Abstract: An integrated circuit for generating a clock signal includes a voltage conversion unit, a maximum power determination unit, a clock control unit and a clock generator. The voltage conversion unit converts an external power supply voltage into an internal power supply voltage and detects a variance in current consumption of a functional block to generate a detected voltage wherein the functional block consumes a predetermined current using the internal power supply voltage. The maximum power determination unit determines a maximum current consumption of the functional block and converts the maximum current consumption to a corresponding maximum allowed voltage. The clock control unit generates at least one frequency control signal based on a comparison between the detected voltage and the maximum allowed voltage. The clock generator generates the clock signal whose frequency is adjusted according to the frequency control signal.

Abstract: A monolithic sensor arrangement includes a housing, a sensor integrated in the housing, and two or three connecting contacts deployed on the housing so as to provide a contact with the sensor. The housing also includes an integrated digital circuit includes a freely programmable digital processor, a program memory and a data memory, which are used to control and/or process the functionalities and/or the measured data of the sensor.

Abstract: A pulse generating circuit includes a plurality of delay elements cascaded so as to constitute a predetermined loop, wherein when a predetermined input pulse is supplied to a leading end of the series connection, an effective frequency multiplication is applied to signals which appear at a plurality of portions out of the node portions among the plurality of delay elements and the terminal end portion of the series connection by a logical circuit to obtain an output pulse having a higher frequency than the input pulse.

Abstract: The disclosure is directed to an internal pulse generator outputting a signal with a constant pulse width nevertheless of a frequency of an input signal, including a first PMOS transistor, a PMOS second transistor and an NMOS transistor which are connected between a power supply voltage and a ground voltage in series, a latch and an inverter which are connected between an output terminal and a first node as a drain of the NMOS transistor, and a Y-time delay circuit connected between the output terminal and a second node that is a common gate of the PMOS and NMOS transistors.

Abstract: An implementation of an apparatus and method to generate a dynamically controlled clock is provided. The resulting clock reduces otherwise produced narrow clock pulses and allows for control from two separate control signals. A first control signal indicates a low power mode, for example a chip-wide low power mode. A second control signal indicates a user-selected mode to shutdown a selected clock.

Abstract: A system and method that use a first clock to digitally generate a second clock, wherein the ratio of the frequency of the first clock to the frequency of the second clock is a non-integer. Circuitry may be used to ensure that the first clock, or input clock, has a frequency at least equal to the highest of the desired output frequencies. The input clock may be used to generate several output clocks with different frequencies. If one of the output clocks has the same frequency as the input clock, the circuitry can be bypassed. The different clocks may be used to drive parts of a system, each of which may require a different frequency.

Abstract: An object is to suppress change of a threshold voltage of a transistor in a shift register and to prevent the transistor from malfunctioning during a non-selection period. A pulse output circuit provided in the shift register regularly supplies a potential to a gate electrode of a transistor which is in a floating state so that the gate electrode is turned on during a non-selection period when a pulse is not outputted. In addition, supply of a potential to the gate electrode of the transistor is performed by turning on or off another transistor regularly.

Abstract: By adjusting a register's capturing clock edge timing so that the register captures data when the data returns to a correct state, the register may be protected against DSET upsets. If a data glitch occurs near the clock edge, the valid time at the register output is increased (CLK to Q). This valid time increase occurs when the presence of a DSET transient is detected near the clock edge.

Abstract: A pulse width modulation circuit includes a first delay-locked loop (DLL) circuit and a second DLL circuit. The first DLL is coupled to a first multiplexer and has a first set of delay stages, wherein the first DLL circuit is configured to receive an input clock signal and, through the first multiplexer, produce a first stage delay signal associated with the first set of delay stages, wherein the first stage delay signal leads the input clock signal by a first duration.

Abstract: A digital clock modulator provides a smoothly modulated clock period to reduce emitted electro-magnetic radiation (EMR). The digital clock modulator includes a plurality of delay elements connected in series and receiving as an input an unmodulated clock signal. A multiplexer receives inputs from unequally spaced taps between the delay elements. A control block provides selection inputs to the multiplexer, and receives the unmodulated clock signal from the delay elements. The delay elements include a last delay element providing the unmodulated clock signal to the control block. The last delay element has a predetermined delay for ensuring that the delay elements and related signal paths are in a same stable state before control to the multiplexer changes.

Abstract: A regenerative clock repeater comprises an edge detector and an output driver means to produce the clock signal by recovering its high logical level and low logical level. The output driver means further comprises a pull-up and a pull-down circuitry adapted to receive a pair of control signals. These control signals are generated by the edge detector to sense the rising edge and falling edge of the clock signal. Inside the edge detector, a pair of threshold level detectors detect a high and a low logical level of the clock signal and inputs the results to a combination of logic gates and a latch to keep the locations of the signal markers fixed. These fixed-location of control signals trigger the output driver means to recover the high logical level and the low logical level of said clock signal.

Abstract: A transfer pulse generator circuit for outputting a vertical register transfer pulse includes transfer pulse control means for controlling to set rise and fall timings of the vertical register transfer pulse to desired timings in a predetermined period.

Abstract: A semiconductor memory device is capable of performing a modulation of output clock signals in order to prevent EMI characteristics of a system having the semiconductor memory device from being degraded. The semiconductor memory device includes a modulation clock signal generator, a clock input unit, a first modulation unit, a delay locked loop circuit, and a second modulation unit. The modulation clock signal generator generates a modulation clock signal. The clock input unit generates a reference clock signal from a system clock signal. The first modulation unit generates a modulated clock signal by modulating the reference clock signal with the modulation clock signal. The delay locked loop circuit performs a delay locking operation on the modulated clock signal to generate a delay locked clock signal. The second modulation unit modulates the delayed locked clock signal with the modulation clock signal.

Abstract: An oscillator circuit includes a capacitance element; an inverter outputting an inverted voltage at a first terminal of the capacitance element; a voltage source including a resistor and an NMOS transistor connected in series between a first high-potential power supply and a ground power supply and outputting a voltage from a node to which the resistor and the NMOS transistor are connected; a switch circuit connecting a second terminal of the capacitance element to the voltage source or the ground power supply in accordance with the voltage output from the inverter; and a constant-current source connected to a second high-potential power supply and allowing, regardless of changes in the voltage and temperature of the second high-potential power supply within certain ranges, flow of a constant current into or out of the first terminal of the capacitance element in accordance with the voltage output from the inverter.

Abstract: A pulse circuit contains an input stage configured to receive input pulses on input nodes using push-pull elements, wherein a given push-pull element is configured to receive an input pulse on a given input node and to provide a corresponding internal signal. The pulse circuit further contains a feedback loop that includes a logic element coupled between outputs from the push-pull elements and reset nodes of the push-pull elements. This logic element is configured to provide one or more outputs from the pulse circuit and to reset the internal signals from the push-pull elements via the feedback loop.

Abstract: One delay circuit is inserted in open loop inside a clock recovery circuit for improving the accuracy of clock recovery. One oscillator signal ?(0) to ?(2i-1) is provided with a basic Step of Time. A rational number of Step of Time corresponding to a bit-duration is measured inside a received flow of bits. The oscillator signal ?(0) to j(2i-1) is transformed into a clock signal CK having active edges of said clock signal in phase with at least one oscillator signal ?(0) to ?(2i-1), two consecutive active edges being separated by a time duration proportional to the integer part of the number of Step of Time. A time delay is computed proportional to the fractional part of the number of Step of Time. The next active edge of the clock signal CK is delayed of said computed delay.

Abstract: Disclosed are methods and systems for subnanosecond rise time high voltage (HV) electric pulse delivery to biological loads. The system includes an imaging device and monitoring apparatus used for bio-photonic studies of pulse induced intracellular effects. The system further features custom fabricated microscope slide having micro-machined electrodes. A printed circuit board to interface the pulse generator to the micro-machined glass slide having the cell solution. An low-parasitic electronic setup to interface with avalanche transistor-switched pulse generation system. The pc-board and the slide are configured to match the output impedance of the pulse generator which minimizes reflection back into the pulse generator, and minimizes distortion of the pulse shape and pulse parameters. The pc-board further includes a high bandwidth voltage divider for real-time monitoring of pulses delivered to the cell solutions.

Abstract: The present invention discloses a frequency detecting apparatus for detecting a frequency of an input clock. The frequency detecting apparatus includes: a pulse generator, a digital signal generator, and a decoder. The pulse generator is coupled to the input clock for extracting a period of the input clock to generate a pulse, and the digital signal generator is coupled to the pulse generator for converting the pulse into a plurality of logic values. The digital signal generator includes: a delay module coupled to the pulse, for delaying the pulse to generate a plurality of delayed pulses according to a plurality of delay amounts, respectively; and a sampling module coupled to the delay module for sampling the pulse to generate the logic values according to the delayed pulses, respectively. The decoder is coupled to the digital signal generator for determining the frequency of the input clock according to the logic values.