Abstract: A pin setting circuit and a clock driving circuit are disclosed. The clock pin setting circuit sets the clock pin of the clock driving circuit. The pin setting circuit includes the double one-shot circuit and the switch circuit. The double one-shot circuit includes the first one-shot circuit and the second one-shot circuit. The first one-shot circuit receives a clock signal and generates a first control signal according to the frequency of the clock signal. The second circuit outputs a second control signal according to the first control signal generated. The switch circuit sets the clock pin to the power end or the ground end according to the second control signal.

Abstract: An electronic pulse-generating device (100) includes an input circuit (10) and an output circuit (20). The input circuit includes an input connector (11), a first resistor (R1) and a capacitor (12). The capacitor has one lead electronically connected to the input connector and another lead electronically connected to the first resistor. The output circuit includes a transistor (21) and an output connector (22) electronically connected to a collector of the transistor. The first resistor is connected to a base of the transistor, and an emitter of the transistor is grounded.

Abstract: Determination and processing for fractional-N programming values. The present invention is operable to receive a clock signal (CLK) and to transform that CLK into a new CLK, when necessary, for use by various circuitries within a system. The present invention is operable to generate two different CLKs for use by a radio frequency (RF) circuitry and a baseband processing circuitry in certain embodiments. The present invention employs a measurement circuitry and to characterize a first CLK and uses a fractional-N synthesizer to perform any necessary processing to generate the one or more CLKs to the other CLKs within the system. The first CLK may be received from an external source or it may be generated internally; in either case, the present invention is able to modify the CLK into another CLK for use by other circuitries within the system or for use by another external device.

Abstract: An integrated circuit device having at least one fuse capable of being blown in order to provide measurements of fuse current-voltage characteristics is provided. The integrated circuit device also provides at least one pulse generation circuit associated with the fuse and capable of generating a pulse to blow the fuse through one or more DC input signals.

Abstract: Various embodiments of the present invention provide systems, circuits and methods that allow for switching between two or more multiphase clocks. As one example, a system for switching between multiphase clocks is disclosed. The system includes a multiphase clock multiplexer. The multiphase clock multiplexer receives a first multiphase clock and a second multiphase clock. The first multiphase clock includes at least a first phase clock and a second phase clock, and the second multiphase clock includes at least a third phase clock and a fourth phase clock.

Abstract: In one embodiment, a reference generator forms a reference signal that may have temperature and process variations. A comparator that has similar variations is used to detect a signal using the reference.

Abstract: Systems and methods for active clock deskew are provided. The disclosed systems/methods advantageously achieve desirable clock deskew at reduced power levels by employing a resistance-based distributed clock deskew technique. The disclosed technique has broad commercial/industrial applicability, e.g., in VLSI/ULSI chips, such as microprocessors, digital signal processing systems (DSPs), integrated circuits, application-specific integrated circuits (ASICs), micro-controllers, embedded systems, memory chips and the like.

Abstract: A frequency multiplier increases the frequency of an external clock and outputs a high-frequency external clock. A period determinator determines whether or not a predetermined period of the external clock elapses and outputs a period determination signal. A frequency selector selectively transmits the external clock or the high-frequency external clock to a clock input buffer under the control of a power-up signal and the period determination signal.

Abstract: A phase recombination circuit includes a first phase input and a first one-shot pulse generator adapted to receive the first phase input and produce a first signal to pull a signal to a first state. The phase recombination circuit also includes a second phase input in phase relationship with the first phase input, and a second one-shot pulse generator adapted to receive the second phase input and produce a second signal to pull a signal to a second state.

Abstract: A phase splitter that receives an external clock signal and that generates first and second internal clock signals having a phase difference of 180° between the first and second internal clock signals, the phase splitter including: a first buffer that buffers the external clock signal and outputs a first signal; an inverting unit that inverts the external clock signal and outputs a second signal; a second buffer that buffers the second signal and outputs a third signal; a first interpolating signal generator that inverts the external clock signal and outputs a fourth signal; and a second interpolating signal generator that inverts the second signal and outputs a fifth signal. The first signal and the fifth signal are interpolated to generate the first internal clock signal. The third signal and the fourth signal are interpolated to generate the second internal clock signal.

Abstract: The invention is related to an apparatus and a method for generating an output clock. The method comprises: receiving a transmitted signal comprising at least one data signal and at least one synchronized signal; producing a reference signal according to the synchronization signal; counting the first reference signal according to a free-run clock outputted by a free-run clock generator to produce a counter signal; and generating the output clock according to the counter signal and the free-run clock.

Abstract: Cumulative delay contributions introduced by an input buffer and by the metal line that distributes the buffered external control signal to data transfer circuits for performing a transfer of data to and from an integrated device are reduced by having the external signal distributed unbuffered through a metal line of sufficiently large size. This introduces a negligible intrinsic propagation delay being within the specified maximum admitted input pad capacitance. The delay reduction is also based on locally dedicated input buffers for each data transfer circuit, and for applying thereto a buffered replica of the external signal present on the metal line.

Abstract: Disclosed is a clock-based data storage device, which includes a dual pulse generating device and a data starge device having two dynamic nodes for prior chargement/dischargement.

Abstract: A clock regeneration circuit includes a half-bit delay device that outputs a half-bit delayed signal B of a multi-level input signal A, a one-bit delay device that outputs a one-bit delayed signal C of the signal A, an adder, an attenuator that forms an threshold signal, an XOR circuit, and a BPF that outputs a clock signal with a frequency corresponding to a bit rate of the XOR signal. The XOR signal is calculated as an XOR of a two-level input signal F, which is a logical zero when a level of the signal A is no more than a level of the threshold signal and otherwise is a logical one, and a two-level input signal G, which is a logical zero when a level of the signal B is no more than the level of the threshold signal and otherwise is a logical one.

Abstract: A wireless communication device is described having a transmitter that generates electromagnetic interference when operating in a transmit mode. The wireless communication device comprises a clock circuit including a first clock element configured to generate a first clock output, and a second clock element configured to generate a second clock output. Also included is a controller configured to switch between the first clock output and the second clock output when the transmitter is operating in the transmit mode.

Abstract: A system and method for generating a pulse stream are disclosed. A ramp signal is generated. The ramp signal is compared with a Time of Transition signal to produce a result indicative of the comparison. Responsive to the result of the comparison, the pulse stream signal is output. The result of the comparison instructs the selector whether to maintain the current output pulse stream signal or replace the current output pulse stream signal with a Polarity signal.

Abstract: A device for generating an output clock signal intended to time a digital processing circuit, said generating device receiving a first clock signal, characterized in that it comprises an oscillator generating a second clock signal constituting said output clock signal, said oscillator functioning in a forced mode under the control of the rising and falling edges of said first clock signal, said oscillator functioning in a free mode in the absence of rising or falling edges in said first clock signal, the natural frequency of said oscillator being lower than the frequency of said first clock signal.

Abstract: The invention proposes a fully automated, computer-aided intervention apparatus (80) with an operational stabilization apparatus (10) and an appropriate method for operational apparatuses (41), where appropriate intervention means (40) are activated by means of an activation apparatus (203) if an intervention event detected by means of at least one pickup apparatus (401) is picked up. The intervention means (40) may comprise, in particular, automated alarm, monitoring and/or control apparatuses.

Abstract: A frequency adjusting circuit for a central processing unit (CPU) includes a transforming unit for transforming a change of a current signal of the CPU into a voltage signal, an amplifying unit for amplifying the voltage signal from the transforming unit, a switching unit being turned on or turned off by the amplified voltage signal from the amplifying unit, and a basic input/output chip for regulating a frequency of the CPU through a clock generator.

Abstract: A glitch-free clock switching circuit receives a first clock signal and a second clock signal and outputs a third clock signal corresponding to the first clock signal or a fourth clock signal corresponding to the second clock signal according to a clock switching signal. The glitch-free clock switching circuit switches to output clock signals by stopping output of a clock signal, and then waiting for a predetermined period of time before outputting another clock signal.

Abstract: An oscillator utilizes two current sources that have the same temperature and VDD dependency so they generate the same current in changing conditions. Therefore, there is very low VT dependency. The resistor and fringe capacitor temperature coefficient are very low and opposite so they compensate for each other. A comparator with a short period of operation also minimizes VT dependency.

Abstract: An apparatus and method for generating local clock signals from system clock signals based upon user inputs that provide a frequency multiplier and a frequency divider. The frequency multiplier and frequency divider are stored in an interface. System clock signals are received and local clock signals are generated by the circuitry. The frequency of the local clock signals is equal to the frequency of the system clock signals multiplied by the frequency multiplier and divided by the frequency divider multiplied by two.

Abstract: A circuit comprising: clock circuitry for supplying a first faster clock signal to a first circuit portion and a second slower clock signal to a second circuit portion, and varying the relative frequency of the first and second clock signals. Synchronisation logic generates pulses which indicate when to transfer data between the first and second circuit portions. The clock circuitry generates a first control signal at a predetermined time in each cycle of the first clock signal prior to a predetermined edge, and a second control signal at a predetermined time in each cycle of the second clock signal prior to a predetermined edge. A change in the relative frequency is conditional on a coincidence of the first and second control signals. The synchronisation generates the pulses such that there is at least one cycle of the first clock signal between those pulses, and such that there is only one of those pulses per cycle of the second clock signal.

Abstract: The internal read signal generator according to the present invention includes: a first delay unit for delaying a clock signal in order to obtain a margin of a setup/hold time of an input signal; a signal transfer unit for transferring the input signal in synchronization with the delayed clock signal of the first delay unit; a second delay unit for delaying an output signal of the signal transfer unit; and an output unit for combining the input signal and an output signal of the second delay unit, wherein an amount of the delay of the second delay unit is determined in order that a rising edge of an output signal of the output unit has a period of the clock signal.

Abstract: Exemplary embodiments of the invention provide a reference signal generator, system and method. An exemplary apparatus to generate a harmonic reference signal includes a reference resonator, such as an LC-tank, a control voltage generator adapted to provide a temperature-dependent control voltage; and a plurality of variable reactance modules. The reference resonator generates a first reference signal having a resonant frequency, and each reactance module is adapted to modify a corresponding reactance in response to the control voltage to maintain the resonant frequency substantially constant or within a predetermined variance over a predetermined temperature range. A frequency controller may also be included to maintain substantially constant a magnitude of a peak amplitude of the first reference signal and maintains substantially constant a common mode voltage level of the reference resonator.

Abstract: An apparatus including a first circuit, a second circuit and a third circuit. The first circuit may be configured to (a) receive (i) a plurality of input signals and (ii) a clock signal and (b) present (i) a plurality of low-swing differential signals and (ii) a full-swing differential signal. The second circuit may be configured to (a) receive (i) the plurality of low-swing differential signals, (ii) the full-swing differential signal and (iii) the clock signal and (b) present a plurality of output signals. The third circuit may be configured to communicate the plurality of low-swing differential signals and the full-swing differential signal from the first circuit to the second circuit. The third circuit may be further configured to generate a local clock in response to the full-swing differential signal.

Abstract: Clocks are distributed efficiently to regions of a specialized processing block in a PLD. Multiple clocks are selected from a larger universe of clocks and distributed to the specialized processing block, but the choices of clocks at the individual functional regions, or stages of functional regions, are less than fully flexible. In some cases, an entire region may use one clock. In another case, portions of a stage within a region that previously had been able to select individual clocks must use one clock for the entire stage. In another case, only a subset of the selected clocks is available for a particular region, but that subset is flexibly distributable within the region. In another case, a clock may be selectable for each stage of each functional region directly from the larger universe of available clocks, avoiding the need for circuitry to select the multiple clocks from the larger universe.

Abstract: A clock generator generates multiple clock signals based on an input signal and adjusts the phases of the clock signals relative to a phase of the input signal, based on a control signal. The clock generator includes a phase locked loop that includes a phase shift unit. The phase shift unit selects some of the clock signals based on the control signal and generates a feedback signal based on the selected clock signals. The feedback signal has a phase based on the phases of the selected clock signals. The phase locked loop aligns the phase of the feedback signal with the phase of the input signal. In this process, the phase locked loop shifts the phase of each of the clock signals relative to the phase of the input signal.

Abstract: A phase interpolator receives an input clock signal and varies the phase of an output clock signal in accordance with a phase control signal.

Abstract: A jitter generator for generating a jittered clock signal, includes a jitter control signal generator and a jittered clock generator. The jitter control signal generator is utilized for selecting a digital control code from a plurality of candidate digital control codes at individual time points and respectively outputting a plurality of selected digital control codes. The jittered clock generator is coupled to the jitter control signal generator, and utilized for generating the jittered clock signal. The jittered clock generator dynamically adjusts the jittered clock signal according to the plurality of different digital control codes.

Abstract: A method signals in an ultra-wide bandwidth network. A data symbol is generated. A set of reference pulses is transmitted for the data symbol. Each reference pulse is of a different type. One data pulse is also transmitted for each reference pulse. A type of each data pulse is identical to the type of the corresponding reference pulse.

Abstract: An electronic system includes a charge pump driver for generating an output to control an electronic element. The electronic system further includes a clock generator coupled to the charge pump driver. The clock generator can generate a clock signal to control the charge pump driver and adjust a frequency of the clock signal according to a status of the electronic element.

Abstract: There is provided a small-size, low-power-consumption intermittent operation circuit capable of obtaining an output waveform having a rapid rise and fall. The intermittent operation circuit includes an active circuit (106), a first control signal generation circuit (101) for generating a first control signal (S1) for controlling the operation start and the operation end of the active circuit (106), a second control signal generation circuit (102) for generating a second control signal (S2) causing the active circuit (106) to perform ringing vibration and controlling the frequency and the amplitude value of the ringing vibration, and a timing adjusting circuit (103) for adjusting the input timing of the first and the second control signal (S1, S2) into the active circuit (106) so that the ringing vibration and the safety vibration are outputted continuously from the active circuit (106).

Abstract: A threshold voltage of a transistor is fluctuated because of fluctuation in film thickness of a gate insulating film or in gate length and gate width caused by differences of used substrates or manufacturing steps. In order to solve the problem, according to the present invention, there is provided a clocked inverter including a first transistor and a second transistor connected in series, and a compensation circuit including a third transistor and a fourth transistor connected in series.

Abstract: A clock manager circuit includes a number of clock output blocks, each providing an independent output. Counter controlled delay devices (CCDs) are used in these clock output blocks. To achieve full cycle delays, the CCDs are placed in parallel with outputs of the CCD outputs driving set and reset terminals of a common latch. The parallel connection of the CCDs, as opposed to a series connection, offers an increase in maximum frequency and possibly fewer needed CCDs than if the CCDs are placed in series. In one embodiment, at least one of the CCDs includes a counter/compare circuit with a frequency divider enabling the frequency of the CCD to be varied relative to the common input clock.

Abstract: An Externally Asynchronous-Internally Clocked (EAIC) system that generates an internal clock signal includes a clock signal control block. The clock signal control block includes a pull-up unit that is activated in response to an input signal used to generate an internal clock signal; a pull-down unit that is activated in response to the input signal used to generate an internal clock signal, and a bypass unit that is provided between the pull-up unit and the pull-down unit, and selectively provides a signal path to the pull-down unit if the pull-down unit is activated and a signal path from the pull-up unit if the pull-up unit is activated.

Abstract: A semiconductor integrated circuit device includes a semiconductor substrate having a first area. A first counter is provided in the first area, cyclically counts and outputs a first counter signal as a result of counting. A global reset circuit is provided on the semiconductor substrate and outputs a global reset signal. A first local reset circuit is provided in the first area and outputs a first local reset signal upon receiving the first counter signal of a set value after supplied with the global reset signal. A first circuit is provided in the first area and supplied with the first local reset signal.

Abstract: A clock driver is provided. A first driving unit is configured with a plurality of drivers and receives a first clock signal to drive a first pumping clock. A second driving unit is configured with a plurality of drivers and receives a second clock signal to drive a second pumping clock. A charge recycling switch is connected between an output terminal of the first driving unit and an output terminal of the second driving unit. A switch controller selectively transfers an input clock signal of the first or second driving unit to the charge recycling switch in response to the first and second pumping clock signals.

Abstract: A ternary pulse generation circuit includes a logic circuit section including three logic elements and a switching control section including three switching elements each controlled by an output of corresponding one of the three logic elements, and the circuit outputs three different voltage values in a switching manner by controlling the three switching elements such that the three switching elements are not turned on simultaneously.

Abstract: A clock signal generating circuit is provided. The clock signal generating circuit includes a clock signal generator for generating a first clock signal having a predetermined frequency; a frequency dividing circuit receiving the first clock signal, for providing a second clock signal with a frequency that is lower than the predetermined frequency of the first clock signal; and a frequency multiplier circuit receiving the second clock signal, for providing a system clock signal resuming the predetermined frequency to a load.

Abstract: A pulsed flip-flop capable of adjusting a pulse width according to an operating voltage includes: a flip-flop operating in synchronization with a pulse signal; a pulse generating circuit generating the pulse signal in response to a clock signal; and a pulse width control circuit reducing a width of the pulse signal generated by the pulse generating circuit when the operating voltage is lower than a reference voltage.

Abstract: A phase conjugation vectoring (PCV) of signals propagating in telephone cables of twisted pairs provides crosstalk free transmission therethrough. The cable is considered a non-uniform physical media, and criteria for phase conjugation of electromagnetic fields are established. Method and system provide PCV for both asymmetric and symmetric transmission.

Abstract: A clock distribution network, structure, and method for providing balanced loading is disclosed. In particular, a clock distribution network may be formed of one or more clock fanout distribution levels. Each respective distribution level may include an equal number of buffer circuits and wiring routes that have substantially identical physical and electrical properties. Additionally, a final distribution level may include wiring routes that have substantially identical physical and electrical properties connecting buffer circuits to one or more logic leaf connection nodes.

Abstract: A circuit for pre-emphasis in data serialization. The circuit has a signal delayline to incrementally delay a serialized signal, producing a delayed serialized signal. The circuit has a one bit generator circuit, which determines the interval between receipt of one bit and a second bit. The one bit generator circuit has a strobe delayline to incrementally delay a strobe signal, producing a delayed strobe signal, a logical gate to compare the delayed strobe signal with a second strobe signal, and a logical component to determine how long the delayed strobe signal was delayed before it matched the second strobe signal. The circuit also has a comparison gate to detect transition points in the serialized signal by comparing the delayed serialized signal with the serialized signal. The circuit also has a current source to provide increased current for the serialized signal at the detected transition points.

Abstract: A synchronous memory device having an output driver controller, comprises a DLL circuit for receiving an external clock and outputting an internal clock; an output driver for outputting data in synchronism with the internal clock; and an output driver controller for controlling operation of the output driver, wherein the output driver controller makes the output driver active after receiving from the DLL circuit a control signal indicating that the internal clock is locked and is in a stabilized state.

Abstract: The EMI-free planar inductor is the core technology of the green technology. The EMI-free planar inductor adopts the structure of the closed magnetic field flux IC inductor (CMFFICI). All the magnetic field being confined in a small volume. The magnetic field is parallel to the surface of the chip. The EMI-free planar inductor makes the on-chip LC tank having very high Q and saves a lot of energy. Combining with the gain-boost-Q technology, it makes the high performance Tales clock chip have the performance being comparable to the xtalchip. The xtalchip is the inductor being replaced with the crystal in the gain-boost Q resonator. Furthermore, the EMI-free planar inductor makes the highest power efficiency boost-buck converter and the on-chip spinning motor. It makes the PC laser TV projector being implementable. The PC laser TV projector is RGB full color for each pixel and having the fast object movement sensitivity and wide dynamic range for the light contrast.

Abstract: A high voltage, high speed, and high repetition rate pulse generator solves the high pulse repetition rate limitations associated with RF power amplifiers. The pulse generator employs resonant techniques to provide current limiting features that allow for continued high voltage, high speed, and high repetition pulse rate operation of the pulse generator without impairment of the pulse generator during both short circuit and open circuit load conditions.

Abstract: A spread spectrum clock generator for sequentially modulating a source clock of a fixed frequency with a predetermined frequency range, including: a plurality of first loading units configured to delay clock edges of the source clock by a delay time corresponding to the number of unit delay steps determined by delay step control signals, wherein each of the first loading units comprises a plurality of second loading units each of which is configured to vary a delay value of each unit delay step by changing an inner interconnection configuration thereof in response to unit delay step control signals.

Abstract: A pulse generating circuit includes a plurality of delay elements cascaded so as to constitute a predetermined loop, wherein when a predetermined input pulse is supplied to a leading end of the series connection, an effective frequency multiplication is applied to signals which appear at a plurality of portions out of the node portions among the plurality of delay elements and the terminal end portion of the series connection by a logical circuit to obtain an output pulse having a higher frequency than the input pulse.

Abstract: The method involves detecting a first signal characterized by a periodically occurring first event, detecting a second signal characterized by a periodically occurring second event, and based on both the detected first and second signals, generating a third signal characterized by a periodically occurring third event. The method also involves automatically adjusting the phase of the third signal so that the periodically occurring third event occurs at a predetermined location between the first and second events of the first and second signals.