Abstract: A signal processing circuit is proposed, which is intended to receive a pair of input signals Sp and Sn in phase opposition on two input terminals and to provide two pairs of output currents SIp and SIn in phase opposition on four output terminals. Each input signal Sp and Sn is amplified in an amplification unit LNAUp and LNAUn and subsequently split in a splitting unit SPLUp and SPLUn. The invention is such that each of the two splitting units SPLUp and SPLUn includes at least two branches, respectively BIp, BQp and BIn, BQn connected between said amplification unit, respectively LNAUp and LNAUn, and one of said output terminals, the four branches BIp, BQp and BIn and BQn each including at least an impedance, respectively RIp, RQp, RIn, RQn, having identical characteristics. Mixer circuits can be easily stacked with this signal processing circuit.

Abstract: A receiver of a high speed digital interface includes at least one differential amplifier, a pair of resistive elements, a current source and a pair of transistors. The differential amplifier receives a small differential signal at a pair of input terminals and outputs an amplified differential signal. Each of the resistive elements has one end coupled to one of the input terminals of the differential amplifier and the other end receiving a reference voltage. The pair of transistors has drains respectively coupled to the input terminals of the differential amplifier, sources commonly coupled to the current source and gates receiving a differential feedback signal derived from the amplified differential signal.

Abstract: A differential amplifier (1D) includes circuitry (5,R1,R2,52) coupling a common mode component of an input voltage (Vin+?Vin?) to a maximum voltage selector circuit (53) that produces an internal voltage (VRAIL-TOP) equal to the larger of a first supply voltage (VREG) and the common mode component. An input amplifier circuit (46) of the differential amplifier is powered by the internal voltage. The input voltage (Vin+?Vin?) is coupled to inputs (41A,B) of the input amplifier circuit (46). Outputs (64A,B) of the input amplifier circuit (46) are amplified by an output amplifier (50).

Abstract: A memory cell for storing a charge that gives rise to a cell voltage representing a bit value, the memory cell being capable of having the cell voltage boosted to a boost value at a time following reading of the stored charge. The memory cell includes a first capacitor connected between a first node and ground. A second capacitor is connected between a second node and ground, and a first switch is connected between the first node and the second node. A second switch and a third capacitor are connected in series between the first node and the second node, with a terminal of the second switch being connected to the first node, the common connection node of the second switch and the third capacitor comprising a third node. A third switch is connected between the third node and ground. In operation, in a first storage phase the first and third switches are closed and the second switch is open.

Abstract: In accordance with the teachings described herein, a digital video cable driver is provided that includes an input stage, an output stage and an amplification stage. The input stage converts a pair of differential input voltages into a control current. The output stage generates a digital output voltage for transmission over a cable. The amplification stage responds to the control current to control a voltage swing of the digital output voltage as a function of the control current. The amplification stage may include a transistor circuit that varies the digital output voltage in proportion to variations in the control current to cause the voltage swing, wherein the control current causes one or more transistors in the transistor circuit to remain in a saturated state during operation of the digital video cable driver.

Abstract: A switch fabric that carries analog differential signals is constructed from 2×2 switches. Each 2×2 switch has two differential inputs that are applied to two demultiplexers. Each 2×2 switch also has two differential outputs, each driven by an equalizing mux. Each demultiplexer has two amplifiers that drive intermediate differential signals to the two equalizing muxes. Each equalizing mux has two equalizers that receive the intermediate differential signals from the two demultiplexers. A select signal enables one equalizer but disables the other to select one of the two intermediate differential inputs. A combining amplifier receives differential outputs from both equalizers and generates a final differential output. R, C values in each equalizer can be adjusted to compensate for loading variations in the intermediate differential signals which can have different physical lengths in a switch fabric.

Abstract: A circuit for removing non-linearity produced when an amplifier includes a load that results in non-linear current levels is provided. The circuit includes a first transistor element being coupled to one of the differential inputs associated with the amplifier. A second transistor element is coupled to another of the differential inputs associated with the amplifier. The second transistor element is coupled to the current associated with the load. Current passing the collectors of the first and second transistors elements are arranged to be always equal so as to eliminate in the circuit the changes between the base currents of the second transistor element and first transistor element caused by the current associated with the load.

Abstract: A differential amplifier circuit has first and second transistors composing a differential pair; a first inductor connected between the output terminal of the first transistor and a power source; a second inductor connected between the output terminal of the second transistor and the power source; a first transmission gate connected in series with the first inductor; and a second transmission gate connected in series with the second inductor.

Abstract: disclosed herein are embodiments of a swing compensation scheme for compensating errors in a transmitter driver.

Abstract: An operational amplifier includes a differential amplifier circuit provided at an input stage and an amplifier circuit at a post stage. In the differential amplifier circuit, first and third bipolar transistors are PNP-type bipolar transistors and Darlington-connected. An inverting input terminal is connected to the base terminal of the first bipolar transistor. The first and third bipolar transistors and second and fourth bipolar transistors construct an input differential pair. First and second protection diodes are connected between the base terminals of the first and second bipolar transistors constructing the input differential pair and the ground potential, respectively. Each of the protection diodes is connected so that the cathode terminal is positioned on the base terminal side of the bipolar transistor, and the cathode terminal is positioned on the ground potential side.

Abstract: The present invention is intended to achieve a transconductance amplifier and a voltage/current converting method which can provide a sufficient amplitude and a high degree of design freedom. The method comprises the steps of converting a first voltage signal to a first current signal; converting a second voltage signal to a second current signal; obtaining the common-mode components of the first and second current signals; and subtracting the common-mode components from the first and second current signals to obtain third and fourth signals, and further, subtracting the fourth current signal from the third current signal to generate a first output, while subtracting the third current signal from the fourth current signal to generate a second output.

Abstract: A method and apparatus for reducing settling time of a switched capacitor amplifier. The method includes disconnecting first and second capacitors from an amplifier. When the first and second capacitors are disconnected from the amplifier, they are charged by respective first and second input signals. The apparatus includes a plurality of sampling capacitors, each configured to sample a respective one of a plurality of signals during a sampling phase, an amplifier, and a plurality of decoupling switches configured to isolate the sampling capacitors from the amplifier during the sampling phase and to connect the plurality of sampling capacitors to the amplifier during the amplifying phase.

Abstract: The invention relates to a receiver (1) comprising an amplifier (31-34) for amplifying an antenna signal, which amplifier (31-34) comprises an amplifier input (11a) and an amplifier output (12a,12b), the amplifier input (11a) being a single ended input for receiving the antenna signal, the amplifier output (12a, 12b) being a differential output, and the amplifier (31-34) comprising circuit (41,42) for reducing a common mode input impedance of the amplifier (31-34).

Abstract: A differential amplifier includes an input stage, a biasing unit and a load unit. The input stage receives a first phase signal and at least two phase signals among odd-numbered phase signals, wherein an average of phases of the at least two phase signals has a phase difference of substantially 180 degrees from the first phase signal. The biasing unit is coupled between the input stage and a first power voltage. The load unit is coupled between the input stage and a second power voltage, and configured to output a differential output signal based on differentially amplifying of the first phase signal and the at least two phase signals. Therefore, a duty cycle distortion in an output signal of a duty cycle correction circuit can be prevented.

Abstract: A voltage comparator contains low voltage devices (e.g., bipolar or MOS transistors) and high voltage devices (e.g., DMOS transistors). The low voltage devices, which cannot sustain a voltage greater than a relatively small range of variation that is substantially less than the range of potential variation of the input voltage, are connected in a differential amplifier configuration to perform precision differential measurements on the input voltage. The high voltage devices are interconnected with the low voltage devices in a manner that enables operating levels of the low voltage devices to move up/down, or ‘slide’, with variations in the input voltage, so that the low voltage devices are effectively immune to high levels of the input voltage.

Abstract: This disclosure relates to load compensating multi-stage amplifier structures at an output of one of the amplifier stages.

Abstract: In one system embodiment, the system is characterized by: a differential amplifier including but not limited to at least one amplifying transistor having an emitter coupled directly to a ground. In one embodiment of a method of making a system, the method is characterized by: operably coupling at least one amplifying transistor of a differential amplifier directly to a ground. In one embodiment of a method of driving a system, the method is characterized by: driving at least one amplifying transistor of a differential amplifier with an emitter-follower feedback loop. In one system embodiment, the system is characterized by: a differential amplifier including but not limited to a first amplifying transistor having a base operably coupled with a first emitter-follower feedback loop.

Abstract: A radio system for communication is provided that has a differential amplifier for amplifying a transmission frequency, particularly 2.4 GHz, wherein the differential amplifier has a first inductor, which is magnetically coupled to a second inductor, and a capacitor. The capacitor, the first inductor, and the second inductor are wired into a resonant circuit in such a way that the resonant circuit has a common-mode impedance for a common-mode signal and a push-pull impedance, different from the common-mode impedance, for the push-pull signal.

Abstract: A conventional driver circuit has difficulty in controlling output voltages such as an output amplitude and a middle voltage in a CML circuit. Furthermore, in another conventional driver circuit, a high level of an output voltage in the CML circuit is dropped from a power supply voltage. To solve these problems, disclosed is a driver circuit including: an amplitude converter which converts the amplitude of a differential output signal and outputs a differential output signal; an amplitude setting unit which sets the amplitude of the differential output signal; and a common voltage setting unit which sets a center potential of the amplitude of the differential output signal.

Abstract: Sharing one or more load inductors comprises receiving a first input signal at a first terminal of a first amplifier and amplifying the first input signal using the first amplifier. The first amplifier is coupled to one or more load inductors at a second terminal of the first amplifier and is coupled to one or more dedicated source inductors at a third terminal of the first amplifier. Also, a second input signal is received at a first terminal of a second amplifier amplifying the second input signal using the second amplifier. The second amplifier is coupled to the one or more load inductors at a second terminal of the second amplifier and is coupled to one or more dedicated source inductors at a third terminal of the second amplifier.

Abstract: A data input buffer in a semiconductor is capable of avoiding operation speed deterioration of the data input buffer due to the temperature condition or process characteristic. The data input buffer in a semiconductor device includes an input detecting unit for detecting logic level of input data by comparing the voltage level of the input data with a reference voltage, a current driving capability adjusting unit for adjusting current driving capability of the input detecting unit based on at least one of temperature condition and process characteristic, and a buffering unit for buffering the output signal from the input detecting unit.

Abstract: A parallel type analog-to-digital conversion circuit, including a reference signal generating portion and a comparison amplification portion, the comparison amplification portion including a plurality of amplifiers, input resetting switches, first sampling capacitors, second sampling capacitors, first sampling switches, and second sampling switches.

Abstract: A variable gain amplifier includes signal amplifying transistor and first and second gain control transistors at output and non-output sides, whose emitters are connected to collector of signal amplifying transistor. The amplifier includes non-output load provided between collector of second gain control transistor and a power source, and equal to output load connected between collector of first gain control transistor and the power source. The amplifier includes non-output side negative feedback path provided between collector of second gain control transistor and an input terminal of signal amplifying transistor, and formed in same circuit form with same circuit constant as a negative feedback path running from an output terminal of first gain control transistor to the input terminal. The amplifier includes current dividing circuit which divides biasing currents between the two paths to flow the currents at same ratio as the current division ratio between first and second gain control transistors.

Abstract: Provided is an amplifying circuit and display unit (for example, a liquid crystal display) which achieves reductions in an area and power consumption without needing to build up complicated logic, while maintaining properties, as compared with the existing amplifying circuit and display unit. In the amplifying circuit, a voltage follower is divided into components including an input stage amplifying part for high voltage, an input stage amplifying part for low voltage and multiple output stage amplifying parts. Without changing an input relationship between the input stage amplifying parts for high voltage and for low voltage, an output relationship between the multiple output stage amplifying parts is changed depending on a control signal. Additionally, when the input stage amplifying part and the output stage amplifying part form one amplifying part, the amplifying part is switched to form the voltage follower in response to switching operation.

Abstract: A balanced voltage amplifier is disclosed as comprising a single stage containing three pairs of vacuum tube triodes configured to amplify two input signals (+INPUT, ?INPUT) and to generate two output signals (+OUTPUT, ?OUTPUT). The balanced voltage amplifier offers high voltage gain, wide bandwidth and low output impedance. Local feedback may be applied between the outputs and the second pair of triodes. Overall feedback may be applied between the outputs and the first pair of triodes. If local or overall feedback is used, it will further broaden the bandwidth, lower the output impedance and improve the overall balancing.

Abstract: A system for processing a signal is provided. The system includes a differential amplifier receiving a radio-frequency input signal at a first differential input. A rectifying device such as a transistor has a control terminal that is coupled to an output of the differential amplifier and an output that is coupled to a second differential input of the differential amplifier. The second differential input of the differential amplifier receives a low frequency feedback signal from the output of the rectifying device, such as by damping the frequency response at the output of the rectifying device using a capacitor and a current source coupled to the output of the rectifying device.

Abstract: A low-cost integrated circuit is used as a secondary side constant voltage and constant current controller. The integrated circuit has four terminals and two amplifier circuits. A first amplifier circuit is used to sense a voltage on a FB terminal and in response to cause a first current to flow through an OPTO terminal. A second amplifier circuit is used to sense a voltage between a SENSE terminal and a SOURCE terminal and in response to cause a second current to flow through the same OPTO terminal. The FB terminal is used for output voltage feedback and is also used to supply power onto the integrated circuit. The SOURCE terminal is used for output current feedback and is also used as power supply return for the integrated circuit. The cost of the integrated circuit is reduced by having only four terminals.

Abstract: Methods and apparatuses for detecting digital signals in high speed signaling systems. In at least one embodiment, at least one received input signal is combined with a plurality of predetermined reference signals according to a plurality of prior digital signal output states to generate a signal for detecting a present digital signal output state. In one aspect of the invention, a method for determining a digital signal state in a differential signaling system includes: comparing a first differential input signal to a second differential input signal; determining a prior digital signal output state; comparing the first differential input signal to one of a first reference voltage and a second reference voltage; comparing the second differential input signal to one of the first reference voltage and the second reference voltage; and determining a present digital signal output state from the prior digital signal output state and from all of the comparisons.

Abstract: There is provided a radio frequency (RF) signal amplifying device consuming less power and operable at a high voltage in a PA driving amplifying apparatus applicable to a PA amplifying circuit which amplifies power of an RF signal. The RF signal amplifying device includes: a balun converting an unbalanced radio frequency signal into a balanced radio frequency signal; a primary amplifier differentially amplifying the balanced radio frequency signal from the balun; and at least one secondary amplifier secondarily and differentially amplifying the balanced radio frequency signal amplified from the primary amplifier.

Abstract: An amplifying circuit and an associated linearity improving method are provided to correct the AM to PM distortion of an amplifier, thereby improving the amplifier linearity. The amplifying circuit includes an amplifier and a correcting unit. The amplifier has a non-linear input capacitor. The correcting unit generates a correction signal according to an input signal of the amplifier, and performs an AM to PM correction according to the correction signal, thereby making the amplifier have an approximately linear equivalent input capacitor.

Abstract: PMOS transistors are interposed parallel to each other between a node, which is a first output part, and a power supply; and PMOS transistors are interposed in parallel to each other between a node, which is a second output part, and the power supply. Output voltages in time of a balanced state in which an input potential difference between an input voltage and a reference voltage is “0” are both set to a reference output common voltage by a replica circuit and a comparator. The reference output common voltage of the replica circuit is set so that the potential difference between the power supply voltage and the output common voltage becomes a value lower than a threshold voltage of the diode connected PMOS transistors.

Abstract: An amplifier comprises an input circuit that receives an input to the amplifier. A start-up circuit communicates with the input circuit, generates a start-up signal, and turns off the start-up signal when an output of the amplifier reaches a threshold voltage. The start-up circuit includes a first transistor having first and second terminals and a base terminal and a second transistor having first and second terminals and a base terminal. The base terminals of the first and second transistors receive a bias input, the first terminals of the first and second transistors communicate with each other and with a first current source, and the second terminals of the first and second transistors communicate with the input circuit.

Abstract: A receiver circuit includes an attenuator that receives a received signal and attenuates the received signal, a DC level shifter that shifts a DC level of an attenuated signal from the attenuator, an amplifier section that has frequency characteristics of a band-pass filter and amplifies a signal from the DC level shifter that has been shifted with respect to the DC level, and a control circuit that controls an attenuation of the attenuator based on a signal output from the amplifier section. The control circuit controls the attenuation of the attenuator by changing filter characteristics of the attenuator corresponding to an amplitude of the signal output from the amplifier section so that the signal output from the amplifier section has a constant amplitude even when an amplitude of the received signal has changed.

Abstract: An amplifier includes an amplification unit which amplify a first difference between first and second input signals, a second difference between second and third input signals and a third difference between third and first input signals by a differential mode gain, and amplify an average of the first, second and third input signal by a common mode gain, for outputting a first output signal corresponding to a sum of the amplified first difference and the amplified average, a second output signal corresponding to a sum of the amplified second difference and the amplified average, and a third output signal corresponding to a sum of the amplified third difference and amplified average; first, second; and a reduction circuit which reduces the common mode gain less than the differential mode gain.

Abstract: A photocurrent amplifier circuit is capable of selectively amplifying one or more of photocurrents which are respectively obtainable from plural receiving devices, and can be realized to have a small size. The photocurrent amplifier circuit includes: light receiving devices; amplifier devices associated with the light receiving devices; device selector switches which apply input voltages, which inactivate the amplifier devices, to the associated amplifier devices; and a differential amplifier circuit having an inverting input unit configured by the amplifier devices which are connected in parallel. The inputs of the amplifier devices and the output of the differential amplifier circuit are connected by gain resistances. The differential amplifier circuit amplifies, into voltage signals, photocurrents flowing from the light receiving devices which respectively associated with the gain resistances.

Abstract: A peak detector can advantageously increase its bandwidth, i.e. its charging and discharging speed, while minimizing the ripple of its output signal by sensing the charging current of a storage device. In response to that charging current, the peak detector can control a discharge current, thereby accelerating its response. For example, the peak detector can reduce a discharge current in response to an increased charging current (which indicates a charging phase) and increase the discharge current in response to a decreased charging current (which indicates a discharge phase).

Abstract: A low flicker noise operational amplifier comprises two circuit branches of the same topology and a plurality of current source pairs. For each current source pair, the two current sources are commutatively steered into the two circuit branches via two sets of differential pair in a manner controlled by a pair of complementary logical signal.

Abstract: An operational amplifier includes: a differential amplifier circuit configured to receive an inverting input voltage (VIN?) and a non-inverting input voltage (VIN+); and an auxiliary circuit for improving a slew rate of an output voltage of the differential amplifier circuit, wherein when a voltage difference between the inverting input voltage (VIN?) and the non-inverting input voltage (VIN+) is less than a predetermined small voltage difference, an output terminal of the auxiliary circuit is disconnected from an output terminal of the differential amplifier circuit, and when the voltage difference exceeds the predetermined small voltage difference so that a voltage waveform is shifted to at least one direction, the voltage shift is accelerated by receiving/transferring a current from/to the output terminal of the differential amplifier circuit toward a shifting direction of an output voltage of the differential amplifier circuit.

Abstract: Small-signal and other circuit design techniques realized by carbon nanotube field-effect transistors (CNFETs) to create analog electronics for analog signal handling, analog signal processing, and conversions between analog signals and digital signals. As the CNFETs exist and operate at nanoscale, they can be readily collocated or integrated into carbon nanotube sensing and transducing systems. Such collocation and integration is at, or adequately near, nanoscale.

Abstract: The present patent application comprises a linear transconductor having at least one input and at least one output, comprising a differential amplifier having a plurality of transistors and a plurality of inputs, wherein a difference of input signals is amplified, a cascode circuit having a plurality of transistors, wherein the transistors are operably connected to the differential amplifier, wherein reverse isolation between an input and an output of the linear transconductor is improved by decoupling the input and the output of the linear transconductor by mounting at least one transistor of the plurality of transistors of the cascode circuit as a common-gate stacked on the at least one transistor of the differential amplifier, an active load having a plurality of transistors operably connected between the cascode circuit and supply voltage, and an auxiliary device operably connected to the connection between the active load, the cascode device and ground.

Abstract: A differential cascode amplifier is disclosed that includes in each branch two transistors connected to form a cascode circuit, and has a cross-compensation (neutralization) with at least one pair of capacitors for compensating a parasitic capacitance of a transistor of each branch, wherein in each case, one capacitor of the pair is equal to the parasitic capacitance of the transistor of the associated branch.

Abstract: A differential circuit includes main transistors differentially coupled for converting differential input signals into main differential currents at output terminals. The differential circuit also includes compensation transistors coupled to the main transistors for converting the differential input signals into compensation differential currents at the output terminals. Each compensation differential current has an exponential current-voltage characteristic for improving linearity of the differential circuit.

Abstract: A quantizer is described for use in a flash analog to digital converter (ADC), which may be implemented as part of an integrated wireless transceiver or other highly integrated electrical circuit. The quantizer may be configured to operate within such a flash ADC in an accurate manner within a desired voltage range, while minimizing factors that may otherwise lead to errors in the analog-to-digital conversion process. For example, a comparator of the quantizer may be used that has properties that are particularly well-suited for such an environment, where such properties may include, for example, a relatively low input referred offset voltage that is associated with a preamplifier of the comparator.

Abstract: A transimpedance amplifier (TIA) with integrated filtering. A capacitance is integrated into the TIA and connected to the power supply and to an internal ground of the TIA. Noise on the power supply of the transimpedance amplifier is filtered by the capacitor such that the power supply noise is reduced. The integrated capacitor also reduces noise ground. The integrated capacitor also reduces the effects of common mode noise that may be received from another circuit.

Abstract: An output buffer circuit includes an input stage of which one end receives an input voltage and the other end receives an output voltage; a class AB output stage that increases a current flowing in the output stage when the difference between the input and output voltages is larger than 0; a floating current source that biases the class AB output stage; a summing circuit that is connected to the input stage, the floating current source, and the class AB output stage so as to sum up the current supplied from the input stage and the internal current supplied from the floating current source; and an offset compensating circuit that is connected to the input stage and is composed of a plurality of switching elements and resistors so as to detect an offset voltage to compensate.

Abstract: A constant ratio current source comprises a first current branch which includes a first transistor that conducts a current I1 from a first current input to a first node and a resistor R1 connected between the first node and a circuit common point, and a second current branch which includes a second transistor that conducts a current I2 from a second current input to a second node and a resistor R2 connected between the second node and the circuit common point. The current branches are arranged such that I2 varies with I1. A linear negative resistance circuit connected between the first and second nodes provides an apparent negative resistance that increases the differential output impedance at the first and second current inputs, such that the ratio of I2:I1 is maintained approximately constant for a varying differential voltage applied across the first and second current inputs.

Abstract: A multi-band integrated circuit radio transceiver comprising receive and transmit radio front end circuit blocks further includes a local oscillation generator for generating a local oscillation for use by the receive and transmit radio front end circuit blocks to down convert received RF signals to baseband or low intermediate frequency signals and for use by the transmit front end circuit blocks to up-convert outgoing communication signals to RF, respectively. The transceiver further includes at least one buffering element coupled disposed in the local oscillation path that produces a buffered oscillation based upon the local oscillation to at least one front end circuit block wherein the buffering element includes a differentially arranged amplifier stage having a load and a cross-coupled capacitive element coupled between input and output nodes of the amplifier stage and at least one of an inductive device or a selectable capacitive device.

Abstract: An amplifier circuit includes an pair of input transistors, the drains of which are connected to emitters of first and second cascode transistors. First and second controlled current sources are connected to the emitters of the first and second cascode transistors, respectively, and third and fourth controlled current sources are connected to the collectors thereof. A bias circuit controls the 4 controlled current sources in response to the emitter voltage of a pair of input transistors of an output stage the inputs of which are connected to the drains of the first and second cascode transistors.

Abstract: Control structures are provided to accurately maintain amplifier common-mode levels at the predetermined level of a common-mode reference voltage Vcm. The disclosed control structures provide amplifier feedback along a first feedback path that is configured to provide high gain and low bandwidth to closely maintain amplifier common-mode level at the predetermined level of a common-mode reference voltage Vcm. They also provide amplifier feedback along a second feedback path that is configured to provide wide bandwidth to substantially reduce perturbations of the common-mode level that would have otherwise been induced by input signal transients. In an important amplifier feature, these controls are obtained without use of structures (e.g., capacitors and switching transistors) that use substantial current which reduces amplifier efficiency.

Abstract: A first differential pair and a second differential pair each receive differential input signals. The first differential pair and the second differential pair are connected such that the second differential pair receives part of a tail current of the first differential pair, and such that output signals of the first differential pair and output signals of the second differential pair cancel each other. A constant current source supplies the tail current to the first differential pair. A transistor which functions as a variable current source is connected between a current path and the second differential pair, and supplies a current drawn from the current path to the second differential pair, the current path connecting the first differential pair and the constant current source.