Abstract: A low voltage differential signalling driver is provided in which a first output node and a second output node provide a differential signal. First differential steering switch circuitry is switched in dependence on a differential input signal to selectively connect the first output node to a voltage supply via a current source, while second differential steering circuitry is switched in dependence on an inverse version of the differential input signal to connect the second output node to the voltage supply via the current source. Slew control circuitry is provided, configured to establish a current discharge path for the current source during the polarity transition of the differential input signal, thus maintaining a symmetric slew rate of the output signals at the first output node and second output node.

Abstract: The present invention relates to a large time constant steering circuit for slowly changing a voltage on a node between at least two discrete voltage levels. The present invention further relates to a slow steering current DAC comprising said large time constant steering circuit. The present invention further relates to an instrumentation amplifier device comprising a current balancing instrumentation amplifier for amplifying an input signal to an amplified output signal and a DC servo-loop for removing a DC-component from the input signal. The present invention further relates to an EEG acquisition ASIC comprising said instrumentation amplifier device.

Abstract: A comparator comprises a differential amplifier (T1, T2, T8, T9) having differential inputs (IN1, IN2) forming the comparator inputs, and a first and a second amplifier output (f1, f2) forming the comparator outputs of a first comparator stage, wherein the differential amplifier has first (T1, T8) and second (T2, T9) parallel branches. The comparator has a first current source circuit (32) defines a current to be driven through the differential amplifier, a second current source circuit (34) comprising a load driven by the first branch and a third current source circuit (36), comprising a load driven by the second branch. Circuitry (T6,T7) is provided for defining the voltage difference between the first and second amplifier outputs when the differential amplifier is in a stable state providing a differential output. This arrangement drives current through the two branches independently, so that the main transistors in each branch can be kept on to enable rapid response times.

Abstract: A temperature compensated low voltage reference circuit can be realized with a reduced operating voltage overhead and reduced spatial requirements This is accomplished in several ways including integrating one or more bipolar junction transistors into a current differencing amplifier and reducing the number of components required to implement various voltage reference circuits. All of the reference circuits may be constructed with various types of transistors including DTMOS transistors.

Abstract: A power amplifier comprises a plurality of primary inductors provided on a substrate in a circular geometry as a whole; a plurality of amplifier pairs; a secondary inductor; and a connection wiring. Each amplifier pair is coupled to two ends of a corresponding primary inductor, and amplifies and output to the corresponding primary inductor a pair of first and second signals given as differential input signals, respectively. The secondary inductor is provided adjacent to the primary inductors in a circular geometry, further combines and outputs signals made by combining first and second signals in each primary inductor. The connection wiring is provided inside the primary inductors on the substrate and electrically couples middle points of respective primary inductors with each other.

Abstract: An amplifier, which may be used in a pipelined analog-to-digital converter, includes a first amplifier stage driving a second amplifier stage. At least one compensation capacitor is coupled to provide negative feedback through the capacitor from the second amplifier stage to the first amplifier stage. The slew rate of the amplifier is enhanced by substantially reducing the negative feedback coupled through the capacitor during a period following the transition of a signal applied to an input terminal of the amplifier. If the first stage of the amplifier has complementary signal nodes, the negative feedback coupled through the capacitor may be reduced, for example, by closing a switch coupled between first and second complementary nodes of the first amplifier stage.

Abstract: A telescopic differential operational amplifier circuit for use in a pipelined A/D converter is provided with two auxiliary differential amplifiers connected to two cascode circuits, each including cascode-connected first to fourth transistors. During the sampling phase, first and second switches are turned on to apply a predetermined bias voltage to the gates of first and fourth transistors, and the input terminal of the differential operational amplifier circuit is set to a common mode voltage. During the hold phase, the first and second switches are turned off so that a voltage of each of the gates of the first and fourth transistors change to follow an input signal inputted via the input terminal with coupling capacitors operating as a level shifter of the input signal. Then the differential operational amplifier circuit performs push-pull operation operative only in a transconductance drive region, and is prevented from operating in a slewing region.

Abstract: A circuit in accordance with an embodiment of the present invention includes an instrumentation amplifier, a dynamically adjustable low pass filter, at least one monitor and a controller. The instrumentation amplifier includes a pair of buffered operational amplifiers that accept a pair of input signals, and a differential operational amplifier that outputs an output signal indicative of a difference between the pair of input signals. The dynamically adjustable low pass filter is configured to provide band limiting of the output signal at frequencies greater than a cutoff frequency. The monitor, or monitors, is/are configured to monitor a signal upstream of the instrumentation amplifier and/or a signal downstream of the instrumentation amplifier and output a monitor signal.

Abstract: A semiconductor integrated circuit, includes an operational amplifier including a first input terminal, a second input terminal, and an output terminal, a first transistor which has a source-drain route connected between an external terminal and a first voltage, and a gate terminal connected to the output terminal of the operational amplifier; and a second transistor which has a source-drain route connected between the first input terminal of the operational amplifier and the first voltage, and a gate terminal connected to the output terminal of the operational amplifier.

Abstract: A limiter for minimizing an amount of phase change caused by input amplitude variation includes a variable gain amplifier configured to receive a signal having an amplitude component and a phase component and having a gain controlled by a compensation capacitance and a variable resistance, in which the compensation capacitance minimizes an effect of parasitic capacitance and the variable resistance adjusts a gain in the variable gain amplifier such that the amplitude component at an output of the variable gain amplifier remains substantially constant.

Abstract: A dynamic flip-flop includes first and second input stages forming a differential input stage adapted to receive differential data. The flip-flop is reset in response to a reset signal. To ensure proper operation, a transistor disposed between the first and second input stages is always maintained active to provide a conduction path between the ground terminal and the nodes that may be charged from the supply voltage. To improve the setup and hold time of the flip-flop, the clock signal is applied to a first transistor disposed in the first input stage and a second transistor disposed in the second input stage.

Abstract: An operational amplifier is provide with: a first MOS transistor pair connected to a non-inverting input terminal and an inverting input terminal; an intermediate stage connected to the first MOS transistor pair connected to the first MOS transistor pair; a first output transistor having a drain connected to an output terminal; and a first source follower. The first source follower is inserted between a gate of the first output transistor and a first output node of the intermediate stage.

Abstract: A regulator circuit includes an output transistor that generates an output current in accordance with a control voltage that is applied to a control terminal of the output transistor. A differential amplifier provides feedback control of the control voltage in accordance with a level of the output current. A phase compensation circuit is connected to the differential amplifier and the control terminal of the output transistor. The phase compensation circuit adjusts an output impedance of the differential amplifier. The phase compensation circuit includes a variable resistor that decreases the output impedance of the differential amplifier when the output current increases.

Abstract: A transconductor circuit, particularly according to the multi-tanh principle, having a first input node and a second input node, a first differential amplifier coupled to the first and second input nodes, and having a first offset voltage, and a second differential amplifier coupled to the first and second input nodes, and having a second offset voltage different from the first offset voltage. A first resistance circuit is coupled between the first differential amplifier and at least one current source, and a second resistance circuit is coupled between the second differential amplifier and the at least one current source. Varying of the current sources enables control of the transconductance without degrading linearity.

Abstract: Mixer-systems comprising gain-blocks (1-4) and switches (5-8) have a flexibility depending upon their configuration (insight) and are made more flexible (basic idea) by supplying data input signals to the gain-blocks (1-4) and oscillation signals to the switches (5-6) for switching couplings between the gain-blocks (1-4). A switch (5-6) comprises a switch-transistor and a gain-block (1-4) either comprises a gain-block-transistor or comprises five gain-block-transistors for increasing the linearity of the mixer-system. The switches (5-6) have main electrodes which in the balanced situation are all coupled via four impedances (13-16) to the gain-blocks (1-4). In the single ended situation two main electrodes are coupled via two impedances (13,15,18,20) to the gain-blocks (1-4) and two others are coupled directly to the gain-blocks (1-4). By introducing further switches (7-8) parallel to the switches (5-6), harmonics can be suppressed.

Abstract: An output circuit that occupies a small area includes a control unit, X, Y, and Z axes amplification units, and first and second common circuits. The control unit outputs a temperature coefficient offset for correcting the temperature dependence of a sensor output. The first and second common circuits use the output from an acceleration sensor when performed amplification for each axis. In a reset phase, the charge accumulated in the first and second common circuits is released. In an amplification phase, the first and second common circuits and an operational amplifier uses the temperature coefficient offset voltage of each voltage to correct and amplify a signal from the acceleration sensor. In a hold phase, the accumulated charge is maintained in the same state to hold the output value of each axis.

Abstract: An integrated circuit (IC) for driving a light emitting semiconductor device is provided. The IC includes an input stage configured to receive a first input signal with a first differential pair of bipolar transistors and a second input signal with a second differential pair of bipolar transistors and to provide a pre-driver output signal being a superposition of the first input signal and the second input signal and an output stage including a third differential pair of bipolar transistors for receiving the pre-driver output signal of the input stage and for driving the light emitting semiconductor device in response to the pre-driver output signal, wherein the IC is configured to pre-distort the pre-driver output signal of the input stage so as to compensate a signal distortion of the output stage.

Abstract: A two stage fully differential amplifier has been designed which works, in tandem with a TX-FIR, as a linear equalizer at low frequencies, not covered by the TX-FIR, and also acts as a linear amplifier at higher frequencies which are equalized by the TX-FIR. The amplifier as a frequency response which does not attenuate signals frequencies less than one twentieth of baud rate, creates gain peaking ion the region between one twentieth and one tenth of baud rate and maintains flat peak gain up to half of baud rate. Different aspects of the frequency response curve (such as dc gain, max gain and zero frequency) are completely programmable. Also, the differential amplifier has been designed from low power and process, voltage and temperature insensitive frequency response.

Abstract: A signal level detector is disclosed, in which the noise tolerance of the signal detection is enhanced without increasing power consumption of the circuit. The signal detector includes two amplifiers, whose gain is fixed but different from each other, a switch to select the output of one of the amplifiers, a peak hold to hold the selected output and a comparator to compare the output of the peak hold with the level corresponding to loss-of-signal level. The switch responds to the compared result. In the invention, the two amplifiers have the same arrangement of the trans-conductance amplifier but only the resistance of the emitter coupling resistor is different.

Abstract: A differential amplifier circuit comprising a differential amplifier capacitor and a mismatch error cancellation circuitry, a first pair of capacitors, a second pair of capacitors consisting of switching network. The switching network is arranged to operate in a first configuration wherein the first pair of capacitors is operably coupled to differential inputs of the differential amplifier circuit. The switching network is further arranged to operate in second configuration wherein each capacitor of the first pair of capacitors is operably coupled within a feedback loop between an output and an input of the differential amplifier such that the differential amplifier outputs signals representative of the sampled input voltage signals, and the second pair of capacitors are operably coupled in parallel between the outputs of the differential amplifier such that the second pair of capacitors sample the voltage difference between the outputs.

Abstract: An electronic amplifier is characterized by a first stage (1) controlled by an input voltage UE, the operating voltage of said stage being on positive and/or negative potentials (V1+/V1A?), which are always constant with respect to the input voltage (UE), and further by a second impedance-converting stage (2), which is controlled by a voltage supplied by the first stage (1) and the operating voltage of which is on positive and/or negative potentials (V5+/V5A?), which are always constant with respect to the voltage supplied by the first stage (1).

Abstract: A driver circuit comprises: differential amplification stages connected in series, and at least two cross-point adjuster circuits respectively connected to at least two differential amplification stages of the differential amplification stages. The cross-point adjuster circuits control at least one of the positive-phase and negative-phase DC levels of a corresponding differential amplification stage and adjust the cross point of the output signals of the corresponding differential amplification stage.

Abstract: A transformer and a structure thereof and a power amplifier are provided. The transformer includes a first inductor to a fourth inductor, a first capacitor, and a second capacitor. A first terminal of the first inductor receives a first signal. A first terminal of the second inductor is coupled to the first terminal of the first inductor. A first terminal of the third inductor receives a second signal, and a second terminal of the third inductor is coupled to a second terminal of the first inductor. A first terminal of the fourth inductor is coupled to the first terminal of the third inductor. The first capacitor is coupled between the first terminal of the first inductor and the first terminal of the third inductor. The second capacitor is coupled between a second terminal of the second inductor and a second terminal of the forth inductor.

Abstract: An electrical circuit includes an amplifier. The amplifier includes an input circuit in communication with an input of the amplifier. A start-up circuit is in communication with the input circuit. The start-up circuit is configured to generate a start-up signal to enable subsequent operation of the amplifier. The start-up circuit turns off when an output of the amplifier reaches a threshold voltage. An output circuit is in communication with each of the outputs of the amplifier, the input circuit, and the start-up circuit.

Abstract: A transconductance cell includes a positive rail for providing a positive power supply voltage and a negative rail for providing a negative power supply voltage. A pair of voltage inputs, one inverting and one non-inverting, develop a differential voltage input signal having a common mode voltage range from one of the rail voltages to within a volt or less of the other rail voltage. And a pair of cross-coupled transconductor circuits each have: (i.) a source voltage follower responsive to one of the voltage inputs for sourcing relatively unbounded output current at unity voltage gain, (ii.) a sink voltage follower responsive to the other voltage input for sinking unbounded output current to a current output terminal, and (iii) a transconductance resistor connected between the source voltage follower and the sink voltage follower for developing a differential output current proportional to the differential voltage input signal.

Abstract: System and method for common mode translation in continuous-time sigma-delta analog-to-digital converters. An embodiment includes a loop filter having an RC network coupled to a differential signal input, a Gm-C/Quantizer/DAC circuit (GQD) coupled to the loop filter, a common-mode level adjust circuit coupled to signal inputs of the GQD, and a tuning circuit coupled to the GQD and the common-mode level adjust circuit. The GQD evaluates an input signal provided by the RC network, computes a difference between a filtered input signal and the feedback quantization signal to generate an error signal, measures the error signal, and compensates for the error signal with sigma-delta noise-shaping. The common-mode level adjust circuit alters a common-mode level of a differential input signal to be substantially equal to a desired common-mode level and the tuning circuit provides a compensation voltage to the common-mode level adjust circuit based on a difference between the common-mode levels.

Abstract: An error amplifier expected to exhibit rail-to-rail operation, high bandwidth, and high slew rate, is described, the error amplifier comprising a first stage to receive an input differential voltage and to provide transconductance gain, an intermediate stage to provide current gain, and an output stage to drive a load.

Abstract: An auxiliary power unit has a speed sensor for sensing a speed of operation of the auxiliary power unit. The speed sensor sends a signal to an electronic control box. The electronic control box is operable to control the auxiliary power unit. A branch line is for communicating the speed signal to a health monitoring system. The branch passes through an electronic component that will isolate the speed signal as it passes beyond the component and to the downstream use, such that corruption at a downstream use will not pass back upstream to corrupt the signals used in the electronic control box.

Abstract: An error amplifier expected to exhibit rail-to-rail operation, high bandwidth, and high slew rate, is described, the error amplifier comprising a first stage to receive an input differential voltage and to provide transconductance gain, an intermediate stage to provide current gain, and an output stage to drive a load.

Abstract: An error amplifier expected to exhibit rail-to-rail operation, high bandwidth, and high slew rate, is described, the error amplifier comprising a first stage to receive an input differential voltage and to provide transconductance gain, an intermediate stage to provide current gain, and an output stage to drive a load.

Abstract: An interface circuit for a multi-differential embedded-clock channel for communicating data provides efficient utilization of the bandwidth of the channel. The interface circuit includes at least four first signals, at least four second signals, and a multi-differential amplifier. The multi-differential amplifier is coupled to the first and second signals. The multi-differential amplifier is adapted to generate the second signals by amplifying, for all combinations of two of the first signals, differential transitions between the two of the first signals. Each of a plurality of symbols of the data has a corresponding one of the differential transitions, and the differential transitions are serially communicated through the channel.

Abstract: There is provided a transceiver comprising a first node for receiving a received signal and transmitting a transmitted signal; a receiver, connected between a first voltage and the first node, for processing the received signal; a transmitter, connected between a second voltage and the first node, for generating the transmitted signal; and a DC voltage controller for selecting a DC component of a voltage of the first node to at least one of: selectively activate at least one of the transmitter and the receiver; and selectively substantially deactivate at least one of the transmitter and receiver.

Abstract: The present invention relates to an integrated electrical circuit in particular a receiver or driver suitable for broadband communication, such as optical interconnect. The circuit comprises two amplifiers which share current supply wherein the integrated circuit is arranged so that cross talk via this current supply is avoided over a large range of frequencies.

Abstract: A balanced amplifier (1) is provided with: a first operational amplifier (11) whose reverse-phase input terminal is connected to an input voltage source (30) and whose reverse-phase input terminal is connected to an output terminal of the first operational amplifier; a second operational amplifier (12) whose positive-phase input terminal is connected to the input voltage source and whose reverse-phase input terminal is connected to an output terminal of the second operational amplifier; and a voltage division circuit (20i, 20j, 20k, 20l) for dividing a reference voltage supplied from a reference voltage source (40), the reference voltage source being connected to a positive-phase input terminal of each of the first operational amplifier and the operational amplifier through the voltage division circuit.

Abstract: An input stage receives a differential input signal at first and second input nodes and provides a differential output current at first and second output nodes. The differential output current includes a component taken from the input nodes through first and second impedances, and an additional component generated in response to a sample of the voltage of the differential input signal. A transconductance cell having cross-coupled inputs may generate the additional component of the output current.

Abstract: An RF power amplifier system adjusts the supply voltage to the power amplifier based upon an amplitude correction signal indicating the amplitude difference between the amplitude of the RF input signal and an attenuated amplitude of the RF output signal of the power amplifier. A variable gain amplifier (VGA) adjusts the amplitude of the RF input signal, thus providing a second means of adjusting the amplitude of the output of the power amplifier. The gain of the VGA or the supply voltage to the power amplifier is controlled based on the AC components of the amplitude correction signal, while the DC components of the amplitude correction signal are blocked from controlling the VGA or the supply voltage to the power amplifier. The DC level of the gain control of the VGA, the average supply voltage to the power amplifier, or the closed loop gain of the overall amplitude correction loop is controlled separately by a compression control signal.

Abstract: A buffer varies the size of its output stage in response to a varying capacitive load. The capacitive load may vary in a predictable or a random manner. The buffer includes an operational amplifier having an output stage of multiple transistors, selectively connected in parallel. During operation, data regarding the size of the capacitive load is obtained and used to determine the size of the output stage. In general, as the capacitive load increases, the number of transistors connected in parallel at the output stage also increases.

Abstract: A method and apparatus is provided for use in power amplifiers for reducing the peak voltage that transistors are subjected to. A power amplifier is provided with first and second switching devices and an inductor connected between the switching devices. The switching devices are driven such that the switching devices are turned on and off during the same time intervals. Differential RF power amplifiers are also provided with inductive networks coupled at various nodes of the power amplifiers. In some examples, techniques are used to stabilize differential power amplifiers by stabilizing common-mode feedback loops.

Abstract: A regulator for generating, from a first power supply voltage exceeding the breakdown voltage of a low voltage transistor block, a second power supply voltage lower than or equal to the breakdown voltage of the low voltage transistor block, includes an operational amplifier including low voltage transistors and high voltage transistors. An operational amplifier including only low voltage transistors can be employed.

Abstract: A bias circuit of a resistance load differential amplifier comprises a first differential pair and a control unit for controlling a tail current of the first differential pair, and making an output current of the first differential pair being in inverse proportion to a load resistance in the resistance load differential amplifier when applying a constant potential difference to an input of the first differential pair. The control unit further controls a tail current of a second differential pair constituting the resistance load differential amplifier, and makes the tail current of the second differential pair being in direct proportion to the tail current of the first differential pair.

Abstract: The invention relates to a receiver (1) comprising an amplifier (31-34) for amplifying an antenna signal, which amplifier (31-34) comprises an amplifier input (11a) and an amplifier output (12a, 12b), the amplifier input (11a) being a single ended input for receiving the antenna signal, the amplifier output (12a, 12b) being a differential output, and the amplifier (31-34) comprising a circuit (54) for compensating a series input impedance of the amplifier (31-34).

Abstract: An amplifier capable of operating in multiple modes may include (a) first and second voltage inputs and (b) first and second current outputs that have substantially the same amplitude and polarity. Preferably, the inputs and outputs of the amplifier will have high impedances. The amplifier may operate in a first mode—and function as an operational amplifier—when the first and second current outputs are coupled together. The amplifier may operate in a second mode—and function as a type-2 current conveyor—when the second current output is coupled to the second voltage input. The amplifier may additionally include a third current output that has an amplitude that is substantially the same as the amplitudes of the first and second outputs and a polarity that is substantially opposite to the polarities of the first and second outputs. In this configuration the amplifier may function as a four-terminal floating nullor.

Abstract: A plurality of inductors are connected in series between a load resistor and a first transistor, and a plurality of second transistors provided in parallel are connected to the plurality of inductors.

Abstract: A single stage differential amplifier is disclosed as comprising a pair of vacuum tube triodes for amplifying two input signals and generating two output signals. The differential amplifier has DC self-biasing ability and grid-to-cathode over-voltage protection for directly coupling from the outputs of another differential amplifier. By possessing these unique features, this differential amplifier becomes an important building block in forming a balanced amplifier by cascading multi differential amplifiers in a directly coupled fashion.

Abstract: A differential amplifier is constituted of first emitter-follower transistors, second emitter-follower transistors, and amplification transistors whose bases are alternately connected to the emitters of the second emitter-follower transistors and whose collectors are connected to the emitters of the first emitter-follower transistors, as well as emitter resistors and constant current sources, whereby it is possible to reduce distortions of output signals in response to large-amplitude input signals, thus ensuring high-speed operation. It is possible to further incorporate base-grounded transistors and diodes, by which substantially the same collector-emitter voltage is applied to the emitter-follower transistors and amplification transistors, thus achieving the same power consumption and the same temperature variations with respect to these transistors.

Abstract: The present invention provides a differential amplifier with a plurality of input pairs. The differential amplifier not only includes a differential amplifier with a single input pair but also includes a pair of transistors and a current source to provide the input signals of an extra input pair. The pair of transistors and the differential amplifier with a single input pair share a same load unit. In addition, by using control signals to control the on/off state of each current source, the input signals of the plurality of input pairs are switched, and thereby improve the signal quality. Thus, the need of an additional electrostatic discharge device (ESD device) may be avoided, and thereby reduce cost.

Abstract: A cross-differential amplifier is provided. The cross-differential amplifier includes an inductor connected to a direct current power source at a first terminal. A first and second switch, such as transistors, are connected to the inductor at a second terminal. A first and second amplifier are connected at their supply terminals to the first and second switch. The first and second switches are operated to commutate the inductor between the amplifiers so as to provide an amplified signal while limiting the ripple voltage on the inductor and thus limiting the maximum voltage imposed across the amplifiers and switches.

Abstract: A system for processing a signal is provided. The system includes a differential amplifier receiving a radio-frequency input signal at a first differential input. A rectifying device such as a transistor has a control terminal that is coupled to an output of the differential amplifier and an output that is coupled to a second differential input of the differential amplifier. The second differential input of the differential amplifier receives a low frequency feedback signal from the output of the rectifying device, such as by damping the frequency response at the output of the rectifying device using a capacitor and a current source coupled to the output of the rectifying device.

Abstract: A driver circuit comprises: differential amplification stages connected in series, and at least two cross-point adjuster circuits respectively connected to at least two differential amplification stages of the differential amplification stages. The cross-point adjuster circuits control at least one of the positive-phase and negative-phase DC levels of a corresponding differential amplification stage and adjust the cross point of the output signals of the corresponding differential amplification stage.

Abstract: A digital communication system for transmitting and receiving Digital Visual Interface (DVI) communication data signals and Display Data Channel (DDC) communication signals over a transmission line comprises an open-loop equalizer circuit and a DDC extension circuit. The open-loop equalizer circuit is operable to receive DVI communication signals transmitted over the transmission line and output equalized DVI communication data signals. The DDC extension circuit is operable to inject a boost current at the receive end of the transmission line during a positive transition in the DDC communication signal, and clamp the receive end of the transmission line during a negative transition of the DDC communication signal.